Commit 7d7f665d authored by Tony Lindgren's avatar Tony Lindgren

ARM: OMAP: Allow registering pin mux function

This patch changes pin multiplexing init to allow registering
custom function. The omap_cfg_reg() func will be split into
omap processor specific functions in later patch.

This is done to make adding omap3 pin multiplexing easier.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>

parent 672e302e
......@@ -32,6 +32,8 @@
#ifdef CONFIG_OMAP_MUX
static struct omap_mux_cfg arch_mux_cfg;
#ifdef CONFIG_ARCH_OMAP730
struct pin_config __initdata_or_module omap730_pins[] = {
MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0)
......@@ -310,18 +312,31 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
};
#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
{
return 0;
}
int __init omap1_mux_init(void)
{
#ifdef CONFIG_ARCH_OMAP730
omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins));
if (cpu_is_omap730()) {
arch_mux_cfg.pins = omap730_pins;
arch_mux_cfg.size = ARRAY_SIZE(omap730_pins);
arch_mux_cfg.cfg_reg = omap1_cfg_reg;
}
#endif
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins));
if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
arch_mux_cfg.pins = omap1xxx_pins;
arch_mux_cfg.size = ARRAY_SIZE(omap1xxx_pins);
arch_mux_cfg.cfg_reg = omap1_cfg_reg;
}
#endif
return 0;
return omap_mux_register(&arch_mux_cfg);
}
#endif
......@@ -32,6 +32,8 @@
#ifdef CONFIG_OMAP_MUX
static struct omap_mux_cfg arch_mux_cfg;
/* NOTE: See mux.h for the enumeration */
struct pin_config __initdata_or_module omap24xx_pins[] = {
......@@ -169,10 +171,25 @@ MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
};
int __init omap2_mux_init(void)
#ifdef CONFIG_ARCH_OMAP24XX
int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
{
omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
return 0;
}
#endif
int __init omap2_mux_init(void)
{
#ifdef CONFIG_ARCH_OMAP24XX
if (cpu_is_omap24xx()) {
arch_mux_cfg.pins = omap24xx_pins;
arch_mux_cfg.size = ARRAY_SIZE(omap24xx_pins);
arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
}
#endif
return omap_mux_register(&arch_mux_cfg);
}
#endif
......@@ -36,17 +36,17 @@
#define OMAP24XX_PULL_ENA (1 << 3)
#define OMAP24XX_PULL_UP (1 << 4)
static struct pin_config * pin_table;
static unsigned long pin_table_sz;
static struct omap_mux_cfg *mux_cfg;
extern struct pin_config * omap730_pins;
extern struct pin_config * omap1xxx_pins;
extern struct pin_config * omap24xx_pins;
int __init omap_mux_register(struct pin_config * pins, unsigned long size)
int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
{
pin_table = pins;
pin_table_sz = size;
if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
|| !arch_mux_cfg->cfg_reg) {
printk(KERN_ERR "Invalid pin table\n");
return -EINVAL;
}
mux_cfg = arch_mux_cfg;
return 0;
}
......@@ -64,17 +64,19 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
pull_orig = 0, pull = 0;
unsigned int mask, warn = 0;
if (!pin_table)
BUG();
if (mux_cfg == NULL) {
printk(KERN_ERR "Pin mux table not initialized\n");
return -ENODEV;
}
if (index >= pin_table_sz) {
if (index >= mux_cfg->size) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
index, pin_table_sz);
index, mux_cfg->size);
dump_stack();
return -ENODEV;
}
cfg = (struct pin_config *)&pin_table[index];
cfg = (struct pin_config *)&mux_cfg->pins[index];
if (cpu_is_omap24xx()) {
u8 reg = 0;
......
......@@ -559,11 +559,17 @@ enum omap24xx_index {
B13_24XX_KBC6,
};
struct omap_mux_cfg {
struct pin_config *pins;
unsigned long size;
int (*cfg_reg)(const struct pin_config *cfg);
};
#ifdef CONFIG_OMAP_MUX
/* setup pin muxing in Linux */
extern int omap1_mux_init(void);
extern int omap2_mux_init(void);
extern int omap_mux_register(struct pin_config * pins, unsigned long size);
extern int omap_mux_register(struct omap_mux_cfg *);
extern int omap_cfg_reg(unsigned long reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
......
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