Commit 7f03cebe authored by David Mosberger's avatar David Mosberger

ia64: Drop pci_sal_ext_{read,write}() and instead simply switch to

	extended config-space addresses when needed.  This avoids
	the fragile SAL version testing.
parent 7067d292
......@@ -53,56 +53,33 @@ struct pci_fixup pcibios_fixups[1];
* synchronization mechanism here.
*/
#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
((u64)(seg << 24) | (u64)(bus << 16) | \
#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
((u64)(seg << 24) | (u64)(bus << 16) | \
(u64)(devfn << 8) | (u64)(reg))
static int
pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
{
int result = 0;
u64 data = 0;
if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255))
return -EINVAL;
result = ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg, bus, devfn, reg), 0, len, &data);
*value = (u32) data;
return result;
}
static int
pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value)
{
if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255))
return -EINVAL;
return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg, bus, devfn, reg), 0, len, value);
}
static struct pci_raw_ops pci_sal_ops = {
.read = pci_sal_read,
.write = pci_sal_write
};
/* SAL 3.2 adds support for extended config space. */
#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
((u64)(seg << 28) | (u64)(bus << 20) | \
#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
((u64)(seg << 28) | (u64)(bus << 20) | \
(u64)(devfn << 12) | (u64)(reg))
static int
pci_sal_ext_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
{
u64 addr, mode, data = 0;
int result = 0;
u64 data = 0;
if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 4095))
return -EINVAL;
result = ia64_sal_pci_config_read(PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg), 1, len, &data);
if ((seg | reg) <= 255) {
addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
mode = 0;
} else {
addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
mode = 1;
}
result = ia64_sal_pci_config_read(addr, mode, len, &data);
*value = (u32) data;
......@@ -110,46 +87,42 @@ pci_sal_ext_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
}
static int
pci_sal_ext_write (int seg, int bus, int devfn, int reg, int len, u32 value)
pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value)
{
u64 addr, mode;
if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
return -EINVAL;
return ia64_sal_pci_config_write(PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg), 1, len, value);
}
static struct pci_raw_ops pci_sal_ext_ops = {
.read = pci_sal_ext_read,
.write = pci_sal_ext_write
};
struct pci_raw_ops *raw_pci_ops = &pci_sal_ops; /* default to SAL < 3.2 */
static int __init
pci_set_sal_ops (void)
{
if (sal_revision >= SAL_VERSION_CODE(3, 2)) {
printk("Using SAL 3.2 to access PCI config space\n");
raw_pci_ops = &pci_sal_ext_ops;
if ((seg | reg) <= 255) {
addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
mode = 0;
} else {
addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
mode = 1;
}
return 0;
return ia64_sal_pci_config_write(addr, mode, len, value);
}
arch_initcall(pci_set_sal_ops);
static struct pci_raw_ops pci_sal_ops = {
.read = pci_sal_read,
.write = pci_sal_write
};
struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
static int
pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
{
return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
devfn, where, size, value);
devfn, where, size, value);
}
static int
pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
{
return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
devfn, where, size, value);
devfn, where, size, value);
}
static struct pci_ops pci_root_ops = {
......
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