Commit 805afb69 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab

e752x_edac: provide more info about how DIMMS/ranks are mapped

No funtional changes here. Only the comments got updated.
Reviewed-by: default avatarAristeu Rozanski <arozansk@redhat.com>
Cc: Mark Gross <mark.gross@intel.com>
Cc: Doug Thompson <norsk5@yahoo.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 64e1fdaf
......@@ -4,10 +4,11 @@
* This file may be distributed under the terms of the
* GNU General Public License.
*
* See "enum e752x_chips" below for supported chipsets
* Implement support for the e7520, E7525, e7320 and i3100 memory controllers.
*
* Datasheet:
* Datasheets:
* http://www.intel.in/content/www/in/en/chipsets/e7525-memory-controller-hub-datasheet.html
* ftp://download.intel.com/design/intarch/datashts/31345803.pdf
*
* Written by Tom Zimmerman
*
......@@ -16,8 +17,6 @@
* Wang Zhenyu at intel.com
* Dave Jiang at mvista.com
*
* $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
*
*/
#include <linux/module.h>
......@@ -190,6 +189,25 @@ enum e752x_chips {
I3100 = 3
};
/*
* Those chips Support single-rank and dual-rank memories only.
*
* On e752x chips, the odd rows are present only on dual-rank memories.
* Dividing the rank by two will provide the dimm#
*
* i3100 MC has a different mapping: it supports only 4 ranks.
*
* The mapping is (from 1 to n):
* slot single-ranked double-ranked
* dimm #1 -> rank #4 NA
* dimm #2 -> rank #3 NA
* dimm #3 -> rank #2 Ranks 2 and 3
* dimm #4 -> rank $1 Ranks 1 and 4
*
* FIXME: The current mapping for i3100 considers that it supports up to 8
* ranks/chanel, but datasheet says that the MC supports only 4 ranks.
*/
struct e752x_pvt {
struct pci_dev *bridge_ck;
struct pci_dev *dev_d0f0;
......
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