PPC32: Use prepare target to make the assembler offsets header file.

This also puts the file in include/asm-ppc/offsets.h rather
than arch/ppc/kernel/asm-offsets.h.  This changes PPC to do things
similarly to other ports, and makes make -j work reliably.

arch/ppc/Makefile

@@ -81,13 +81,21 @@ $(BOOT_TARGETS): vmlinux
 	cp -f arch/ppc/configs/$(@:config=defconfig) .config
 
 archclean:
-	rm -f arch/ppc/kernel/{mk_defs,asm-offsets.h,find_name}
-	rm -f arch/ppc/iSeries/ReleaseData.h
 	@$(MAKEBOOT) clean
 
 archmrproper:
 
-prepare: checkbin
+prepare: include/asm-$(ARCH)/offsets.h checkbin
+
+arch/$(ARCH)/kernel/asm-offsets.s: include/asm include/linux/version.h \
+				   include/config/MARKER
+
+include/asm-$(ARCH)/offsets.h.tmp: arch/$(ARCH)/kernel/asm-offsets.s
+	@$(generate-asm-offsets.h) < $< > $@
+
+include/asm-$(ARCH)/offsets.h: include/asm-$(ARCH)/offsets.h.tmp
+	@echo -n '  Generating $@'
+	@$(update-if-changed)
 
 ifdef CONFIG_6xx
 # Ensure this is binutils 2.12.1 (or 2.12.90.0.7) or later
@@ -107,3 +115,8 @@ else
 checkbin:
 	@true
 endif
+
+CLEAN_FILES +=	include/asm-$(ARCH)/offsets.h.tmp \
+		include/asm-$(ARCH)/offsets.h \
+		arch/$(ARCH)/kernel/asm-offsets.s \
+		arch/$(ARCH)/iSeries/ReleaseData.h

arch/ppc/kernel/Makefile

@@ -89,23 +89,5 @@ obj-$(CONFIG_PPC_ISERIES)	+= iSeries_misc.o
 
 include $(TOPDIR)/Rules.make
 
-entry.o: entry.S asm-offsets.h
-misc.o: misc.S asm-offsets.h
-l2cr.o: l2cr.S asm-offsets.h
-head.o: head.S asm-offsets.h
-head_4xx.o: head_4xx.S asm-offsets.h
-head_8xx.o: head_8xx.S asm-offsets.h
-iSeries_head.o: iSeries_head.S asm-offsets.h
-iSeries_misc.o: iSeries_misc.S asm-offsets.h
-
-asm-offsets.h: mk_defs.c asm-offsets.head \
-		$(TOPDIR)/include/asm/mmu.h \
-		$(TOPDIR)/include/asm/processor.h \
-		$(TOPDIR)/include/asm/pgtable.h \
-		$(TOPDIR)/include/asm/ptrace.h
-	$(CC) $(CFLAGS) -S mk_defs.c
-	(cat asm-offsets.head; grep '^#define' mk_defs.s) >asm-offsets.h
-	rm mk_defs.s
-
 find_name : find_name.c
 	$(HOSTCC) $(HOSTCFLAGS) -o find_name find_name.c

arch/ppc/kernel/asm-offsets.head

-/*
- * WARNING! This file is automatically generated - DO NOT EDIT!
- */

arch/ppc/kernel/entry.S

@@ -30,7 +30,7 @@
 #include <asm/cputable.h>
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
-#include "asm-offsets.h"
+#include <asm/offsets.h>
 #ifdef	CONFIG_PPC_ISERIES
 #include "iSeries_asm.h"
 #endif /* CONFIG_PPC_ISERIES */

arch/ppc/kernel/head.S

@@ -31,7 +31,7 @@
 #include <asm/cache.h>
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
-#include "asm-offsets.h"
+#include <asm/offsets.h>
 
 #ifdef CONFIG_APUS
 #include <asm/amigappc.h>

arch/ppc/kernel/head_4xx.S

@@ -40,7 +40,7 @@
 #include <asm/cputable.h>
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
-#include "asm-offsets.h"
+#include <asm/offsets.h>
 
 /* As with the other PowerPC ports, it is expected that when code
  * execution begins here, the following registers contain valid, yet

arch/ppc/kernel/head_8xx.S

@@ -30,7 +30,7 @@
 #include <asm/cputable.h>
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
-#include "asm-offsets.h"
+#include <asm/offsets.h>
 
 	.text
 	.globl	_stext

arch/ppc/kernel/iSeries_head.S

@@ -32,7 +32,7 @@
 #include <asm/pgtable.h>
 #include <asm/ppc_asm.h>
 #include <asm/thread_info.h>
-#include "asm-offsets.h"
+#include <asm/offsets.h>
 #include "iSeries_asm.h"
 
 

arch/ppc/kernel/iSeries_misc.S

@@ -22,7 +22,7 @@
 #include <asm/page.h>
 #include <asm/cache.h>
 #include <asm/ppc_asm.h>
-#include "asm-offsets.h"
+#include <asm/offsets.h>
 #include "iSeries_asm.h"
 
 	.text

arch/ppc/kernel/misc.S

@@ -23,7 +23,7 @@
 #include <asm/mmu.h>
 #include <asm/ppc_asm.h>
 #include <asm/thread_info.h>
-#include "asm-offsets.h"
+#include <asm/offsets.h>
 
 	.text
 

arch/ppc/mm/hashtable.S

@@ -30,7 +30,7 @@
 #include <asm/cputable.h>
 #include <asm/ppc_asm.h>
 #include <asm/thread_info.h>
-#include "asm-offsets.h"
+#include <asm/offsets.h>
 
 #ifdef CONFIG_SMP
 	.comm	mmu_hash_lock,4
@@ -144,9 +144,7 @@ retry:
 #endif
 
 	/* Return from the exception */
-	lwz	r4,_LINK(r11)
 	lwz	r5,_CTR(r11)
-	mtlr	r4
 	mtctr	r5
 	lwz	r0,GPR0(r11)
 	lwz	r7,GPR7(r11)