Commit 81637a6e authored by Ankit Nautiyal's avatar Ankit Nautiyal Committed by Jani Nikula

drm/i915: Fix HAS_LSPCON macro for platforms between GEN9 and GEN10

Legacy LSPCON chip from MCA and Parade is only used for platforms
between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same.
Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210208055554.24357-1-ankit.k.nautiyal@intel.com
parent 714b1cdb
...@@ -1722,7 +1722,7 @@ tgl_stepping_get(struct drm_i915_private *dev_priv) ...@@ -1722,7 +1722,7 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) #define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10))
/* DPF == dynamic parity feature */ /* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
......
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