watchdog: renesas_wdt: apply better precision
The error margin of the clks_per_second variable was too large and caused offsets when used with clock frequencies which left a remainder after applying the dividers. Now we always calculate directly using the clock rate and the divider using some helper macros. That also means that DIV_ROUND_UP moves from probe to the multiplication macro. In probe, we don't need to ensure anymore that 'clks_per_sec' would go too fast but rather ensure that the lower limit is really at least 1 to certainly get a full cycle. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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