Commit 84bead6c authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Grant Likely

gpio/langwell: Clear edge bit before handling

I don't have the specs for this beast, but it looks a lot like the PXA
GPIO block. Though I bet it's the same IP and the driver should have
reused the PXA code.

Acknowleding the edge detect status after handling one or more gpio
interrupts looks wrong. We might lose an edge which came in while we
handled the previous one.
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarAlek Du <alek.du@intel.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
parent 732063b9
...@@ -190,23 +190,22 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc) ...@@ -190,23 +190,22 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
struct irq_data *data = irq_desc_get_irq_data(desc); struct irq_data *data = irq_desc_get_irq_data(desc);
struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data); struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
struct irq_chip *chip = irq_data_get_irq_chip(data); struct irq_chip *chip = irq_data_get_irq_chip(data);
u32 base, gpio, gedr_v; u32 base, gpio, mask;
unsigned long pending; unsigned long pending;
void __iomem *gedr; void __iomem *gedr;
/* check GPIO controller to check which pin triggered the interrupt */ /* check GPIO controller to check which pin triggered the interrupt */
for (base = 0; base < lnw->chip.ngpio; base += 32) { for (base = 0; base < lnw->chip.ngpio; base += 32) {
gedr = gpio_reg(&lnw->chip, base, GEDR); gedr = gpio_reg(&lnw->chip, base, GEDR);
gedr_v = pending = readl(gedr); pending = readl(gedr);
if (!gedr_v)
continue;
while (pending) { while (pending) {
gpio = __ffs(pending) - 1; gpio = __ffs(pending) - 1;
pending &= ~BIT(gpio); mask = BIT(gpio);
pending &= ~mask;
/* Clear before handling so we can't lose an edge */
writel(mask, gedr);
generic_handle_irq(lnw->irq_base + base + gpio); generic_handle_irq(lnw->irq_base + base + gpio);
} }
/* clear the edge detect status bit */
writel(gedr_v, gedr);
} }
chip->irq_eoi(data); chip->irq_eoi(data);
......
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