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Commit 87744403 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/fifo: switch to device pri macros 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 2fde1f1c
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Showing with 345 additions and 289 deletions
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
View file @ 87744403
......@@ -80,10 +80,11 @@ static int
g84_fifo_context_detach(struct nvkm_object *parent, bool suspend,
struct nvkm_object *object)
{
struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo *fifo = (void *)parent->engine;
struct nv50_fifo_base *base = (void *)parent->parent;
struct nv50_fifo_chan *chan = (void *)parent;
struct nvkm_device *device = fifo->base.engine.subdev.device;
struct nvkm_bar *bar = device->bar;
u32 addr, save, engn;
bool done;
......@@ -103,10 +104,10 @@ g84_fifo_context_detach(struct nvkm_object *parent, bool suspend,
return -EINVAL;
}
save = nv_mask(fifo, 0x002520, 0x0000003f, 1 << engn);
nv_wr32(fifo, 0x0032fc, nv_gpuobj(base)->addr >> 12);
save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn);
nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12);
done = nv_wait_ne(fifo, 0x0032fc, 0xffffffff, 0xffffffff);
nv_wr32(fifo, 0x002520, save);
nvkm_wr32(device, 0x002520, save);
if (!done) {
nv_error(fifo, "channel %d [%s] unload timeout\n",
chan->base.chid, nvkm_client_name(chan));
......@@ -313,6 +314,7 @@ g84_fifo_chan_init(struct nvkm_object *object)
struct nv50_fifo_base *base = (void *)object->parent;
struct nv50_fifo_chan *chan = (void *)object;
struct nvkm_gpuobj *ramfc = base->ramfc;
struct nvkm_device *device = fifo->base.engine.subdev.device;
u32 chid = chan->base.chid;
int ret;
......@@ -320,7 +322,7 @@ g84_fifo_chan_init(struct nvkm_object *object)
if (ret)
return ret;
nv_wr32(fifo, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
nv50_fifo_playlist_update(fifo);
return 0;
}
......@@ -422,14 +424,16 @@ static void
g84_fifo_uevent_init(struct nvkm_event *event, int type, int index)
{
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
nv_mask(fifo, 0x002140, 0x40000000, 0x40000000);
struct nvkm_device *device = fifo->engine.subdev.device;
nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
}
static void
g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
{
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
nv_mask(fifo, 0x002140, 0x40000000, 0x00000000);
struct nvkm_device *device = fifo->engine.subdev.device;
nvkm_mask(device, 0x002140, 0x40000000, 0x00000000);
}
static const struct nvkm_event_func
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
View file @ 87744403
......@@ -177,29 +177,30 @@ static int
nv17_fifo_init(struct nvkm_object *object)
{
struct nv04_fifo *fifo = (void *)object;
struct nvkm_device *device = fifo->base.engine.subdev.device;
int ret;
ret = nvkm_fifo_init(&fifo->base);
if (ret)
return ret;
nv_wr32(fifo, NV04_PFIFO_DELAY_0, 0x000000ff);
nv_wr32(fifo, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
nv_wr32(fifo, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((fifo->ramht->bits - 9) << 16) |
(fifo->ramht->gpuobj.addr >> 8));
nv_wr32(fifo, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8);
nv_wr32(fifo, NV03_PFIFO_RAMFC, fifo->ramfc->addr >> 8 | 0x00010000);
nvkm_wr32(device, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8);
nvkm_wr32(device, NV03_PFIFO_RAMFC, fifo->ramfc->addr >> 8 | 0x00010000);
nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max);
nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max);
nv_wr32(fifo, NV03_PFIFO_INTR_0, 0xffffffff);
nv_wr32(fifo, NV03_PFIFO_INTR_EN_0, 0xffffffff);
nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, 1);
nv_wr32(fifo, NV04_PFIFO_CACHE1_PULL0, 1);
nv_wr32(fifo, NV03_PFIFO_CACHES, 1);
nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View file @ 87744403
......@@ -105,6 +105,7 @@ nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx)
{
struct nv04_fifo *fifo = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
struct nvkm_device *device = fifo->base.engine.subdev.device;
unsigned long flags;
u32 reg, ctx;
......@@ -125,13 +126,13 @@ nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx)
spin_lock_irqsave(&fifo->base.lock, flags);
nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;
nv_mask(fifo, 0x002500, 0x00000001, 0x00000000);
nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);
if ((nv_rd32(fifo, 0x003204) & fifo->base.max) == chan->base.chid)
nv_wr32(fifo, reg, nv_engctx(engctx)->addr);
if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid)
nvkm_wr32(device, reg, nv_engctx(engctx)->addr);
nv_wo32(fifo->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);
nv_mask(fifo, 0x002500, 0x00000001, 0x00000001);
nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&fifo->base.lock, flags);
return 0;
}
......@@ -142,6 +143,7 @@ nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend,
{
struct nv04_fifo *fifo = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
struct nvkm_device *device = fifo->base.engine.subdev.device;
unsigned long flags;
u32 reg, ctx;
......@@ -161,13 +163,13 @@ nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend,
}
spin_lock_irqsave(&fifo->base.lock, flags);
nv_mask(fifo, 0x002500, 0x00000001, 0x00000000);
nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);
if ((nv_rd32(fifo, 0x003204) & fifo->base.max) == chan->base.chid)
nv_wr32(fifo, reg, 0x00000000);
if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid)
nvkm_wr32(device, reg, 0x00000000);
nv_wo32(fifo->ramfc, chan->ramfc + ctx, 0x00000000);
nv_mask(fifo, 0x002500, 0x00000001, 0x00000001);
nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&fifo->base.lock, flags);
return 0;
}
......@@ -295,51 +297,52 @@ static int
nv40_fifo_init(struct nvkm_object *object)
{
struct nv04_fifo *fifo = (void *)object;
struct nvkm_fb *fb = nvkm_fb(object);
struct nvkm_device *device = fifo->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
int ret;
ret = nvkm_fifo_init(&fifo->base);
if (ret)
return ret;
nv_wr32(fifo, 0x002040, 0x000000ff);
nv_wr32(fifo, 0x002044, 0x2101ffff);
nv_wr32(fifo, 0x002058, 0x00000001);
nvkm_wr32(device, 0x002040, 0x000000ff);
nvkm_wr32(device, 0x002044, 0x2101ffff);
nvkm_wr32(device, 0x002058, 0x00000001);
nv_wr32(fifo, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((fifo->ramht->bits - 9) << 16) |
(fifo->ramht->gpuobj.addr >> 8));
nv_wr32(fifo, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8);
nvkm_wr32(device, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8);
switch (nv_device(fifo)->chipset) {
case 0x47:
case 0x49:
case 0x4b:
nv_wr32(fifo, 0x002230, 0x00000001);
nvkm_wr32(device, 0x002230, 0x00000001);
case 0x40:
case 0x41:
case 0x42:
case 0x43:
case 0x45:
case 0x48:
nv_wr32(fifo, 0x002220, 0x00030002);
nvkm_wr32(device, 0x002220, 0x00030002);
break;
default:
nv_wr32(fifo, 0x002230, 0x00000000);
nv_wr32(fifo, 0x002220, ((fb->ram->size - 512 * 1024 +
nvkm_wr32(device, 0x002230, 0x00000000);
nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 +
fifo->ramfc->addr) >> 16) |
0x00030000);
break;
}
nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max);
nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max);
nv_wr32(fifo, NV03_PFIFO_INTR_0, 0xffffffff);
nv_wr32(fifo, NV03_PFIFO_INTR_EN_0, 0xffffffff);
nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, 1);
nv_wr32(fifo, NV04_PFIFO_CACHE1_PULL0, 1);
nv_wr32(fifo, NV03_PFIFO_CACHES, 1);
nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
View file @ 87744403
......@@ -41,7 +41,8 @@
static void
nv50_fifo_playlist_update_locked(struct nv50_fifo *fifo)
{
struct nvkm_bar *bar = nvkm_bar(fifo);
struct nvkm_device *device = fifo->base.engine.subdev.device;
struct nvkm_bar *bar = device->bar;
struct nvkm_gpuobj *cur;
int i, p;
......@@ -49,15 +50,15 @@ nv50_fifo_playlist_update_locked(struct nv50_fifo *fifo)
fifo->cur_playlist = !fifo->cur_playlist;
for (i = fifo->base.min, p = 0; i < fifo->base.max; i++) {
if (nv_rd32(fifo, 0x002600 + (i * 4)) & 0x80000000)
if (nvkm_rd32(device, 0x002600 + (i * 4)) & 0x80000000)
nv_wo32(cur, p++ * 4, i);
}
bar->flush(bar);
nv_wr32(fifo, 0x0032f4, cur->addr >> 12);
nv_wr32(fifo, 0x0032ec, p);
nv_wr32(fifo, 0x002500, 0x00000101);
nvkm_wr32(device, 0x0032f4, cur->addr >> 12);
nvkm_wr32(device, 0x0032ec, p);
nvkm_wr32(device, 0x002500, 0x00000101);
}
void
......@@ -102,10 +103,11 @@ static int
nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend,
struct nvkm_object *object)
{
struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo *fifo = (void *)parent->engine;
struct nv50_fifo_base *base = (void *)parent->parent;
struct nv50_fifo_chan *chan = (void *)parent;
struct nvkm_device *device = fifo->base.engine.subdev.device;
struct nvkm_bar *bar = device->bar;
u32 addr, me;
int ret = 0;
......@@ -129,17 +131,17 @@ nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend,
* there's also a "ignore these engines" bitmask reg we can use
* if we hit the issue there..
*/
me = nv_mask(fifo, 0x00b860, 0x00000001, 0x00000001);
me = nvkm_mask(device, 0x00b860, 0x00000001, 0x00000001);
/* do the kickoff... */
nv_wr32(fifo, 0x0032fc, nv_gpuobj(base)->addr >> 12);
nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12);
if (!nv_wait_ne(fifo, 0x0032fc, 0xffffffff, 0xffffffff)) {
nv_error(fifo, "channel %d [%s] unload timeout\n",
chan->base.chid, nvkm_client_name(chan));
if (suspend)
ret = -EBUSY;
}
nv_wr32(fifo, 0x00b860, me);
nvkm_wr32(device, 0x00b860, me);
if (ret == 0) {
nv_wo32(base->eng, addr + 0x00, 0x00000000);
......@@ -324,6 +326,7 @@ nv50_fifo_chan_init(struct nvkm_object *object)
struct nv50_fifo_base *base = (void *)object->parent;
struct nv50_fifo_chan *chan = (void *)object;
struct nvkm_gpuobj *ramfc = base->ramfc;
struct nvkm_device *device = fifo->base.engine.subdev.device;
u32 chid = chan->base.chid;
int ret;
......@@ -331,7 +334,7 @@ nv50_fifo_chan_init(struct nvkm_object *object)
if (ret)
return ret;
nv_wr32(fifo, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
nv50_fifo_playlist_update(fifo);
return 0;
}
......@@ -341,12 +344,13 @@ nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_fifo *fifo = (void *)object->engine;
struct nv50_fifo_chan *chan = (void *)object;
struct nvkm_device *device = fifo->base.engine.subdev.device;
u32 chid = chan->base.chid;
/* remove channel from playlist, fifo will unload context */
nv_mask(fifo, 0x002600 + (chid * 4), 0x80000000, 0x00000000);
nvkm_mask(device, 0x002600 + (chid * 4), 0x80000000, 0x00000000);
nv50_fifo_playlist_update(fifo);
nv_wr32(fifo, 0x002600 + (chid * 4), 0x00000000);
nvkm_wr32(device, 0x002600 + (chid * 4), 0x00000000);
return nvkm_fifo_channel_fini(&chan->base, suspend);
}
......@@ -498,27 +502,28 @@ int
nv50_fifo_init(struct nvkm_object *object)
{
struct nv50_fifo *fifo = (void *)object;
struct nvkm_device *device = fifo->base.engine.subdev.device;
int ret, i;
ret = nvkm_fifo_init(&fifo->base);
if (ret)
return ret;
nv_mask(fifo, 0x000200, 0x00000100, 0x00000000);
nv_mask(fifo, 0x000200, 0x00000100, 0x00000100);
nv_wr32(fifo, 0x00250c, 0x6f3cfc34);
nv_wr32(fifo, 0x002044, 0x01003fff);
nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
nvkm_wr32(device, 0x00250c, 0x6f3cfc34);
nvkm_wr32(device, 0x002044, 0x01003fff);
nv_wr32(fifo, 0x002100, 0xffffffff);
nv_wr32(fifo, 0x002140, 0xbfffffff);
nvkm_wr32(device, 0x002100, 0xffffffff);
nvkm_wr32(device, 0x002140, 0xbfffffff);
for (i = 0; i < 128; i++)
nv_wr32(fifo, 0x002600 + (i * 4), 0x00000000);
nvkm_wr32(device, 0x002600 + (i * 4), 0x00000000);
nv50_fifo_playlist_update_locked(fifo);
nv_wr32(fifo, 0x003200, 0x00000001);
nv_wr32(fifo, 0x003250, 0x00000001);
nv_wr32(fifo, 0x002500, 0x00000001);
nvkm_wr32(device, 0x003200, 0x00000001);
nvkm_wr32(device, 0x003250, 0x00000001);
nvkm_wr32(device, 0x002500, 0x00000001);
return 0;
}
......
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