Commit 897eba82 authored by Michel Dänzer's avatar Michel Dänzer Committed by Alex Deucher

drm/radeon: Disable HDP flush before every CS again for < r600

It was causing display corruption with R300 generation GPUs at least.
Reported-and-Tested-by: default avatarMikael Pettersson <mikpelinux@gmail.com>
Signed-off-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64d8ee59
...@@ -821,6 +821,20 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) ...@@ -821,6 +821,20 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
return RREG32(RADEON_CRTC2_CRNT_FRAME); return RREG32(RADEON_CRTC2_CRNT_FRAME);
} }
/**
* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
* rdev: radeon device structure
* ring: ring buffer struct for emitting packets
*/
static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
{
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
RADEON_HDP_READ_BUFFER_INVALIDATE);
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
}
/* Who ever call radeon_fence_emit should call ring_lock and ask /* Who ever call radeon_fence_emit should call ring_lock and ask
* for enough space (today caller are ib schedule and buffer move) */ * for enough space (today caller are ib schedule and buffer move) */
void r100_fence_ring_emit(struct radeon_device *rdev, void r100_fence_ring_emit(struct radeon_device *rdev,
...@@ -1056,20 +1070,6 @@ void r100_gfx_set_wptr(struct radeon_device *rdev, ...@@ -1056,20 +1070,6 @@ void r100_gfx_set_wptr(struct radeon_device *rdev,
(void)RREG32(RADEON_CP_RB_WPTR); (void)RREG32(RADEON_CP_RB_WPTR);
} }
/**
* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
* rdev: radeon device structure
* ring: ring buffer struct for emitting packets
*/
void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
{
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
RADEON_HDP_READ_BUFFER_INVALIDATE);
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
}
static void r100_cp_load_microcode(struct radeon_device *rdev) static void r100_cp_load_microcode(struct radeon_device *rdev)
{ {
const __be32 *fw_data; const __be32 *fw_data;
......
...@@ -185,7 +185,6 @@ static struct radeon_asic_ring r100_gfx_ring = { ...@@ -185,7 +185,6 @@ static struct radeon_asic_ring r100_gfx_ring = {
.get_rptr = &r100_gfx_get_rptr, .get_rptr = &r100_gfx_get_rptr,
.get_wptr = &r100_gfx_get_wptr, .get_wptr = &r100_gfx_get_wptr,
.set_wptr = &r100_gfx_set_wptr, .set_wptr = &r100_gfx_set_wptr,
.hdp_flush = &r100_ring_hdp_flush,
}; };
static struct radeon_asic r100_asic = { static struct radeon_asic r100_asic = {
...@@ -332,7 +331,6 @@ static struct radeon_asic_ring r300_gfx_ring = { ...@@ -332,7 +331,6 @@ static struct radeon_asic_ring r300_gfx_ring = {
.get_rptr = &r100_gfx_get_rptr, .get_rptr = &r100_gfx_get_rptr,
.get_wptr = &r100_gfx_get_wptr, .get_wptr = &r100_gfx_get_wptr,
.set_wptr = &r100_gfx_set_wptr, .set_wptr = &r100_gfx_set_wptr,
.hdp_flush = &r100_ring_hdp_flush,
}; };
static struct radeon_asic r300_asic = { static struct radeon_asic r300_asic = {
......
...@@ -148,8 +148,7 @@ u32 r100_gfx_get_wptr(struct radeon_device *rdev, ...@@ -148,8 +148,7 @@ u32 r100_gfx_get_wptr(struct radeon_device *rdev,
struct radeon_ring *ring); struct radeon_ring *ring);
void r100_gfx_set_wptr(struct radeon_device *rdev, void r100_gfx_set_wptr(struct radeon_device *rdev,
struct radeon_ring *ring); struct radeon_ring *ring);
void r100_ring_hdp_flush(struct radeon_device *rdev,
struct radeon_ring *ring);
/* /*
* r200,rv250,rs300,rv280 * r200,rv250,rs300,rv280
*/ */
......
...@@ -83,7 +83,7 @@ ...@@ -83,7 +83,7 @@
* CIK: 1D and linear tiling modes contain valid PIPE_CONFIG * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
* 2.39.0 - Add INFO query for number of active CUs * 2.39.0 - Add INFO query for number of active CUs
* 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
* CS to GPU * CS to GPU on >= r600
*/ */
#define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MAJOR 2
#define KMS_DRIVER_MINOR 40 #define KMS_DRIVER_MINOR 40
......
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