[PATCH] Make MTRR init conform with recommended procedure
From: Zwane Mwaikambo <zwane@linuxpower.ca> This is a patch to make the MTRR initialisation more conformant with what is stated in volume 3 of (10-36 Memory Cache Control). The most notable change is entering the no-fill cache mode before clearing the PGE bit in cr4. Intel also states that we should do the cache flush via the cr3 register shuffle. If there is a problem with the patch please don't hesitate to beat me vigorously with a clue-by-four. It has been tested on a 3x Pentium 133, 8x PIII Xeon 700, 1x Celeron 550 and 32x PIII 500 NUMAQ (hardware courtesy of OSDL)
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