Commit 8c373f8c authored by Emil Renner Berthing's avatar Emil Renner Berthing Committed by Stephen Boyd

clk: starfive: jh7100: Support more clock types

Unlike the system clocks there are audio clocks that combine both
multiplexer/divider and gate/multiplexer/divider, so add support for
that.
Signed-off-by: default avatarEmil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-7-kernel@esmil.dkSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 26ad971f
...@@ -534,6 +534,27 @@ static const struct clk_ops jh7100_clk_gmux_ops = { ...@@ -534,6 +534,27 @@ static const struct clk_ops jh7100_clk_gmux_ops = {
.debug_init = jh7100_clk_debug_init, .debug_init = jh7100_clk_debug_init,
}; };
static const struct clk_ops jh7100_clk_mdiv_ops = {
.recalc_rate = jh7100_clk_recalc_rate,
.determine_rate = jh7100_clk_determine_rate,
.get_parent = jh7100_clk_get_parent,
.set_parent = jh7100_clk_set_parent,
.set_rate = jh7100_clk_set_rate,
.debug_init = jh7100_clk_debug_init,
};
static const struct clk_ops jh7100_clk_gmd_ops = {
.enable = jh7100_clk_enable,
.disable = jh7100_clk_disable,
.is_enabled = jh7100_clk_is_enabled,
.recalc_rate = jh7100_clk_recalc_rate,
.determine_rate = jh7100_clk_determine_rate,
.get_parent = jh7100_clk_get_parent,
.set_parent = jh7100_clk_set_parent,
.set_rate = jh7100_clk_set_rate,
.debug_init = jh7100_clk_debug_init,
};
static const struct clk_ops jh7100_clk_inv_ops = { static const struct clk_ops jh7100_clk_inv_ops = {
.get_phase = jh7100_clk_get_phase, .get_phase = jh7100_clk_get_phase,
.set_phase = jh7100_clk_set_phase, .set_phase = jh7100_clk_set_phase,
...@@ -543,6 +564,11 @@ static const struct clk_ops jh7100_clk_inv_ops = { ...@@ -543,6 +564,11 @@ static const struct clk_ops jh7100_clk_inv_ops = {
const struct clk_ops *starfive_jh7100_clk_ops(u32 max) const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
{ {
if (max & JH7100_CLK_DIV_MASK) { if (max & JH7100_CLK_DIV_MASK) {
if (max & JH7100_CLK_MUX_MASK) {
if (max & JH7100_CLK_ENABLE)
return &jh7100_clk_gmd_ops;
return &jh7100_clk_mdiv_ops;
}
if (max & JH7100_CLK_ENABLE) if (max & JH7100_CLK_ENABLE)
return &jh7100_clk_gdiv_ops; return &jh7100_clk_gdiv_ops;
if (max == JH7100_CLK_FRAC_MAX) if (max == JH7100_CLK_FRAC_MAX)
......
...@@ -70,6 +70,21 @@ struct jh7100_clk_data { ...@@ -70,6 +70,21 @@ struct jh7100_clk_data {
.parents = { __VA_ARGS__ }, \ .parents = { __VA_ARGS__ }, \
} }
#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
.name = _name, \
.flags = 0, \
.max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
.parents = { __VA_ARGS__ }, \
}
#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
.name = _name, \
.flags = _flags, \
.max = JH7100_CLK_ENABLE | \
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
.parents = { __VA_ARGS__ }, \
}
#define JH7100__INV(_idx, _name, _parent) [_idx] = { \ #define JH7100__INV(_idx, _name, _parent) [_idx] = { \
.name = _name, \ .name = _name, \
.flags = CLK_SET_RATE_PARENT, \ .flags = CLK_SET_RATE_PARENT, \
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment