Commit 8c8661e4 authored by Ben Hutchings's avatar Ben Hutchings Committed by Jeff Garzik

sfc: Extend self-tests

Include PMA/PMD in loopback self-tests as intended.

Add NVRAM checksum validation and include it in self-tests.

Add register self-tests.

Run PHY self-tests where available.
Signed-off-by: default avatarBen Hutchings <bhutchings@solarflare.com>
Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
parent a515089c
...@@ -416,12 +416,23 @@ typedef union efx_oword { ...@@ -416,12 +416,23 @@ typedef union efx_oword {
* for read-modify-write operations. * for read-modify-write operations.
* *
*/ */
#define EFX_INVERT_OWORD(oword) do { \ #define EFX_INVERT_OWORD(oword) do { \
(oword).u64[0] = ~((oword).u64[0]); \ (oword).u64[0] = ~((oword).u64[0]); \
(oword).u64[1] = ~((oword).u64[1]); \ (oword).u64[1] = ~((oword).u64[1]); \
} while (0) } while (0)
#define EFX_AND_OWORD(oword, from, mask) \
do { \
(oword).u64[0] = (from).u64[0] & (mask).u64[0]; \
(oword).u64[1] = (from).u64[1] & (mask).u64[1]; \
} while (0)
#define EFX_OR_OWORD(oword, from, mask) \
do { \
(oword).u64[0] = (from).u64[0] | (mask).u64[0]; \
(oword).u64[1] = (from).u64[1] | (mask).u64[1]; \
} while (0)
#define EFX_INSERT64(min, max, low, high, value) \ #define EFX_INSERT64(min, max, low, high, value) \
cpu_to_le64(EFX_INSERT_NATIVE(min, max, low, high, value)) cpu_to_le64(EFX_INSERT_NATIVE(min, max, low, high, value))
...@@ -529,4 +540,10 @@ typedef union efx_oword { ...@@ -529,4 +540,10 @@ typedef union efx_oword {
#define EFX_DMA_TYPE_WIDTH(width) \ #define EFX_DMA_TYPE_WIDTH(width) \
(((width) < DMA_ADDR_T_WIDTH) ? (width) : DMA_ADDR_T_WIDTH) (((width) < DMA_ADDR_T_WIDTH) ? (width) : DMA_ADDR_T_WIDTH)
/* Static initialiser */
#define EFX_OWORD32(a, b, c, d) \
{ .u32 = { __constant_cpu_to_le32(a), __constant_cpu_to_le32(b), \
__constant_cpu_to_le32(c), __constant_cpu_to_le32(d) } }
#endif /* EFX_BITFIELD_H */ #endif /* EFX_BITFIELD_H */
...@@ -508,6 +508,11 @@ static void efx_link_status_changed(struct efx_nic *efx) ...@@ -508,6 +508,11 @@ static void efx_link_status_changed(struct efx_nic *efx)
if (!netif_running(efx->net_dev)) if (!netif_running(efx->net_dev))
return; return;
if (efx->port_inhibited) {
netif_carrier_off(efx->net_dev);
return;
}
if (efx->link_up != netif_carrier_ok(efx->net_dev)) { if (efx->link_up != netif_carrier_ok(efx->net_dev)) {
efx->n_link_state_changes++; efx->n_link_state_changes++;
...@@ -549,7 +554,7 @@ static void efx_link_status_changed(struct efx_nic *efx) ...@@ -549,7 +554,7 @@ static void efx_link_status_changed(struct efx_nic *efx)
/* This call reinitialises the MAC to pick up new PHY settings. The /* This call reinitialises the MAC to pick up new PHY settings. The
* caller must hold the mac_lock */ * caller must hold the mac_lock */
static void __efx_reconfigure_port(struct efx_nic *efx) void __efx_reconfigure_port(struct efx_nic *efx)
{ {
WARN_ON(!mutex_is_locked(&efx->mac_lock)); WARN_ON(!mutex_is_locked(&efx->mac_lock));
...@@ -634,6 +639,7 @@ static int efx_init_port(struct efx_nic *efx) ...@@ -634,6 +639,7 @@ static int efx_init_port(struct efx_nic *efx)
return rc; return rc;
efx->port_initialized = true; efx->port_initialized = true;
efx->stats_enabled = true;
/* Reconfigure port to program MAC registers */ /* Reconfigure port to program MAC registers */
falcon_reconfigure_xmac(efx); falcon_reconfigure_xmac(efx);
...@@ -1311,7 +1317,7 @@ static struct net_device_stats *efx_net_stats(struct net_device *net_dev) ...@@ -1311,7 +1317,7 @@ static struct net_device_stats *efx_net_stats(struct net_device *net_dev)
*/ */
if (!spin_trylock(&efx->stats_lock)) if (!spin_trylock(&efx->stats_lock))
return stats; return stats;
if (efx->state == STATE_RUNNING) { if (efx->stats_enabled) {
falcon_update_stats_xmac(efx); falcon_update_stats_xmac(efx);
falcon_update_nic_stats(efx); falcon_update_nic_stats(efx);
} }
...@@ -1529,7 +1535,7 @@ static void efx_unregister_netdev(struct efx_nic *efx) ...@@ -1529,7 +1535,7 @@ static void efx_unregister_netdev(struct efx_nic *efx)
/* Tears down the entire software state and most of the hardware state /* Tears down the entire software state and most of the hardware state
* before reset. */ * before reset. */
static void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{ {
int rc; int rc;
...@@ -1538,6 +1544,7 @@ static void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) ...@@ -1538,6 +1544,7 @@ static void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd)
/* The net_dev->get_stats handler is quite slow, and will fail /* The net_dev->get_stats handler is quite slow, and will fail
* if a fetch is pending over reset. Serialise against it. */ * if a fetch is pending over reset. Serialise against it. */
spin_lock(&efx->stats_lock); spin_lock(&efx->stats_lock);
efx->stats_enabled = false;
spin_unlock(&efx->stats_lock); spin_unlock(&efx->stats_lock);
efx_stop_all(efx); efx_stop_all(efx);
...@@ -1555,8 +1562,7 @@ static void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) ...@@ -1555,8 +1562,7 @@ static void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd)
* that we were unable to reinitialise the hardware, and the * that we were unable to reinitialise the hardware, and the
* driver should be disabled. If ok is false, then the rx and tx * driver should be disabled. If ok is false, then the rx and tx
* engines are not restarted, pending a RESET_DISABLE. */ * engines are not restarted, pending a RESET_DISABLE. */
static int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, bool ok)
bool ok)
{ {
int rc; int rc;
...@@ -1577,8 +1583,10 @@ static int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, ...@@ -1577,8 +1583,10 @@ static int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd,
mutex_unlock(&efx->mac_lock); mutex_unlock(&efx->mac_lock);
if (ok) if (ok) {
efx_start_all(efx); efx_start_all(efx);
efx->stats_enabled = true;
}
return rc; return rc;
} }
......
...@@ -37,6 +37,12 @@ extern void efx_flush_queues(struct efx_nic *efx); ...@@ -37,6 +37,12 @@ extern void efx_flush_queues(struct efx_nic *efx);
/* Ports */ /* Ports */
extern void efx_reconfigure_port(struct efx_nic *efx); extern void efx_reconfigure_port(struct efx_nic *efx);
extern void __efx_reconfigure_port(struct efx_nic *efx);
/* Reset handling */
extern void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd);
extern int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd,
bool ok);
/* Global */ /* Global */
extern void efx_schedule_reset(struct efx_nic *efx, enum reset_type type); extern void efx_schedule_reset(struct efx_nic *efx, enum reset_type type);
......
...@@ -333,7 +333,10 @@ static int efx_ethtool_fill_self_tests(struct efx_nic *efx, ...@@ -333,7 +333,10 @@ static int efx_ethtool_fill_self_tests(struct efx_nic *efx,
unsigned int n = 0; unsigned int n = 0;
enum efx_loopback_mode mode; enum efx_loopback_mode mode;
/* Interrupt */ efx_fill_test(n++, strings, data, &tests->mii,
"core", 0, "mii", NULL);
efx_fill_test(n++, strings, data, &tests->nvram,
"core", 0, "nvram", NULL);
efx_fill_test(n++, strings, data, &tests->interrupt, efx_fill_test(n++, strings, data, &tests->interrupt,
"core", 0, "interrupt", NULL); "core", 0, "interrupt", NULL);
...@@ -353,16 +356,17 @@ static int efx_ethtool_fill_self_tests(struct efx_nic *efx, ...@@ -353,16 +356,17 @@ static int efx_ethtool_fill_self_tests(struct efx_nic *efx,
"eventq.poll", NULL); "eventq.poll", NULL);
} }
/* PHY presence */ efx_fill_test(n++, strings, data, &tests->registers,
efx_fill_test(n++, strings, data, &tests->phy_ok, "core", 0, "registers", NULL);
EFX_PORT_NAME, "phy_ok", NULL); efx_fill_test(n++, strings, data, &tests->phy,
EFX_PORT_NAME, "phy", NULL);
/* Loopback tests */ /* Loopback tests */
efx_fill_test(n++, strings, data, &tests->loopback_speed, efx_fill_test(n++, strings, data, &tests->loopback_speed,
EFX_PORT_NAME, "loopback.speed", NULL); EFX_PORT_NAME, "loopback.speed", NULL);
efx_fill_test(n++, strings, data, &tests->loopback_full_duplex, efx_fill_test(n++, strings, data, &tests->loopback_full_duplex,
EFX_PORT_NAME, "loopback.full_duplex", NULL); EFX_PORT_NAME, "loopback.full_duplex", NULL);
for (mode = LOOPBACK_NONE; mode < LOOPBACK_TEST_MAX; mode++) { for (mode = LOOPBACK_NONE; mode <= LOOPBACK_TEST_MAX; mode++) {
if (!(efx->loopback_modes & (1 << mode))) if (!(efx->loopback_modes & (1 << mode)))
continue; continue;
n = efx_fill_loopback_test(efx, n = efx_fill_loopback_test(efx,
...@@ -500,15 +504,9 @@ static void efx_ethtool_self_test(struct net_device *net_dev, ...@@ -500,15 +504,9 @@ static void efx_ethtool_self_test(struct net_device *net_dev,
goto out; goto out;
/* Perform offline tests only if online tests passed */ /* Perform offline tests only if online tests passed */
if (offline) { if (offline)
/* Stop the kernel from sending packets during the test. */
efx_stop_queue(efx);
efx_flush_queues(efx);
rc = efx_offline_test(efx, &efx_tests, rc = efx_offline_test(efx, &efx_tests,
efx->loopback_modes); efx->loopback_modes);
efx_wake_queue(efx);
}
out: out:
if (!already_up) if (!already_up)
......
...@@ -2223,6 +2223,170 @@ void falcon_set_multicast_hash(struct efx_nic *efx) ...@@ -2223,6 +2223,170 @@ void falcon_set_multicast_hash(struct efx_nic *efx)
falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER); falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
} }
/**************************************************************************
*
* Falcon test code
*
**************************************************************************/
int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
{
struct falcon_nvconfig *nvconfig;
struct efx_spi_device *spi;
void *region;
int rc, magic_num, struct_ver;
__le16 *word, *limit;
u32 csum;
region = kmalloc(NVCONFIG_END, GFP_KERNEL);
if (!region)
return -ENOMEM;
nvconfig = region + NVCONFIG_OFFSET;
spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
rc = falcon_spi_read(spi, 0, NVCONFIG_END, NULL, region);
if (rc) {
EFX_ERR(efx, "Failed to read %s\n",
efx->spi_flash ? "flash" : "EEPROM");
rc = -EIO;
goto out;
}
magic_num = le16_to_cpu(nvconfig->board_magic_num);
struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
rc = -EINVAL;
if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
goto out;
}
if (struct_ver < 2) {
EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
goto out;
} else if (struct_ver < 4) {
word = &nvconfig->board_magic_num;
limit = (__le16 *) (nvconfig + 1);
} else {
word = region;
limit = region + NVCONFIG_END;
}
for (csum = 0; word < limit; ++word)
csum += le16_to_cpu(*word);
if (~csum & 0xffff) {
EFX_ERR(efx, "NVRAM has incorrect checksum\n");
goto out;
}
rc = 0;
if (nvconfig_out)
memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
out:
kfree(region);
return rc;
}
/* Registers tested in the falcon register test */
static struct {
unsigned address;
efx_oword_t mask;
} efx_test_registers[] = {
{ ADR_REGION_REG_KER,
EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
{ RX_CFG_REG_KER,
EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
{ TX_CFG_REG_KER,
EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
{ TX_CFG2_REG_KER,
EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
{ MAC0_CTRL_REG_KER,
EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
{ SRM_TX_DC_CFG_REG_KER,
EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
{ RX_DC_CFG_REG_KER,
EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
{ RX_DC_PF_WM_REG_KER,
EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
{ DP_CTRL_REG,
EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
{ XM_GLB_CFG_REG,
EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
{ XM_TX_CFG_REG,
EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
{ XM_RX_CFG_REG,
EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
{ XM_RX_PARAM_REG,
EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
{ XM_FC_REG,
EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
{ XM_ADR_LO_REG,
EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
{ XX_SD_CTL_REG,
EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
};
static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
const efx_oword_t *mask)
{
return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
}
int falcon_test_registers(struct efx_nic *efx)
{
unsigned address = 0, i, j;
efx_oword_t mask, imask, original, reg, buf;
/* Falcon should be in loopback to isolate the XMAC from the PHY */
WARN_ON(!LOOPBACK_INTERNAL(efx));
for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
address = efx_test_registers[i].address;
mask = imask = efx_test_registers[i].mask;
EFX_INVERT_OWORD(imask);
falcon_read(efx, &original, address);
/* bit sweep on and off */
for (j = 0; j < 128; j++) {
if (!EFX_EXTRACT_OWORD32(mask, j, j))
continue;
/* Test this testable bit can be set in isolation */
EFX_AND_OWORD(reg, original, mask);
EFX_SET_OWORD32(reg, j, j, 1);
falcon_write(efx, &reg, address);
falcon_read(efx, &buf, address);
if (efx_masked_compare_oword(&reg, &buf, &mask))
goto fail;
/* Test this testable bit can be cleared in isolation */
EFX_OR_OWORD(reg, original, mask);
EFX_SET_OWORD32(reg, j, j, 0);
falcon_write(efx, &reg, address);
falcon_read(efx, &buf, address);
if (efx_masked_compare_oword(&reg, &buf, &mask))
goto fail;
}
falcon_write(efx, &original, address);
}
return 0;
fail:
EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
" at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
return -EIO;
}
/************************************************************************** /**************************************************************************
* *
* Device reset * Device reset
...@@ -2404,37 +2568,22 @@ static void falcon_remove_spi_devices(struct efx_nic *efx) ...@@ -2404,37 +2568,22 @@ static void falcon_remove_spi_devices(struct efx_nic *efx)
static int falcon_probe_nvconfig(struct efx_nic *efx) static int falcon_probe_nvconfig(struct efx_nic *efx)
{ {
struct falcon_nvconfig *nvconfig; struct falcon_nvconfig *nvconfig;
struct efx_spi_device *spi; int board_rev;
int magic_num, struct_ver, board_rev;
int rc; int rc;
nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
if (!nvconfig) if (!nvconfig)
return -ENOMEM; return -ENOMEM;
/* Read the whole configuration structure into memory. */ rc = falcon_read_nvram(efx, nvconfig);
spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom; if (rc == -EINVAL) {
rc = falcon_spi_read(spi, NVCONFIG_BASE, sizeof(*nvconfig), EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
NULL, (char *)nvconfig);
if (rc) {
EFX_ERR(efx, "Failed to read %s\n", efx->spi_flash ? "flash" :
"EEPROM");
goto fail1;
}
/* Read the MAC addresses */
memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
/* Read the board configuration. */
magic_num = le16_to_cpu(nvconfig->board_magic_num);
struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
"therefore using defaults\n", magic_num, struct_ver);
efx->phy_type = PHY_TYPE_NONE; efx->phy_type = PHY_TYPE_NONE;
efx->mii.phy_id = PHY_ADDR_INVALID; efx->mii.phy_id = PHY_ADDR_INVALID;
board_rev = 0; board_rev = 0;
rc = 0;
} else if (rc) {
goto fail1;
} else { } else {
struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3; struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
...@@ -2443,7 +2592,7 @@ static int falcon_probe_nvconfig(struct efx_nic *efx) ...@@ -2443,7 +2592,7 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
efx->mii.phy_id = v2->port0_phy_addr; efx->mii.phy_id = v2->port0_phy_addr;
board_rev = le16_to_cpu(v2->board_revision); board_rev = le16_to_cpu(v2->board_revision);
if (struct_ver >= 3) { if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
__le32 fl = v3->spi_device_type[EE_SPI_FLASH]; __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
__le32 ee = v3->spi_device_type[EE_SPI_EEPROM]; __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
rc = falcon_spi_device_init(efx, &efx->spi_flash, rc = falcon_spi_device_init(efx, &efx->spi_flash,
...@@ -2459,6 +2608,9 @@ static int falcon_probe_nvconfig(struct efx_nic *efx) ...@@ -2459,6 +2608,9 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
} }
} }
/* Read the MAC addresses */
memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id); EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
efx_set_board_info(efx, board_rev); efx_set_board_info(efx, board_rev);
......
...@@ -93,6 +93,12 @@ extern void falcon_update_nic_stats(struct efx_nic *efx); ...@@ -93,6 +93,12 @@ extern void falcon_update_nic_stats(struct efx_nic *efx);
extern void falcon_set_multicast_hash(struct efx_nic *efx); extern void falcon_set_multicast_hash(struct efx_nic *efx);
extern int falcon_reset_xaui(struct efx_nic *efx); extern int falcon_reset_xaui(struct efx_nic *efx);
/* Tests */
struct falcon_nvconfig;
extern int falcon_read_nvram(struct efx_nic *efx,
struct falcon_nvconfig *nvconfig);
extern int falcon_test_registers(struct efx_nic *efx);
/************************************************************************** /**************************************************************************
* *
* Falcon MAC stats * Falcon MAC stats
......
...@@ -1150,7 +1150,9 @@ struct falcon_nvconfig_board_v3 { ...@@ -1150,7 +1150,9 @@ struct falcon_nvconfig_board_v3 {
#define SPI_DEV_TYPE_FIELD(type, field) \ #define SPI_DEV_TYPE_FIELD(type, field) \
(((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field))) (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
#define NVCONFIG_BASE 0x300 #define NVCONFIG_OFFSET 0x300
#define NVCONFIG_END 0x400
#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C #define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
struct falcon_nvconfig { struct falcon_nvconfig {
efx_oword_t ee_vpd_cfg_reg; /* 0x300 */ efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
......
...@@ -373,17 +373,9 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) ...@@ -373,17 +373,9 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) || reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
(xaui_loopback != old_xaui_loopback) || (xaui_loopback != old_xaui_loopback) ||
(xgmii_loopback != old_xgmii_loopback)); (xgmii_loopback != old_xgmii_loopback));
if (reset_xgxs) {
falcon_read(efx, &reg, XX_PWR_RST_REG); if (reset_xgxs)
EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1); falcon_reset_xaui(efx);
EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
falcon_write(efx, &reg, XX_PWR_RST_REG);
udelay(1);
EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 0);
EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 0);
falcon_write(efx, &reg, XX_PWR_RST_REG);
udelay(1);
}
} }
falcon_read(efx, &reg, XX_CORE_STAT_REG); falcon_read(efx, &reg, XX_CORE_STAT_REG);
......
...@@ -515,6 +515,7 @@ struct efx_phy_operations { ...@@ -515,6 +515,7 @@ struct efx_phy_operations {
void (*clear_interrupt) (struct efx_nic *efx); void (*clear_interrupt) (struct efx_nic *efx);
int (*check_hw) (struct efx_nic *efx); int (*check_hw) (struct efx_nic *efx);
void (*reset_xaui) (struct efx_nic *efx); void (*reset_xaui) (struct efx_nic *efx);
int (*test) (struct efx_nic *efx);
int mmds; int mmds;
unsigned loopbacks; unsigned loopbacks;
}; };
...@@ -533,7 +534,7 @@ enum efx_phy_mode { ...@@ -533,7 +534,7 @@ enum efx_phy_mode {
static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
{ {
return (mode & ~PHY_MODE_TX_DISABLED) != 0; return !!(mode & ~PHY_MODE_TX_DISABLED);
} }
/* /*
...@@ -655,13 +656,14 @@ union efx_multicast_hash { ...@@ -655,13 +656,14 @@ union efx_multicast_hash {
* This field will be %NULL if no EEPROM device is present. * This field will be %NULL if no EEPROM device is present.
* @n_rx_nodesc_drop_cnt: RX no descriptor drop count * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
* @nic_data: Hardware dependant state * @nic_data: Hardware dependant state
* @mac_lock: MAC access lock. Protects @port_enabled, efx_monitor() and * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
* efx_reconfigure_port() * @port_inhibited, efx_monitor() and efx_reconfigure_port()
* @port_enabled: Port enabled indicator. * @port_enabled: Port enabled indicator.
* Serialises efx_stop_all(), efx_start_all() and efx_monitor() and * Serialises efx_stop_all(), efx_start_all() and efx_monitor() and
* efx_reconfigure_work with kernel interfaces. Safe to read under any * efx_reconfigure_work with kernel interfaces. Safe to read under any
* one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
* be held to modify it. * be held to modify it.
* @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
* @port_initialized: Port initialized? * @port_initialized: Port initialized?
* @net_dev: Operating system network device. Consider holding the rtnl lock * @net_dev: Operating system network device. Consider holding the rtnl lock
* @rx_checksum_enabled: RX checksumming enabled * @rx_checksum_enabled: RX checksumming enabled
...@@ -671,14 +673,16 @@ union efx_multicast_hash { ...@@ -671,14 +673,16 @@ union efx_multicast_hash {
* can provide. Generic code converts these into a standard * can provide. Generic code converts these into a standard
* &struct net_device_stats. * &struct net_device_stats.
* @stats_buffer: DMA buffer for statistics * @stats_buffer: DMA buffer for statistics
* @stats_lock: Statistics update lock * @stats_lock: Statistics update lock. Serialises statistics fetches
* @stats_enabled: Temporarily disable statistics fetches.
* Serialised by @stats_lock
* @mac_address: Permanent MAC address * @mac_address: Permanent MAC address
* @phy_type: PHY type * @phy_type: PHY type
* @phy_lock: PHY access lock * @phy_lock: PHY access lock
* @phy_op: PHY interface * @phy_op: PHY interface
* @phy_data: PHY private data (including PHY-specific stats) * @phy_data: PHY private data (including PHY-specific stats)
* @mii: PHY interface * @mii: PHY interface
* @phy_mode: PHY operating mode * @phy_mode: PHY operating mode. Serialised by @mac_lock.
* @link_up: Link status * @link_up: Link status
* @link_options: Link options (MII/GMII format) * @link_options: Link options (MII/GMII format)
* @n_link_state_changes: Number of times the link has changed state * @n_link_state_changes: Number of times the link has changed state
...@@ -733,6 +737,7 @@ struct efx_nic { ...@@ -733,6 +737,7 @@ struct efx_nic {
struct mutex mac_lock; struct mutex mac_lock;
bool port_enabled; bool port_enabled;
bool port_inhibited;
bool port_initialized; bool port_initialized;
struct net_device *net_dev; struct net_device *net_dev;
...@@ -744,6 +749,7 @@ struct efx_nic { ...@@ -744,6 +749,7 @@ struct efx_nic {
struct efx_mac_stats mac_stats; struct efx_mac_stats mac_stats;
struct efx_buffer stats_buffer; struct efx_buffer stats_buffer;
spinlock_t stats_lock; spinlock_t stats_lock;
bool stats_enabled;
unsigned char mac_address[ETH_ALEN]; unsigned char mac_address[ETH_ALEN];
......
This diff is collapsed.
...@@ -29,14 +29,19 @@ struct efx_loopback_self_tests { ...@@ -29,14 +29,19 @@ struct efx_loopback_self_tests {
* indicates failure. * indicates failure.
*/ */
struct efx_self_tests { struct efx_self_tests {
/* online tests */
int mii;
int nvram;
int interrupt; int interrupt;
int eventq_dma[EFX_MAX_CHANNELS]; int eventq_dma[EFX_MAX_CHANNELS];
int eventq_int[EFX_MAX_CHANNELS]; int eventq_int[EFX_MAX_CHANNELS];
int eventq_poll[EFX_MAX_CHANNELS]; int eventq_poll[EFX_MAX_CHANNELS];
int phy_ok; /* offline tests */
int registers;
int phy;
int loopback_speed; int loopback_speed;
int loopback_full_duplex; int loopback_full_duplex;
struct efx_loopback_self_tests loopback[LOOPBACK_TEST_MAX]; struct efx_loopback_self_tests loopback[LOOPBACK_TEST_MAX + 1];
}; };
extern void efx_loopback_rx_packet(struct efx_nic *efx, extern void efx_loopback_rx_packet(struct efx_nic *efx,
......
...@@ -65,25 +65,10 @@ ...@@ -65,25 +65,10 @@
#define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
/* Self test (BIST) control register */
#define PMA_PMD_BIST_CTRL_REG (0xc014)
#define PMA_PMD_BIST_BER_LBN (2) /* Run BER test */
#define PMA_PMD_BIST_CONT_LBN (1) /* Run continuous BIST until cleared */
#define PMA_PMD_BIST_SINGLE_LBN (0) /* Run 1 BIST iteration (self clears) */
/* Self test status register */
#define PMA_PMD_BIST_STAT_REG (0xc015)
#define PMA_PMD_BIST_ENX_LBN (3)
#define PMA_PMD_BIST_PMA_LBN (2)
#define PMA_PMD_BIST_RXD_LBN (1)
#define PMA_PMD_BIST_AFE_LBN (0)
/* Special Software reset register */ /* Special Software reset register */
#define PMA_PMD_EXT_CTRL_REG 49152 #define PMA_PMD_EXT_CTRL_REG 49152
#define PMA_PMD_EXT_SSR_LBN 15 #define PMA_PMD_EXT_SSR_LBN 15
#define BIST_MAX_DELAY (1000)
#define BIST_POLL_DELAY (10)
/* Misc register defines */ /* Misc register defines */
#define PCS_CLOCK_CTRL_REG 0xd801 #define PCS_CLOCK_CTRL_REG 0xd801
#define PLL312_RST_N_LBN 2 #define PLL312_RST_N_LBN 2
...@@ -491,6 +476,12 @@ static void tenxpress_reset_xaui(struct efx_nic *efx) ...@@ -491,6 +476,12 @@ static void tenxpress_reset_xaui(struct efx_nic *efx)
udelay(10); udelay(10);
} }
static int tenxpress_phy_test(struct efx_nic *efx)
{
/* BIST is automatically run after a special software reset */
return tenxpress_special_reset(efx);
}
struct efx_phy_operations falcon_tenxpress_phy_ops = { struct efx_phy_operations falcon_tenxpress_phy_ops = {
.init = tenxpress_phy_init, .init = tenxpress_phy_init,
.reconfigure = tenxpress_phy_reconfigure, .reconfigure = tenxpress_phy_reconfigure,
...@@ -498,6 +489,7 @@ struct efx_phy_operations falcon_tenxpress_phy_ops = { ...@@ -498,6 +489,7 @@ struct efx_phy_operations falcon_tenxpress_phy_ops = {
.fini = tenxpress_phy_fini, .fini = tenxpress_phy_fini,
.clear_interrupt = tenxpress_phy_clear_interrupt, .clear_interrupt = tenxpress_phy_clear_interrupt,
.reset_xaui = tenxpress_reset_xaui, .reset_xaui = tenxpress_reset_xaui,
.test = tenxpress_phy_test,
.mmds = TENXPRESS_REQUIRED_DEVS, .mmds = TENXPRESS_REQUIRED_DEVS,
.loopbacks = TENXPRESS_LOOPBACKS, .loopbacks = TENXPRESS_LOOPBACKS,
}; };
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