Commit 8d01071d authored by Chengming Gui's avatar Chengming Gui Committed by Alex Deucher

drm/amd/powerplay: enable UMDPSTATE support on raven2 (v2)

enable UMDPSTATE support to force performance level for raven2.

v2: squash in warning fix (Alex)
Signed-off-by: default avatarChengming Gui <Jack.Gui@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 45516e91
...@@ -573,7 +573,6 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, ...@@ -573,7 +573,6 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level) enum amd_dpm_forced_level level)
{ {
struct smu10_hwmgr *data = hwmgr->backend; struct smu10_hwmgr *data = hwmgr->backend;
struct amdgpu_device *adev = hwmgr->adev;
uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
...@@ -582,11 +581,6 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, ...@@ -582,11 +581,6 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
return 0; return 0;
} }
/* Disable UMDPSTATE support on rv2 temporarily */
if ((adev->asic_type == CHIP_RAVEN) &&
(adev->rev_id >= 8))
return 0;
if (min_sclk < data->gfx_min_freq_limit) if (min_sclk < data->gfx_min_freq_limit)
min_sclk = data->gfx_min_freq_limit; min_sclk = data->gfx_min_freq_limit;
......
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