hwmon: (ucd90320) Add minimum delay between bus accesses
When probing the ucd90320 access to some of the registers randomly fails. Sometimes it NACKs a transfer, sometimes it returns just random data and the PEC check fails. Experimentation shows that this seems to be triggered by a register access directly back to back with a previous register write. Experimentation also shows that inserting a small delay after register writes makes the issue go away. Use a similar solution to what the max15301 driver does to solve the same problem. Create a custom set of bus read and write functions that make sure that the delay is added. Fixes: a470f11c ("hwmon: (pmbus/ucd9000) Add support for UCD90320 Power Sequencer") Signed-off-by:Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230312160312.2227405-1-lars@metafoo.deSigned-off-by:
Guenter Roeck <linux@roeck-us.net>
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