Commit 8e6302eb authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher

drm/amd/display: add dp dto programming function to dccg

[WHY&HOW]
Add support for programming dp dto via dccg.
Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 77aac4c2
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
#include "dce_clock_source.h" #include "dce_clock_source.h"
#include "clk_mgr.h" #include "clk_mgr.h"
#include "dccg.h"
#include "reg_helper.h" #include "reg_helper.h"
......
...@@ -56,6 +56,13 @@ enum dentist_dispclk_change_mode { ...@@ -56,6 +56,13 @@ enum dentist_dispclk_change_mode {
DISPCLK_CHANGE_MODE_RAMPING, DISPCLK_CHANGE_MODE_RAMPING,
}; };
struct dp_dto_params {
int otg_inst;
enum signal_type signal;
long long pixclk_hz;
long long refclk_hz;
};
enum pixel_rate_div { enum pixel_rate_div {
PIXEL_RATE_DIV_BY_1 = 0, PIXEL_RATE_DIV_BY_1 = 0,
PIXEL_RATE_DIV_BY_2 = 1, PIXEL_RATE_DIV_BY_2 = 1,
...@@ -182,6 +189,9 @@ struct dccg_funcs { ...@@ -182,6 +189,9 @@ struct dccg_funcs {
struct dccg *dccg, struct dccg *dccg,
uint32_t stream_enc_inst, uint32_t stream_enc_inst,
uint32_t link_enc_inst); uint32_t link_enc_inst);
void (*set_dp_dto)(
struct dccg *dccg,
const struct dp_dto_params *params);
}; };
#endif //__DAL_DCCG_H__ #endif //__DAL_DCCG_H__
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