Commit 8f7e001e authored by Palmer Dabbelt's avatar Palmer Dabbelt

RISC-V: Clean up the Zicbom block size probing

This fixes two issues: I truncated the warning's hart ID when porting to
the 64-bit hart ID code, and the original code's warning handling could
fire on an uninitialized hart ID.

The biggest change here is that riscv_cbom_block_size is no longer
initialized, as IMO the default isn't sane: there's nothing in the ISA
that mandates any specific cache block size, so falling back to one will
just silently produce the wrong answer on some systems.  This also
changes the probing order so the cache block size is known before
enabling Zicbom support.

CC: stable@vger.kernel.org
CC: Andrew Jones <ajones@ventanamicro.com>
CC: Heiko Stuebner <heiko@sntech.de>
CC: Atish Patra <atishp@rivosinc.com>
Fixes: 3aefb2ee ("riscv: implement Zicbom-based CMO instructions + the t-head variant")
Fixes: 1631ba12 ("riscv: Add support for non-coherent devices using zicbom extension")
Reported-by: default avatarkernel test robot <lkp@intel.com>
Reported-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
[Conor: fixed the redefinition errors]
Tested-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220912224800.998121-1-mail@conchuod.ieSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 20e0fbab
...@@ -37,6 +37,7 @@ static bool errata_probe_cmo(unsigned int stage, ...@@ -37,6 +37,7 @@ static bool errata_probe_cmo(unsigned int stage,
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
return false; return false;
riscv_cbom_block_size = L1_CACHE_BYTES;
riscv_noncoherent_supported(); riscv_noncoherent_supported();
return true; return true;
#else #else
......
...@@ -43,6 +43,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local); ...@@ -43,6 +43,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
#endif /* CONFIG_SMP */ #endif /* CONFIG_SMP */
#ifdef CONFIG_RISCV_ISA_ZICBOM #ifdef CONFIG_RISCV_ISA_ZICBOM
extern unsigned int riscv_cbom_block_size;
void riscv_init_cbom_blocksize(void); void riscv_init_cbom_blocksize(void);
#else #else
static inline void riscv_init_cbom_blocksize(void) { } static inline void riscv_init_cbom_blocksize(void) { }
......
...@@ -296,8 +296,8 @@ void __init setup_arch(char **cmdline_p) ...@@ -296,8 +296,8 @@ void __init setup_arch(char **cmdline_p)
setup_smp(); setup_smp();
#endif #endif
riscv_fill_hwcap();
riscv_init_cbom_blocksize(); riscv_init_cbom_blocksize();
riscv_fill_hwcap();
apply_boot_alternatives(); apply_boot_alternatives();
} }
......
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
#include <linux/of_device.h> #include <linux/of_device.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES; unsigned int riscv_cbom_block_size;
static bool noncoherent_supported; static bool noncoherent_supported;
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
...@@ -79,38 +79,41 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, ...@@ -79,38 +79,41 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
void riscv_init_cbom_blocksize(void) void riscv_init_cbom_blocksize(void)
{ {
struct device_node *node; struct device_node *node;
unsigned long cbom_hartid;
u32 val, probed_block_size;
int ret; int ret;
u32 val;
probed_block_size = 0;
for_each_of_cpu_node(node) { for_each_of_cpu_node(node) {
unsigned long hartid; unsigned long hartid;
int cbom_hartid;
ret = riscv_of_processor_hartid(node, &hartid); ret = riscv_of_processor_hartid(node, &hartid);
if (ret) if (ret)
continue; continue;
if (hartid < 0)
continue;
/* set block-size for cbom extension if available */ /* set block-size for cbom extension if available */
ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
if (ret) if (ret)
continue; continue;
if (!riscv_cbom_block_size) { if (!probed_block_size) {
riscv_cbom_block_size = val; probed_block_size = val;
cbom_hartid = hartid; cbom_hartid = hartid;
} else { } else {
if (riscv_cbom_block_size != val) if (probed_block_size != val)
pr_warn("cbom-block-size mismatched between harts %d and %lu\n", pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
cbom_hartid, hartid); cbom_hartid, hartid);
} }
} }
if (probed_block_size)
riscv_cbom_block_size = probed_block_size;
} }
#endif #endif
void riscv_noncoherent_supported(void) void riscv_noncoherent_supported(void)
{ {
WARN(!riscv_cbom_block_size,
"Non-coherent DMA support enabled without a block size\n");
noncoherent_supported = true; noncoherent_supported = true;
} }
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