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Commit 8fe33fd5 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events: Update Intel nehalemex 

Update to v3, there are no TMA metrics for nehalemex.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py

to download and generate the latest events and metrics. Manually copy
the nehalemex files into perf and update mapfile.csv.

Tested on a non-nehalemex with 'perf test':
 10: PMU events                                                      :
 10.1: PMU event table sanity                                        : Ok
 10.2: PMU event map aliases                                         : Ok
 10.3: Parsing of PMU event table metrics                            : Ok
 10.4: Parsing of PMU event table metrics with fake PMUs             : Ok

Note: most of this change is just sorting the keys in the json dictionaries.
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-21-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
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Showing with 2471 additions and 2471 deletions
tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 8fe33fd5
......@@ -18,7 +18,7 @@ GenuineIntel-6-2D,v21,jaketown,core
GenuineIntel-6-(57|85),v9,knightslanding,core
GenuineIntel-6-AA,v1.00,meteorlake,core
GenuineIntel-6-1[AEF],v3,nehalemep,core
GenuineIntel-6-2E,v2,nehalemex,core
GenuineIntel-6-2E,v3,nehalemex,core
GenuineIntel-6-[4589]E,v24,skylake,core
GenuineIntel-6-A[56],v24,skylake,core
GenuineIntel-6-37,v13,silvermont,core
......
tools/perf/pmu-events/arch/x86/nehalemex/cache.json
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tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
View file @ 8fe33fd5
[
{
"EventCode": "0xD0",
"BriefDescription": "Instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions decoded"
"UMask": "0x1"
},
{
"EventCode": "0xA6",
"BriefDescription": "Macro-fused instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Macro-fused instructions decoded"
"UMask": "0x1"
},
{
"EventCode": "0x19",
"BriefDescription": "Two Uop instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Two Uop instructions decoded"
"UMask": "0x1"
}
]
\ No newline at end of file
]
tools/perf/pmu-events/arch/x86/nehalemex/other.json
View file @ 8fe33fd5
[
{
"EventCode": "0xE8",
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
"BriefDescription": "Early Branch Prediciton Unit clears"
},
{
"EventCode": "0xE8",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
"BriefDescription": "Late Branch Prediction Unit clears"
},
{
"EventCode": "0xE5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
"BriefDescription": "Branch prediction unit missed call or return"
},
{
"EventCode": "0xD5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
"BriefDescription": "ES segment renames"
"UMask": "0x1"
},
{
"EventCode": "0x6C",
"BriefDescription": "I/O transactions",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
"BriefDescription": "I/O transactions"
"UMask": "0x1"
},
{
"EventCode": "0x80",
"BriefDescription": "L1I instruction fetch stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch stall cycles"
"UMask": "0x4"
},
{
"EventCode": "0x80",
"BriefDescription": "L1I instruction fetch hits",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch hits"
"UMask": "0x1"
},
{
"EventCode": "0x80",
"BriefDescription": "L1I instruction fetch misses",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch misses"
"UMask": "0x2"
},
{
"EventCode": "0x80",
"BriefDescription": "L1I Instruction fetches",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I Instruction fetches"
"UMask": "0x3"
},
{
"EventCode": "0x82",
"BriefDescription": "Large ITLB hit",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "Large ITLB hit"
"UMask": "0x1"
},
{
"EventCode": "0x13",
"BriefDescription": "All loads dispatched",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All loads dispatched"
"UMask": "0x7"
},
{
"EventCode": "0x13",
"BriefDescription": "Loads dispatched from the MOB",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched from the MOB"
"UMask": "0x4"
},
{
"EventCode": "0x13",
"BriefDescription": "Loads dispatched that bypass the MOB",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched that bypass the MOB"
"UMask": "0x1"
},
{
"EventCode": "0x13",
"BriefDescription": "Loads dispatched from stage 305",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched from stage 305"
"UMask": "0x2"
},
{
"EventCode": "0x7",
"BriefDescription": "False dependencies due to partial address aliasing",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
"BriefDescription": "False dependencies due to partial address aliasing"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0xf",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All RAT stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
"BriefDescription": "Flag stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
"BriefDescription": "Partial register stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
"BriefDescription": "ROB read port stalls cycles"
"UMask": "0x1"
},
{
"EventCode": "0xD2",
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
"BriefDescription": "Scoreboard stall cycles"
},
{
"EventCode": "0x4",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "All Store buffer stall cycles"
"UMask": "0x7"
},
{
"EventCode": "0xD4",
"BriefDescription": "Segment rename stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
"BriefDescription": "Segment rename stall cycles"
"UMask": "0x1"
},
{
"EventCode": "0xB8",
"BriefDescription": "Thread responded HIT to snoop",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HIT to snoop"
"UMask": "0x1"
},
{
"EventCode": "0xB8",
"BriefDescription": "Thread responded HITE to snoop",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HITE to snoop"
"UMask": "0x2"
},
{
"EventCode": "0xB8",
"BriefDescription": "Thread responded HITM to snoop",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HITM to snoop"
"UMask": "0x4"
},
{
"EventCode": "0xF6",
"BriefDescription": "Super Queue full stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Super Queue full stall cycles"
"UMask": "0x1"
}
]
\ No newline at end of file
]
tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
View file @ 8fe33fd5
[
{
"EventCode": "0x8",
"BriefDescription": "DTLB load misses",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load misses"
"UMask": "0x1"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss caused by low part of address",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss caused by low part of address"
"UMask": "0x20"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB second level hit",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB second level hit"
"UMask": "0x10"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss page walks complete",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walks complete"
"UMask": "0x2"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB misses",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses"
"UMask": "0x1"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB first level misses but second level hit",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB first level misses but second level hit"
"UMask": "0x10"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB miss page walks",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss page walks"
"UMask": "0x2"
},
{
"EventCode": "0xAE",
"BriefDescription": "ITLB flushes",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB flushes"
"UMask": "0x1"
},
{
"PEBS": "1",
"EventCode": "0xC8",
"BriefDescription": "ITLB miss",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "ITLB_MISS_RETIRED",
"SampleAfterValue": "200000",
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss"
"UMask": "0x1"
},
{
"EventCode": "0x85",
"BriefDescription": "ITLB miss page walks",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss page walks"
"UMask": "0x2"
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
"EventCode": "0xCB",
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
"UMask": "0x80"
},
{
"PEBS": "1",
"EventCode": "0xC",
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
"SampleAfterValue": "200000",
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
"UMask": "0x1"
}
]
\ No newline at end of file
]
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