Commit 9269bf18 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu: add asic callback for querying video codec info (v3)

This will be used by a new INFO ioctl query to fetch the decode
and encode capabilities from the kernel driver rather than
hardcoding them in mesa.  This gives us more fine grained control
of capabilities using information that is only availabl in the
kernel (e.g., platform limitations or bandwidth restrictions).

v2: reorder the codecs to better align with mesa
v3: add max_pixels_per_frame to handle the portrait case
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com> (v2)
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6f59f229
...@@ -584,6 +584,28 @@ enum amd_reset_method { ...@@ -584,6 +584,28 @@ enum amd_reset_method {
AMD_RESET_METHOD_PCI, AMD_RESET_METHOD_PCI,
}; };
#define AMDGPU_VIDEO_CODEC_TYPE_MPEG2 0
#define AMDGPU_VIDEO_CODEC_TYPE_MPEG4 1
#define AMDGPU_VIDEO_CODEC_TYPE_VC1 2
#define AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC 3
#define AMDGPU_VIDEO_CODEC_TYPE_HEVC 4
#define AMDGPU_VIDEO_CODEC_TYPE_JPEG 5
#define AMDGPU_VIDEO_CODEC_TYPE_VP9 6
#define AMDGPU_VIDEO_CODEC_TYPE_AV1 7
struct amdgpu_video_codec_info {
u32 codec_type;
u32 max_width;
u32 max_height;
u32 max_pixels_per_frame;
u32 max_level;
};
struct amdgpu_video_codecs {
const u32 codec_count;
const struct amdgpu_video_codec_info *codec_array;
};
/* /*
* ASIC specific functions. * ASIC specific functions.
*/ */
...@@ -628,6 +650,9 @@ struct amdgpu_asic_funcs { ...@@ -628,6 +650,9 @@ struct amdgpu_asic_funcs {
void (*pre_asic_init)(struct amdgpu_device *adev); void (*pre_asic_init)(struct amdgpu_device *adev);
/* enter/exit umd stable pstate */ /* enter/exit umd stable pstate */
int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
/* query video codecs */
int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
const struct amdgpu_video_codecs **codecs);
}; };
/* /*
...@@ -1222,6 +1247,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); ...@@ -1222,6 +1247,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment