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Commit 92fba5d3 authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie
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drm/nouveau/disp: collapse nv50_disp into nvkm_disp 

Dump of one struct's members into another, with a couple of list
renames because of collisions.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 0407b33f
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Showing with 472 additions and 562 deletions
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
View file @ 92fba5d3
......@@ -9,14 +9,42 @@ struct nvkm_disp {
const struct nvkm_disp_func *func;
struct nvkm_engine engine;
struct list_head head;
struct list_head ior;
struct list_head outp;
struct list_head conn;
struct list_head heads;
struct list_head iors;
struct list_head outps;
struct list_head conns;
struct nvkm_event hpd;
struct nvkm_event vblank;
struct workqueue_struct *wq;
struct work_struct supervisor;
u32 super;
struct nvkm_event uevent;
struct {
unsigned long mask;
int nr;
} wndw, head, dac;
struct {
unsigned long mask;
int nr;
u32 lvdsconf;
} sor;
struct {
unsigned long mask;
int nr;
u8 type[3];
} pior;
struct nvkm_gpuobj *inst;
struct nvkm_ramht *ramht;
struct nv50_disp_chan *chan[81];
struct {
spinlock_t lock;
struct nvkm_oproxy *object;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
View file @ 92fba5d3
......@@ -108,7 +108,7 @@ nvkm_disp_hpd_ctor(struct nvkm_object *object, void *data, u32 size,
if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, false))) {
notify->size = sizeof(struct nvif_notify_conn_rep_v0);
list_for_each_entry(outp, &disp->outp, head) {
list_for_each_entry(outp, &disp->outps, head) {
if (ret = -ENXIO, outp->conn->index == req->v0.conn) {
if (ret = -ENODEV, outp->conn->hpd.event) {
notify->types = req->v0.mask;
......@@ -222,11 +222,11 @@ nvkm_disp_fini(struct nvkm_engine *engine, bool suspend)
if (disp->func->fini)
disp->func->fini(disp);
list_for_each_entry(outp, &disp->outp, head) {
list_for_each_entry(outp, &disp->outps, head) {
nvkm_outp_fini(outp);
}
list_for_each_entry(conn, &disp->conn, head) {
list_for_each_entry(conn, &disp->conns, head) {
nvkm_conn_fini(conn);
}
......@@ -241,11 +241,11 @@ nvkm_disp_init(struct nvkm_engine *engine)
struct nvkm_outp *outp;
struct nvkm_ior *ior;
list_for_each_entry(conn, &disp->conn, head) {
list_for_each_entry(conn, &disp->conns, head) {
nvkm_conn_init(conn);
}
list_for_each_entry(outp, &disp->outp, head) {
list_for_each_entry(outp, &disp->outps, head) {
nvkm_outp_init(outp);
}
......@@ -258,7 +258,7 @@ nvkm_disp_init(struct nvkm_engine *engine)
/* Set 'normal' (ie. when it's attached to a head) state for
* each output resource to 'fully enabled'.
*/
list_for_each_entry(ior, &disp->ior, head) {
list_for_each_entry(ior, &disp->iors, head) {
ior->func->power(ior, true, true, true, true, true);
}
......@@ -325,12 +325,12 @@ nvkm_disp_oneinit(struct nvkm_engine *engine)
continue;
}
list_add_tail(&outp->head, &disp->outp);
list_add_tail(&outp->head, &disp->outps);
hpd = max(hpd, (u8)(dcbE.connector + 1));
}
/* Create connector objects based on available output paths. */
list_for_each_entry_safe(outp, outt, &disp->outp, head) {
list_for_each_entry_safe(outp, outt, &disp->outps, head) {
/* VBIOS data *should* give us the most useful information. */
data = nvbios_connEp(bios, outp->info.connector, &ver, &hdr,
&connE);
......@@ -344,7 +344,7 @@ nvkm_disp_oneinit(struct nvkm_engine *engine)
*/
int ccb_index = outp->info.i2c_index;
if (ccb_index != 0xf) {
list_for_each_entry(pair, &disp->outp, head) {
list_for_each_entry(pair, &disp->outps, head) {
if (pair->info.i2c_index == ccb_index) {
outp->conn = pair->conn;
break;
......@@ -364,7 +364,7 @@ nvkm_disp_oneinit(struct nvkm_engine *engine)
}
/* Check that we haven't already created this connector. */
list_for_each_entry(conn, &disp->conn, head) {
list_for_each_entry(conn, &disp->conns, head) {
if (conn->index == outp->info.connector) {
outp->conn = conn;
break;
......@@ -386,7 +386,7 @@ nvkm_disp_oneinit(struct nvkm_engine *engine)
continue;
}
list_add_tail(&outp->conn->head, &disp->conn);
list_add_tail(&outp->conn->head, &disp->conns);
}
ret = nvkm_event_init(&nvkm_disp_hpd_func, 3, hpd, &disp->hpd);
......@@ -402,7 +402,7 @@ nvkm_disp_oneinit(struct nvkm_engine *engine)
/* Enforce identity-mapped SOR assignment for panels, which have
* certain bits (ie. backlight controls) wired to a specific SOR.
*/
list_for_each_entry(outp, &disp->outp, head) {
list_for_each_entry(outp, &disp->outps, head) {
if (outp->conn->info.type == DCB_CONNECTOR_LVDS ||
outp->conn->info.type == DCB_CONNECTOR_eDP) {
ior = nvkm_ior_find(disp, SOR, ffs(outp->info.or) - 1);
......@@ -413,7 +413,7 @@ nvkm_disp_oneinit(struct nvkm_engine *engine)
}
i = 0;
list_for_each_entry(head, &disp->head, head)
list_for_each_entry(head, &disp->heads, head)
i = max(i, head->id + 1);
return nvkm_event_init(&nvkm_disp_vblank_func, 1, i, &disp->vblank);
......@@ -425,6 +425,8 @@ nvkm_disp_dtor(struct nvkm_engine *engine)
struct nvkm_disp *disp = nvkm_disp(engine);
struct nvkm_conn *conn;
struct nvkm_outp *outp;
struct nvkm_ior *ior;
struct nvkm_head *head;
void *data = disp;
if (disp->func->dtor)
......@@ -433,27 +435,25 @@ nvkm_disp_dtor(struct nvkm_engine *engine)
nvkm_event_fini(&disp->vblank);
nvkm_event_fini(&disp->hpd);
while (!list_empty(&disp->conn)) {
conn = list_first_entry(&disp->conn, typeof(*conn), head);
while (!list_empty(&disp->conns)) {
conn = list_first_entry(&disp->conns, typeof(*conn), head);
list_del(&conn->head);
nvkm_conn_del(&conn);
}
while (!list_empty(&disp->outp)) {
outp = list_first_entry(&disp->outp, typeof(*outp), head);
while (!list_empty(&disp->outps)) {
outp = list_first_entry(&disp->outps, typeof(*outp), head);
list_del(&outp->head);
nvkm_outp_del(&outp);
}
while (!list_empty(&disp->ior)) {
struct nvkm_ior *ior =
list_first_entry(&disp->ior, typeof(*ior), head);
while (!list_empty(&disp->iors)) {
ior = list_first_entry(&disp->iors, typeof(*ior), head);
nvkm_ior_del(&ior);
}
while (!list_empty(&disp->head)) {
struct nvkm_head *head =
list_first_entry(&disp->head, typeof(*head), head);
while (!list_empty(&disp->heads)) {
head = list_first_entry(&disp->heads, typeof(*head), head);
nvkm_head_del(&head);
}
......@@ -475,10 +475,10 @@ nvkm_disp_ctor(const struct nvkm_disp_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_disp *disp)
{
disp->func = func;
INIT_LIST_HEAD(&disp->head);
INIT_LIST_HEAD(&disp->ior);
INIT_LIST_HEAD(&disp->outp);
INIT_LIST_HEAD(&disp->conn);
INIT_LIST_HEAD(&disp->heads);
INIT_LIST_HEAD(&disp->iors);
INIT_LIST_HEAD(&disp->outps);
INIT_LIST_HEAD(&disp->conns);
spin_lock_init(&disp->client.lock);
return nvkm_engine_ctor(&nvkm_disp, device, type, inst, true, &disp->engine);
}
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c
View file @ 92fba5d3
......@@ -67,7 +67,7 @@ g84_disp_base_mthd = {
int
g84_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_base_new_(&nv50_disp_dmac_func, &g84_disp_base_mthd,
disp, 1, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c
View file @ 92fba5d3
......@@ -101,7 +101,7 @@ gf119_disp_base_mthd = {
int
gf119_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_base_new_(&gf119_disp_dmac_func, &gf119_disp_base_mthd,
disp, 1, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/basegp102.c
View file @ 92fba5d3
......@@ -25,7 +25,7 @@
int
gp102_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_base_new_(&gp102_disp_dmac_func, &gf119_disp_base_mthd,
disp, 1, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c
View file @ 92fba5d3
......@@ -32,7 +32,7 @@
int
nv50_disp_base_new_(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp *disp, int chid,
struct nvkm_disp *disp, int chid,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
......@@ -48,7 +48,7 @@ nv50_disp_base_new_(const struct nv50_disp_chan_func *func,
nvif_ioctl(parent, "create disp base channel dma vers %d "
"pushbuf %016llx head %d\n",
args->v0.version, args->v0.pushbuf, args->v0.head);
if (!nvkm_head_find(&disp->base, args->v0.head))
if (!nvkm_head_find(disp, args->v0.head))
return -EINVAL;
push = args->v0.pushbuf;
head = args->v0.head;
......@@ -112,7 +112,7 @@ nv50_disp_base_mthd = {
int
nv50_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_base_new_(&nv50_disp_dmac_func, &nv50_disp_base_mthd,
disp, 1, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/capsgv100.c
View file @ 92fba5d3
......@@ -24,7 +24,7 @@
struct gv100_disp_caps {
struct nvkm_object object;
struct nv50_disp *disp;
struct nvkm_disp *disp;
};
static int
......@@ -32,7 +32,7 @@ gv100_disp_caps_map(struct nvkm_object *object, void *argv, u32 argc,
enum nvkm_object_map *type, u64 *addr, u64 *size)
{
struct gv100_disp_caps *caps = gv100_disp_caps(object);
struct nvkm_device *device = caps->disp->base.engine.subdev.device;
struct nvkm_device *device = caps->disp->engine.subdev.device;
*type = NVKM_OBJECT_MAP_IO;
*addr = 0x640000 + device->func->resource_addr(device, 0);
*size = 0x1000;
......@@ -46,7 +46,7 @@ gv100_disp_caps = {
int
gv100_disp_caps_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
struct gv100_disp_caps *caps;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c
View file @ 92fba5d3
......@@ -26,8 +26,8 @@
static void
gf119_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
{
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000000 << index);
nvkm_wr32(device, 0x61008c, 0x00000001 << index);
}
......@@ -35,8 +35,8 @@ gf119_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
static void
gf119_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
{
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_wr32(device, 0x61008c, 0x00000001 << index);
nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000001 << index);
}
......@@ -51,7 +51,7 @@ gf119_disp_chan_uevent = {
void
gf119_disp_chan_intr(struct nv50_disp_chan *chan, bool en)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 mask = 0x00000001 << chan->chid.user;
if (!en) {
nvkm_mask(device, 0x610090, mask, 0x00000000);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
View file @ 92fba5d3
......@@ -35,10 +35,10 @@
#include <nvif/unpack.h>
static void
nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c,
nv50_disp_mthd_list(struct nvkm_disp *disp, int debug, u32 base, int c,
const struct nv50_disp_mthd_list *list, int inst)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int i;
......@@ -66,8 +66,8 @@ nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c,
void
nv50_disp_chan_mthd(struct nv50_disp_chan *chan, int debug)
{
struct nv50_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->engine.subdev;
const struct nv50_disp_chan_mthd *mthd = chan->mthd;
const struct nv50_disp_mthd_list *list;
int i, j;
......@@ -106,8 +106,8 @@ nv50_disp_chan_mthd(struct nv50_disp_chan *chan, int debug)
static void
nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
{
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_mask(device, 0x610028, 0x00000001 << index, 0x00000000 << index);
nvkm_wr32(device, 0x610020, 0x00000001 << index);
}
......@@ -115,14 +115,14 @@ nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
static void
nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
{
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_wr32(device, 0x610020, 0x00000001 << index);
nvkm_mask(device, 0x610028, 0x00000001 << index, 0x00000001 << index);
}
void
nv50_disp_chan_uevent_send(struct nv50_disp *disp, int chid)
nv50_disp_chan_uevent_send(struct nvkm_disp *disp, int chid)
{
struct nvif_notify_uevent_rep {
} rep;
......@@ -167,7 +167,7 @@ nv50_disp_chan_user(struct nv50_disp_chan *chan, u64 *psize)
void
nv50_disp_chan_intr(struct nv50_disp_chan *chan, bool en)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 mask = 0x00010001 << chan->chid.user;
const u32 data = en ? 0x00010000 << chan->chid.user : 0x00000000;
nvkm_mask(device, 0x610028, mask, data);
......@@ -177,7 +177,7 @@ static int
nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr, u32 *data)
{
struct nv50_disp_chan *chan = nv50_disp_chan(object);
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
u64 size, base = chan->func->user(chan, &size);
*data = nvkm_rd32(device, base + addr);
return 0;
......@@ -187,7 +187,7 @@ static int
nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
struct nv50_disp_chan *chan = nv50_disp_chan(object);
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
u64 size, base = chan->func->user(chan, &size);
nvkm_wr32(device, base + addr, data);
return 0;
......@@ -198,7 +198,7 @@ nv50_disp_chan_ntfy(struct nvkm_object *object, u32 type,
struct nvkm_event **pevent)
{
struct nv50_disp_chan *chan = nv50_disp_chan(object);
struct nv50_disp *disp = chan->disp;
struct nvkm_disp *disp = chan->disp;
switch (type) {
case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT:
*pevent = &disp->uevent;
......@@ -214,7 +214,7 @@ nv50_disp_chan_map(struct nvkm_object *object, void *argv, u32 argc,
enum nvkm_object_map *type, u64 *addr, u64 *size)
{
struct nv50_disp_chan *chan = nv50_disp_chan(object);
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u64 base = device->func->resource_addr(device, 0);
*type = NVKM_OBJECT_MAP_IO;
*addr = base + chan->func->user(chan, size);
......@@ -223,7 +223,7 @@ nv50_disp_chan_map(struct nvkm_object *object, void *argv, u32 argc,
struct nv50_disp_chan_object {
struct nvkm_oproxy oproxy;
struct nv50_disp *disp;
struct nvkm_disp *disp;
int hash;
};
......@@ -245,8 +245,8 @@ nv50_disp_chan_child_new(const struct nvkm_oclass *oclass,
void *argv, u32 argc, struct nvkm_object **pobject)
{
struct nv50_disp_chan *chan = nv50_disp_chan(oclass->parent);
struct nv50_disp *disp = chan->disp;
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_disp *disp = chan->disp;
struct nvkm_device *device = disp->engine.subdev.device;
const struct nvkm_device_oclass *sclass = oclass->priv;
struct nv50_disp_chan_object *object;
int ret;
......@@ -274,7 +274,7 @@ nv50_disp_chan_child_get(struct nvkm_object *object, int index,
struct nvkm_oclass *sclass)
{
struct nv50_disp_chan *chan = nv50_disp_chan(object);
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const struct nvkm_device_oclass *oclass = NULL;
if (chan->func->bind)
......@@ -315,7 +315,7 @@ static void *
nv50_disp_chan_dtor(struct nvkm_object *object)
{
struct nv50_disp_chan *chan = nv50_disp_chan(object);
struct nv50_disp *disp = chan->disp;
struct nvkm_disp *disp = chan->disp;
if (chan->chid.user >= 0)
disp->chan[chan->chid.user] = NULL;
nvkm_memory_unref(&chan->memory);
......@@ -337,7 +337,7 @@ nv50_disp_chan = {
int
nv50_disp_chan_new_(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp *disp, int ctrl, int user, int head,
struct nvkm_disp *disp, int ctrl, int user, int head,
const struct nvkm_oclass *oclass,
struct nvkm_object **pobject)
{
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
View file @ 92fba5d3
......@@ -3,13 +3,13 @@
#define __NV50_DISP_CHAN_H__
#define nv50_disp_chan(p) container_of((p), struct nv50_disp_chan, object)
#include <core/object.h>
#include "nv50.h"
#include "priv.h"
struct nv50_disp_root;
struct nv50_disp_chan {
const struct nv50_disp_chan_func *func;
const struct nv50_disp_chan_mthd *mthd;
struct nv50_disp *disp;
struct nvkm_disp *disp;
struct {
int ctrl;
......@@ -35,11 +35,11 @@ struct nv50_disp_chan_func {
int nv50_disp_chan_new_(const struct nv50_disp_chan_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp *, int ctrl, int user, int head,
struct nvkm_disp *, int ctrl, int user, int head,
const struct nvkm_oclass *, struct nvkm_object **);
int nv50_disp_dmac_new_(const struct nv50_disp_chan_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp *, int chid, int head, u64 push,
struct nvkm_disp *, int chid, int head, u64 push,
const struct nvkm_oclass *, struct nvkm_object **);
void nv50_disp_chan_intr(struct nv50_disp_chan *, bool);
......@@ -65,88 +65,88 @@ void gv100_disp_dmac_fini(struct nv50_disp_chan *);
int gv100_disp_dmac_bind(struct nv50_disp_chan *, struct nvkm_object *, u32);
int nv50_disp_curs_new_(const struct nv50_disp_chan_func *,
struct nv50_disp *, int ctrl, int user,
struct nvkm_disp *, int ctrl, int user,
const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_oimm_new_(const struct nv50_disp_chan_func *,
struct nv50_disp *, int ctrl, int user,
struct nvkm_disp *, int ctrl, int user,
const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_base_new_(const struct nv50_disp_chan_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp *, int chid,
struct nvkm_disp *, int chid,
const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_core_new_(const struct nv50_disp_chan_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp *, int chid,
struct nvkm_disp *, int chid,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_ovly_new_(const struct nv50_disp_chan_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp *, int chid,
struct nvkm_disp *, int chid,
const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_curs_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int nv50_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int nv50_disp_base_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int nv50_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int nv50_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int g84_disp_base_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int g84_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int g84_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int g94_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gt200_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gf119_disp_curs_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gf119_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gf119_disp_base_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gf119_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gf119_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gk104_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gk104_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gp102_disp_curs_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gp102_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gp102_disp_base_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gp102_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gp102_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gv100_disp_curs_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gv100_disp_wimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gv100_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
int gv100_disp_wndw_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
struct nv50_disp_mthd_list {
u32 mthd;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c
View file @ 92fba5d3
......@@ -104,7 +104,7 @@ g84_disp_core_mthd = {
int
g84_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&nv50_disp_core_func, &g84_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c
View file @ 92fba5d3
......@@ -50,7 +50,7 @@ g94_disp_core_mthd = {
int
g94_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&nv50_disp_core_func, &g94_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c
View file @ 92fba5d3
......@@ -169,7 +169,7 @@ gf119_disp_core_mthd = {
void
gf119_disp_core_fini(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
/* deactivate channel */
......@@ -189,7 +189,7 @@ gf119_disp_core_fini(struct nv50_disp_chan *chan)
static int
gf119_disp_core_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
/* initialise channel for dma command submission */
......@@ -224,7 +224,7 @@ gf119_disp_core_func = {
int
gf119_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&gf119_disp_core_func, &gf119_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c
View file @ 92fba5d3
......@@ -119,7 +119,7 @@ gk104_disp_core_mthd = {
int
gk104_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&gf119_disp_core_func, &gk104_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c
View file @ 92fba5d3
......@@ -28,7 +28,7 @@
static int
gp102_disp_core_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
/* initialise channel for dma command submission */
......@@ -63,7 +63,7 @@ gp102_disp_core_func = {
int
gp102_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&gp102_disp_core_func, &gk104_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c
View file @ 92fba5d3
......@@ -137,7 +137,7 @@ gv100_disp_core_mthd = {
static int
gv100_disp_core_idle(struct nv50_disp_chan *chan)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
nvkm_msec(device, 2000,
u32 stat = nvkm_rd32(device, 0x610630);
if ((stat & 0x001f0000) == 0x000b0000)
......@@ -156,7 +156,7 @@ gv100_disp_core_user(struct nv50_disp_chan *chan, u64 *psize)
static void
gv100_disp_core_intr(struct nv50_disp_chan *chan, bool en)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 mask = 0x00000001;
const u32 data = en ? mask : 0;
nvkm_mask(device, 0x611dac, mask, data);
......@@ -165,7 +165,7 @@ gv100_disp_core_intr(struct nv50_disp_chan *chan, bool en)
static void
gv100_disp_core_fini(struct nv50_disp_chan *chan)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000);
gv100_disp_core_idle(chan);
nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000);
......@@ -175,7 +175,7 @@ gv100_disp_core_fini(struct nv50_disp_chan *chan)
static int
gv100_disp_core_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push));
......@@ -200,7 +200,7 @@ gv100_disp_core = {
int
gv100_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&gv100_disp_core, &gv100_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c
View file @ 92fba5d3
......@@ -32,7 +32,7 @@
int
nv50_disp_core_new_(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp *disp, int chid,
struct nvkm_disp *disp, int chid,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
......@@ -166,7 +166,7 @@ nv50_disp_core_mthd = {
static void
nv50_disp_core_fini(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
/* deactivate channel */
......@@ -186,7 +186,7 @@ nv50_disp_core_fini(struct nv50_disp_chan *chan)
static int
nv50_disp_core_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
/* attempt to unstick channel from some unknown state */
......@@ -227,7 +227,7 @@ nv50_disp_core_func = {
int
nv50_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&nv50_disp_core_func, &nv50_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c
View file @ 92fba5d3
......@@ -25,7 +25,7 @@
int
gf119_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_curs_new_(&gf119_disp_pioc_func, disp, 13, 13,
oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgp102.c
View file @ 92fba5d3
......@@ -25,7 +25,7 @@
int
gp102_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_curs_new_(&gf119_disp_pioc_func, disp, 13, 17,
oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c
View file @ 92fba5d3
......@@ -26,7 +26,7 @@
static int
gv100_disp_curs_idle(struct nv50_disp_chan *chan)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 soff = (chan->chid.ctrl - 1) * 0x04;
nvkm_msec(device, 2000,
u32 stat = nvkm_rd32(device, 0x610664 + soff);
......@@ -39,7 +39,7 @@ gv100_disp_curs_idle(struct nv50_disp_chan *chan)
static void
gv100_disp_curs_intr(struct nv50_disp_chan *chan, bool en)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 mask = 0x00010000 << chan->head;
const u32 data = en ? mask : 0;
nvkm_mask(device, 0x611dac, mask, data);
......@@ -48,7 +48,7 @@ gv100_disp_curs_intr(struct nv50_disp_chan *chan, bool en)
static void
gv100_disp_curs_fini(struct nv50_disp_chan *chan)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 hoff = chan->chid.ctrl * 4;
nvkm_mask(device, 0x6104e0 + hoff, 0x00000010, 0x00000010);
gv100_disp_curs_idle(chan);
......@@ -58,7 +58,7 @@ gv100_disp_curs_fini(struct nv50_disp_chan *chan)
static int
gv100_disp_curs_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
nvkm_wr32(device, 0x6104e0 + chan->chid.ctrl * 4, 0x00000001);
return gv100_disp_curs_idle(chan);
......@@ -74,7 +74,7 @@ gv100_disp_curs = {
int
gv100_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_curs_new_(&gv100_disp_curs, disp, 73, 73,
oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c
View file @ 92fba5d3
......@@ -31,7 +31,7 @@
int
nv50_disp_curs_new_(const struct nv50_disp_chan_func *func,
struct nv50_disp *disp, int ctrl, int user,
struct nvkm_disp *disp, int ctrl, int user,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
......@@ -45,7 +45,7 @@ nv50_disp_curs_new_(const struct nv50_disp_chan_func *func,
if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create disp cursor vers %d head %d\n",
args->v0.version, args->v0.head);
if (!nvkm_head_find(&disp->base, args->v0.head))
if (!nvkm_head_find(disp, args->v0.head))
return -EINVAL;
head = args->v0.head;
} else
......@@ -57,7 +57,7 @@ nv50_disp_curs_new_(const struct nv50_disp_chan_func *func,
int
nv50_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_curs_new_(&nv50_disp_pioc_func, disp, 7, 7,
oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c
View file @ 92fba5d3
......@@ -38,7 +38,7 @@ gf119_disp_dmac_bind(struct nv50_disp_chan *chan,
void
gf119_disp_dmac_fini(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......@@ -60,7 +60,7 @@ gf119_disp_dmac_fini(struct nv50_disp_chan *chan)
static int
gf119_disp_dmac_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c
View file @ 92fba5d3
......@@ -28,7 +28,7 @@
static int
gp102_disp_dmac_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c
View file @ 92fba5d3
......@@ -27,7 +27,7 @@
static int
gv100_disp_dmac_idle(struct nv50_disp_chan *chan)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 soff = (chan->chid.ctrl - 1) * 0x04;
nvkm_msec(device, 2000,
u32 stat = nvkm_rd32(device, 0x610664 + soff);
......@@ -49,7 +49,7 @@ gv100_disp_dmac_bind(struct nv50_disp_chan *chan,
void
gv100_disp_dmac_fini(struct nv50_disp_chan *chan)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 uoff = (chan->chid.ctrl - 1) * 0x1000;
const u32 coff = chan->chid.ctrl * 0x04;
nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000);
......@@ -61,7 +61,7 @@ gv100_disp_dmac_fini(struct nv50_disp_chan *chan)
int
gv100_disp_dmac_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
const u32 uoff = (chan->chid.ctrl - 1) * 0x1000;
const u32 poff = chan->chid.ctrl * 0x10;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c
View file @ 92fba5d3
......@@ -33,7 +33,7 @@
int
nv50_disp_dmac_new_(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp *disp, int chid, int head, u64 push,
struct nvkm_disp *disp, int chid, int head, u64 push,
const struct nvkm_oclass *oclass,
struct nvkm_object **pobject)
{
......@@ -79,7 +79,7 @@ nv50_disp_dmac_bind(struct nv50_disp_chan *chan,
static void
nv50_disp_dmac_fini(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......@@ -101,7 +101,7 @@ nv50_disp_dmac_fini(struct nv50_disp_chan *chan)
static int
nv50_disp_dmac_init(struct nv50_disp_chan *chan)
{
struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c
View file @ 92fba5d3
......@@ -508,7 +508,7 @@ nvkm_dp_acquire(struct nvkm_outp *outp)
mutex_lock(&outp->dp.mutex);
/* Check that link configuration meets current requirements. */
list_for_each_entry(head, &outp->disp->head, head) {
list_for_each_entry(head, &outp->disp->heads, head) {
if (ior->asy.head & (1 << head->id)) {
u32 khz = (head->asy.hz >> ior->asy.rgdiv) / 1000;
datakbps += khz * head->asy.or.depth;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,19 +30,16 @@ static const struct nvkm_disp_func
g84_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = nv50_disp_init,
.fini_ = nv50_disp_fini,
.intr_ = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.init = nv50_disp_init,
.fini = nv50_disp_fini,
.intr = nv50_disp_intr,
.super = nv50_disp_super,
.root = &g84_disp_root_oclass,
.uevent = &nv50_disp_chan_uevent,
.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &g84_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,19 +30,16 @@ static const struct nvkm_disp_func
g94_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = nv50_disp_init,
.fini_ = nv50_disp_fini,
.intr_ = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.init = nv50_disp_init,
.fini = nv50_disp_fini,
.intr = nv50_disp_intr,
.super = nv50_disp_super,
.root = &g94_disp_root_oclass,
.uevent = &nv50_disp_chan_uevent,
.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = g94_sor_cnt, .new = g94_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &g94_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c
View file @ 92fba5d3
......@@ -19,7 +19,7 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "channv50.h"
......@@ -29,19 +29,16 @@ static const struct nvkm_disp_func
ga102_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = tu102_disp_init,
.fini_ = gv100_disp_fini,
.intr_ = gv100_disp_intr,
.uevent = &gv100_disp_chan_uevent,
.init = tu102_disp_init,
.fini = gv100_disp_fini,
.intr = gv100_disp_intr,
.super = gv100_disp_super,
.root = &ga102_disp_root_oclass,
.uevent = &gv100_disp_chan_uevent,
.wndw = { .cnt = gv100_disp_wndw_cnt },
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
.sor = { .cnt = gv100_sor_cnt, .new = ga102_sor_new },
.ramht_size = 0x2000,
.root = &ga102_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
View file @ 92fba5d3
......@@ -21,9 +21,10 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "outp.h"
#include "channv50.h"
#include "rootnv50.h"
......@@ -33,15 +34,14 @@
void
gf119_disp_super(struct work_struct *work)
{
struct nv50_disp *disp =
container_of(work, struct nv50_disp, supervisor);
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_disp *disp = container_of(work, struct nvkm_disp, supervisor);
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_head *head;
u32 mask[4];
nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super));
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800));
HEAD_DBG(head, "%08x", mask[head->id]);
}
......@@ -49,47 +49,47 @@ gf119_disp_super(struct work_struct *work)
if (disp->super & 0x00000001) {
nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
nv50_disp_super_1(disp);
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00001000))
continue;
nv50_disp_super_1_0(disp, head);
}
} else
if (disp->super & 0x00000002) {
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00001000))
continue;
nv50_disp_super_2_0(disp, head);
}
nvkm_outp_route(&disp->base);
list_for_each_entry(head, &disp->base.head, head) {
nvkm_outp_route(disp);
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00010000))
continue;
nv50_disp_super_2_1(disp, head);
}
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00001000))
continue;
nv50_disp_super_2_2(disp, head);
}
} else
if (disp->super & 0x00000004) {
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00001000))
continue;
nv50_disp_super_3_0(disp, head);
}
}
list_for_each_entry(head, &disp->base.head, head)
list_for_each_entry(head, &disp->heads, head)
nvkm_wr32(device, 0x6101d4 + (head->id * 0x800), 0x00000000);
nvkm_wr32(device, 0x6101d0, 0x80000000);
}
void
gf119_disp_intr_error(struct nv50_disp *disp, int chid)
gf119_disp_intr_error(struct nvkm_disp *disp, int chid)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x6101f0 + (chid * 12));
u32 type = (stat & 0x00007000) >> 12;
......@@ -119,9 +119,9 @@ gf119_disp_intr_error(struct nv50_disp *disp, int chid)
}
void
gf119_disp_intr(struct nv50_disp *disp)
gf119_disp_intr(struct nvkm_disp *disp)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_head *head;
u32 intr = nvkm_rd32(device, 0x610088);
......@@ -161,13 +161,13 @@ gf119_disp_intr(struct nv50_disp *disp)
intr &= ~0x00100000;
}
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
const u32 hoff = head->id * 0x800;
u32 mask = 0x01000000 << head->id;
if (mask & intr) {
u32 stat = nvkm_rd32(device, 0x6100bc + hoff);
if (stat & 0x00000001)
nvkm_disp_vblank(&disp->base, head->id);
nvkm_disp_vblank(disp, head->id);
nvkm_mask(device, 0x6100bc + hoff, 0, 0);
nvkm_rd32(device, 0x6100c0 + hoff);
}
......@@ -175,17 +175,17 @@ gf119_disp_intr(struct nv50_disp *disp)
}
void
gf119_disp_fini(struct nv50_disp *disp)
gf119_disp_fini(struct nvkm_disp *disp)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_device *device = disp->engine.subdev.device;
/* disable all interrupts */
nvkm_wr32(device, 0x6100b0, 0x00000000);
}
int
gf119_disp_init(struct nv50_disp *disp)
gf119_disp_init(struct nvkm_disp *disp)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_device *device = disp->engine.subdev.device;
struct nvkm_head *head;
u32 tmp;
int i;
......@@ -196,7 +196,7 @@ gf119_disp_init(struct nv50_disp *disp)
*/
/* ... CRTC caps */
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
const u32 hoff = head->id * 0x800;
tmp = nvkm_rd32(device, 0x616104 + hoff);
nvkm_wr32(device, 0x6101b4 + hoff, tmp);
......@@ -243,7 +243,7 @@ gf119_disp_init(struct nv50_disp *disp)
*
* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
*/
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
const u32 hoff = head->id * 0x800;
nvkm_mask(device, 0x616308 + hoff, 0x00000111, 0x00000010);
}
......@@ -255,19 +255,16 @@ static const struct nvkm_disp_func
gf119_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = gf119_disp_init,
.fini_ = gf119_disp_fini,
.intr_ = gf119_disp_intr,
.init = gf119_disp_init,
.fini = gf119_disp_fini,
.intr = gf119_disp_intr,
.intr_error = gf119_disp_intr_error,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_super,
.root = &gf119_disp_root_oclass,
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gf119_sor_new },
.root = &gf119_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,19 +30,16 @@ static const struct nvkm_disp_func
gk104_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = gf119_disp_init,
.fini_ = gf119_disp_fini,
.intr_ = gf119_disp_intr,
.init = gf119_disp_init,
.fini = gf119_disp_fini,
.intr = gf119_disp_intr,
.intr_error = gf119_disp_intr_error,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_super,
.root = &gk104_disp_root_oclass,
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
.root = &gk104_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,19 +30,16 @@ static const struct nvkm_disp_func
gk110_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = gf119_disp_init,
.fini_ = gf119_disp_fini,
.intr_ = gf119_disp_intr,
.init = gf119_disp_init,
.fini = gf119_disp_fini,
.intr = gf119_disp_intr,
.intr_error = gf119_disp_intr_error,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_super,
.root = &gk110_disp_root_oclass,
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
.root = &gk110_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,19 +30,16 @@ static const struct nvkm_disp_func
gm107_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = gf119_disp_init,
.fini_ = gf119_disp_fini,
.intr_ = gf119_disp_intr,
.init = gf119_disp_init,
.fini = gf119_disp_fini,
.intr = gf119_disp_intr,
.intr_error = gf119_disp_intr_error,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_super,
.root = &gm107_disp_root_oclass,
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gm107_sor_new },
.root = &gm107_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,19 +30,16 @@ static const struct nvkm_disp_func
gm200_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = gf119_disp_init,
.fini_ = gf119_disp_fini,
.intr_ = gf119_disp_intr,
.init = gf119_disp_init,
.fini = gf119_disp_fini,
.intr = gf119_disp_intr,
.intr_error = gf119_disp_intr_error,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_super,
.root = &gm200_disp_root_oclass,
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
.sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new },
.root = &gm200_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,18 +30,15 @@ static const struct nvkm_disp_func
gp100_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = gf119_disp_init,
.fini_ = gf119_disp_fini,
.intr_ = gf119_disp_intr,
.init = gf119_disp_init,
.fini = gf119_disp_fini,
.intr = gf119_disp_intr,
.intr_error = gf119_disp_intr_error,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_super,
.root = &gp100_disp_root_oclass,
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new },
.root = &gp100_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
View file @ 92fba5d3
......@@ -21,16 +21,16 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "channv50.h"
#include "rootnv50.h"
static void
gp102_disp_intr_error(struct nv50_disp *disp, int chid)
gp102_disp_intr_error(struct nvkm_disp *disp, int chid)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12));
u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12));
......@@ -57,18 +57,15 @@ static const struct nvkm_disp_func
gp102_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = gf119_disp_init,
.fini_ = gf119_disp_fini,
.intr_ = gf119_disp_intr,
.init = gf119_disp_init,
.fini = gf119_disp_fini,
.intr = gf119_disp_intr,
.intr_error = gp102_disp_intr_error,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_super,
.root = &gp102_disp_root_oclass,
.uevent = &gf119_disp_chan_uevent,
.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
.sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new },
.root = &gp102_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,19 +30,16 @@ static const struct nvkm_disp_func
gt200_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = nv50_disp_init,
.fini_ = nv50_disp_fini,
.intr_ = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.init = nv50_disp_init,
.fini = nv50_disp_fini,
.intr = nv50_disp_intr,
.super = nv50_disp_super,
.root = &gt200_disp_root_oclass,
.uevent = &nv50_disp_chan_uevent,
.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &gt200_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
View file @ 92fba5d3
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -30,19 +30,16 @@ static const struct nvkm_disp_func
gt215_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = nv50_disp_init,
.fini_ = nv50_disp_fini,
.intr_ = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.init = nv50_disp_init,
.fini = nv50_disp_fini,
.intr = nv50_disp_intr,
.super = nv50_disp_super,
.root = &gt215_disp_root_oclass,
.uevent = &nv50_disp_chan_uevent,
.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = g94_sor_cnt, .new = gt215_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &gt215_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
View file @ 92fba5d3
......@@ -19,9 +19,10 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "outp.h"
#include "channv50.h"
#include "rootnv50.h"
......@@ -39,16 +40,15 @@ gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask)
void
gv100_disp_super(struct work_struct *work)
{
struct nv50_disp *disp =
container_of(work, struct nv50_disp, supervisor);
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_disp *disp = container_of(work, struct nvkm_disp, supervisor);
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_head *head;
u32 stat = nvkm_rd32(device, 0x6107a8);
u32 mask[4];
nvkm_debug(subdev, "supervisor %d: %08x\n", ffs(disp->super), stat);
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4));
HEAD_DBG(head, "%08x", mask[head->id]);
}
......@@ -56,47 +56,47 @@ gv100_disp_super(struct work_struct *work)
if (disp->super & 0x00000001) {
nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
nv50_disp_super_1(disp);
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00001000))
continue;
nv50_disp_super_1_0(disp, head);
}
} else
if (disp->super & 0x00000002) {
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00001000))
continue;
nv50_disp_super_2_0(disp, head);
}
nvkm_outp_route(&disp->base);
list_for_each_entry(head, &disp->base.head, head) {
nvkm_outp_route(disp);
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00010000))
continue;
nv50_disp_super_2_1(disp, head);
}
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00001000))
continue;
nv50_disp_super_2_2(disp, head);
}
} else
if (disp->super & 0x00000004) {
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (!(mask[head->id] & 0x00001000))
continue;
nv50_disp_super_3_0(disp, head);
}
}
list_for_each_entry(head, &disp->base.head, head)
list_for_each_entry(head, &disp->heads, head)
nvkm_wr32(device, 0x6107ac + (head->id * 4), 0x00000000);
nvkm_wr32(device, 0x6107a8, 0x80000000);
}
static void
gv100_disp_exception(struct nv50_disp *disp, int chid)
gv100_disp_exception(struct nvkm_disp *disp, int chid)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12));
u32 type = (stat & 0x00007000) >> 12;
......@@ -136,9 +136,9 @@ gv100_disp_exception(struct nv50_disp *disp, int chid)
}
static void
gv100_disp_intr_ctrl_disp(struct nv50_disp *disp)
gv100_disp_intr_ctrl_disp(struct nvkm_disp *disp)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x611c30);
......@@ -184,9 +184,9 @@ gv100_disp_intr_ctrl_disp(struct nv50_disp *disp)
}
static void
gv100_disp_intr_exc_other(struct nv50_disp *disp)
gv100_disp_intr_exc_other(struct nvkm_disp *disp)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x611854);
unsigned long mask;
......@@ -213,9 +213,9 @@ gv100_disp_intr_exc_other(struct nv50_disp *disp)
}
static void
gv100_disp_intr_exc_winim(struct nv50_disp *disp)
gv100_disp_intr_exc_winim(struct nvkm_disp *disp)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
unsigned long stat = nvkm_rd32(device, 0x611850);
int wndw;
......@@ -233,9 +233,9 @@ gv100_disp_intr_exc_winim(struct nv50_disp *disp)
}
static void
gv100_disp_intr_exc_win(struct nv50_disp *disp)
gv100_disp_intr_exc_win(struct nvkm_disp *disp)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
unsigned long stat = nvkm_rd32(device, 0x61184c);
int wndw;
......@@ -253,9 +253,9 @@ gv100_disp_intr_exc_win(struct nv50_disp *disp)
}
static void
gv100_disp_intr_head_timing(struct nv50_disp *disp, int head)
gv100_disp_intr_head_timing(struct nvkm_disp *disp, int head)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x611800 + (head * 0x04));
......@@ -266,7 +266,7 @@ gv100_disp_intr_head_timing(struct nv50_disp *disp, int head)
}
if (stat & 0x00000004) {
nvkm_disp_vblank(&disp->base, head);
nvkm_disp_vblank(disp, head);
nvkm_wr32(device, 0x611800 + (head * 0x04), 0x00000004);
stat &= ~0x00000004;
}
......@@ -278,9 +278,9 @@ gv100_disp_intr_head_timing(struct nv50_disp *disp, int head)
}
void
gv100_disp_intr(struct nv50_disp *disp)
gv100_disp_intr(struct nvkm_disp *disp)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x611ec0);
unsigned long mask;
......@@ -318,16 +318,16 @@ gv100_disp_intr(struct nv50_disp *disp)
}
void
gv100_disp_fini(struct nv50_disp *disp)
gv100_disp_fini(struct nvkm_disp *disp)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_wr32(device, 0x611db0, 0x00000000);
}
static int
gv100_disp_init(struct nv50_disp *disp)
gv100_disp_init(struct nvkm_disp *disp)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_device *device = disp->engine.subdev.device;
struct nvkm_head *head;
int i, j;
u32 tmp;
......@@ -354,7 +354,7 @@ gv100_disp_init(struct nv50_disp *disp)
}
/* Head capabilities. */
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
const int id = head->id;
/* RG. */
......@@ -414,7 +414,7 @@ gv100_disp_init(struct nv50_disp *disp)
nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */
/* HEAD_TIMING(n): VBLANK. */
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
const u32 hoff = head->id * 4;
nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */
nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */
......@@ -430,19 +430,16 @@ static const struct nvkm_disp_func
gv100_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = gv100_disp_init,
.fini_ = gv100_disp_fini,
.intr_ = gv100_disp_intr,
.uevent = &gv100_disp_chan_uevent,
.init = gv100_disp_init,
.fini = gv100_disp_fini,
.intr = gv100_disp_intr,
.super = gv100_disp_super,
.root = &gv100_disp_root_oclass,
.uevent = &gv100_disp_chan_uevent,
.wndw = { .cnt = gv100_disp_wndw_cnt },
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
.sor = { .cnt = gv100_sor_cnt, .new = gv100_sor_new },
.ramht_size = 0x2000,
.root = &gv100_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c
View file @ 92fba5d3
......@@ -32,7 +32,7 @@ struct nvkm_head *
nvkm_head_find(struct nvkm_disp *disp, int id)
{
struct nvkm_head *head;
list_for_each_entry(head, &disp->head, head) {
list_for_each_entry(head, &disp->heads, head) {
if (head->id == id)
return head;
}
......@@ -99,7 +99,7 @@ nvkm_head_new_(const struct nvkm_head_func *func,
head->func = func;
head->disp = disp;
head->id = id;
list_add_tail(&head->head, &disp->head);
list_add_tail(&head->head, &disp->heads);
HEAD_DBG(head, "ctor");
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c
View file @ 92fba5d3
......@@ -34,7 +34,7 @@ struct nvkm_ior *
nvkm_ior_find(struct nvkm_disp *disp, enum nvkm_ior_type type, int id)
{
struct nvkm_ior *ior;
list_for_each_entry(ior, &disp->ior, head) {
list_for_each_entry(ior, &disp->iors, head) {
if (ior->type == type && (id < 0 || ior->id == id))
return ior;
}
......@@ -64,9 +64,8 @@ nvkm_ior_new_(const struct nvkm_ior_func *func, struct nvkm_disp *disp,
ior->disp = disp;
ior->type = type;
ior->id = id;
snprintf(ior->name, sizeof(ior->name), "%s-%d",
nvkm_ior_name[ior->type], ior->id);
list_add_tail(&ior->head, &disp->ior);
snprintf(ior->name, sizeof(ior->name), "%s-%d", nvkm_ior_name[ior->type], ior->id);
list_add_tail(&ior->head, &disp->iors);
IOR_DBG(ior, "ctor");
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
View file @ 92fba5d3
......@@ -19,7 +19,7 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -28,19 +28,16 @@ static const struct nvkm_disp_func
mcp77_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = nv50_disp_init,
.fini_ = nv50_disp_fini,
.intr_ = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.init = nv50_disp_init,
.fini = nv50_disp_fini,
.intr = nv50_disp_intr,
.super = nv50_disp_super,
.root = &g94_disp_root_oclass,
.uevent = &nv50_disp_chan_uevent,
.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = g94_sor_cnt, .new = mcp77_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &g94_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
View file @ 92fba5d3
......@@ -19,7 +19,7 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "rootnv50.h"
......@@ -28,19 +28,16 @@ static const struct nvkm_disp_func
mcp89_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = nv50_disp_init,
.fini_ = nv50_disp_fini,
.intr_ = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.init = nv50_disp_init,
.fini = nv50_disp_fini,
.intr = nv50_disp_intr,
.super = nv50_disp_super,
.root = &gt215_disp_root_oclass,
.uevent = &nv50_disp_chan_uevent,
.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
.sor = { .cnt = g94_sor_cnt, .new = mcp89_sor_new },
.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
.root = &gt215_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h deleted 100644 → 0
View file @ 0407b33f
/* SPDX-License-Identifier: MIT */
#ifndef __NV50_DISP_H__
#define __NV50_DISP_H__
#define nv50_disp(p) container_of((p), struct nv50_disp, base)
#include "priv.h"
struct nvkm_head;
#include <core/enum.h>
struct nv50_disp {
const struct nvkm_disp_func *func;
struct nvkm_disp base;
struct workqueue_struct *wq;
struct work_struct supervisor;
u32 super;
struct nvkm_event uevent;
struct {
unsigned long mask;
int nr;
} wndw, head, dac;
struct {
unsigned long mask;
int nr;
u32 lvdsconf;
} sor;
struct {
unsigned long mask;
int nr;
u8 type[3];
} pior;
struct nvkm_gpuobj *inst;
struct nvkm_ramht *ramht;
struct nv50_disp_chan *chan[81];
};
void nv50_disp_super_1(struct nv50_disp *);
void nv50_disp_super_1_0(struct nv50_disp *, struct nvkm_head *);
void nv50_disp_super_2_0(struct nv50_disp *, struct nvkm_head *);
void nv50_disp_super_2_1(struct nv50_disp *, struct nvkm_head *);
void nv50_disp_super_2_2(struct nv50_disp *, struct nvkm_head *);
void nv50_disp_super_3_0(struct nv50_disp *, struct nvkm_head *);
int nv50_disp_new_(const struct nvkm_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_disp **);
int nv50_disp_init(struct nv50_disp *);
void nv50_disp_fini(struct nv50_disp *);
void nv50_disp_intr(struct nv50_disp *);
void nv50_disp_super(struct work_struct *);
extern const struct nvkm_enum nv50_disp_intr_error_type[];
int gf119_disp_init(struct nv50_disp *);
void gf119_disp_fini(struct nv50_disp *);
void gf119_disp_intr(struct nv50_disp *);
void gf119_disp_super(struct work_struct *);
void gf119_disp_intr_error(struct nv50_disp *, int);
void gv100_disp_fini(struct nv50_disp *);
void gv100_disp_intr(struct nv50_disp *);
void gv100_disp_super(struct work_struct *);
int gv100_disp_wndw_cnt(struct nvkm_disp *, unsigned long *);
int tu102_disp_init(struct nv50_disp *);
void nv50_disp_dptmds_war_2(struct nv50_disp *, struct dcb_output *);
void nv50_disp_dptmds_war_3(struct nv50_disp *, struct dcb_output *);
void nv50_disp_update_sppll1(struct nv50_disp *);
extern const struct nvkm_event_func nv50_disp_chan_uevent;
int nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *);
void nv50_disp_chan_uevent_send(struct nv50_disp *, int);
extern const struct nvkm_event_func gf119_disp_chan_uevent;
extern const struct nvkm_event_func gv100_disp_chan_uevent;
#endif
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c
View file @ 92fba5d3
......@@ -25,7 +25,7 @@
int
gf119_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_oimm_new_(&gf119_disp_pioc_func, disp, 9, 9,
oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgp102.c
View file @ 92fba5d3
......@@ -25,7 +25,7 @@
int
gp102_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_oimm_new_(&gf119_disp_pioc_func, disp, 9, 13,
oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c
View file @ 92fba5d3
......@@ -31,7 +31,7 @@
int
nv50_disp_oimm_new_(const struct nv50_disp_chan_func *func,
struct nv50_disp *disp, int ctrl, int user,
struct nvkm_disp *disp, int ctrl, int user,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
......@@ -45,7 +45,7 @@ nv50_disp_oimm_new_(const struct nv50_disp_chan_func *func,
if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create disp overlay vers %d head %d\n",
args->v0.version, args->v0.head);
if (!nvkm_head_find(&disp->base, args->v0.head))
if (!nvkm_head_find(disp, args->v0.head))
return -EINVAL;
head = args->v0.head;
} else
......@@ -57,7 +57,7 @@ nv50_disp_oimm_new_(const struct nv50_disp_chan_func *func,
int
nv50_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_oimm_new_(&nv50_disp_pioc_func, disp, 5, 5,
oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c
View file @ 92fba5d3
......@@ -35,7 +35,7 @@ nvkm_outp_route(struct nvkm_disp *disp)
struct nvkm_outp *outp;
struct nvkm_ior *ior;
list_for_each_entry(ior, &disp->ior, head) {
list_for_each_entry(ior, &disp->iors, head) {
if ((outp = ior->arm.outp) && ior->arm.outp != ior->asy.outp) {
OUTP_DBG(outp, "release %s", ior->name);
if (ior->func->route.set)
......@@ -44,7 +44,7 @@ nvkm_outp_route(struct nvkm_disp *disp)
}
}
list_for_each_entry(ior, &disp->ior, head) {
list_for_each_entry(ior, &disp->iors, head) {
if ((outp = ior->asy.outp)) {
OUTP_DBG(outp, "acquire %s", ior->name);
if (ior->asy.outp != ior->arm.outp) {
......@@ -119,7 +119,7 @@ nvkm_outp_acquire_hda(struct nvkm_outp *outp, enum nvkm_ior_type type,
struct nvkm_ior *ior;
/* Failing that, a completely unused OR is the next best thing. */
list_for_each_entry(ior, &outp->disp->ior, head) {
list_for_each_entry(ior, &outp->disp->iors, head) {
if (!ior->identity && !!ior->func->hda.hpd == hda &&
!ior->asy.outp && ior->type == type && !ior->arm.outp &&
(ior->func->route.set || ior->id == __ffs(outp->info.or)))
......@@ -129,7 +129,7 @@ nvkm_outp_acquire_hda(struct nvkm_outp *outp, enum nvkm_ior_type type,
/* Last resort is to assign an OR that's already active on HW,
* but will be released during the next modeset.
*/
list_for_each_entry(ior, &outp->disp->ior, head) {
list_for_each_entry(ior, &outp->disp->iors, head) {
if (!ior->identity && !!ior->func->hda.hpd == hda &&
!ior->asy.outp && ior->type == type &&
(ior->func->route.set || ior->id == __ffs(outp->info.or)))
......@@ -168,7 +168,7 @@ nvkm_outp_acquire(struct nvkm_outp *outp, u8 user, bool hda)
/* First preference is to reuse the OR that is currently armed
* on HW, if any, in order to prevent unnecessary switching.
*/
list_for_each_entry(ior, &outp->disp->ior, head) {
list_for_each_entry(ior, &outp->disp->iors, head) {
if (!ior->identity && !ior->asy.outp && ior->arm.outp == outp) {
/*XXX: For various complicated reasons, we can't outright switch
* the boot-time OR on the first modeset without some fairly
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c
View file @ 92fba5d3
......@@ -64,7 +64,7 @@ g84_disp_ovly_mthd = {
int
g84_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &g84_disp_ovly_mthd,
disp, 3, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c
View file @ 92fba5d3
......@@ -88,7 +88,7 @@ gf119_disp_ovly_mthd = {
int
gf119_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_ovly_new_(&gf119_disp_dmac_func, &gf119_disp_ovly_mthd,
disp, 5, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c
View file @ 92fba5d3
......@@ -90,7 +90,7 @@ gk104_disp_ovly_mthd = {
int
gk104_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_ovly_new_(&gf119_disp_dmac_func, &gk104_disp_ovly_mthd,
disp, 5, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygp102.c
View file @ 92fba5d3
......@@ -25,7 +25,7 @@
int
gp102_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_ovly_new_(&gp102_disp_dmac_func, &gk104_disp_ovly_mthd,
disp, 5, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c
View file @ 92fba5d3
......@@ -67,7 +67,7 @@ gt200_disp_ovly_mthd = {
int
gt200_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &gt200_disp_ovly_mthd,
disp, 3, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c
View file @ 92fba5d3
......@@ -32,7 +32,7 @@
int
nv50_disp_ovly_new_(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp *disp, int chid,
struct nvkm_disp *disp, int chid,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
......@@ -48,7 +48,7 @@ nv50_disp_ovly_new_(const struct nv50_disp_chan_func *func,
nvif_ioctl(parent, "create disp overlay channel dma vers %d "
"pushbuf %016llx head %d\n",
args->v0.version, args->v0.pushbuf, args->v0.head);
if (!nvkm_head_find(&disp->base, args->v0.head))
if (!nvkm_head_find(disp, args->v0.head))
return -EINVAL;
push = args->v0.pushbuf;
head = args->v0.head;
......@@ -100,7 +100,7 @@ nv50_disp_ovly_mthd = {
int
nv50_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_ovly_new_(&nv50_disp_dmac_func, &nv50_disp_ovly_mthd,
disp, 3, oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c
View file @ 92fba5d3
......@@ -29,8 +29,8 @@
static void
gf119_disp_pioc_fini(struct nv50_disp_chan *chan)
{
struct nv50_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......@@ -48,8 +48,8 @@ gf119_disp_pioc_fini(struct nv50_disp_chan *chan)
static int
gf119_disp_pioc_init(struct nv50_disp_chan *chan)
{
struct nv50_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c
View file @ 92fba5d3
......@@ -29,8 +29,8 @@
static void
nv50_disp_pioc_fini(struct nv50_disp_chan *chan)
{
struct nv50_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......@@ -48,8 +48,8 @@ nv50_disp_pioc_fini(struct nv50_disp_chan *chan)
static int
nv50_disp_pioc_init(struct nv50_disp_chan *chan)
{
struct nv50_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_disp *disp = chan->disp;
struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = subdev->device;
int ctrl = chan->chid.ctrl;
int user = chan->chid.user;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h
View file @ 92fba5d3
......@@ -2,8 +2,10 @@
#ifndef __NVKM_DISP_PRIV_H__
#define __NVKM_DISP_PRIV_H__
#include <engine/disp.h>
#include "outp.h"
struct nv50_disp;
#include <core/enum.h>
struct nvkm_head;
struct nvkm_outp;
struct dcb_output;
int nvkm_disp_ctor(const struct nvkm_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_disp *);
......@@ -17,16 +19,11 @@ struct nvkm_disp_func {
int (*init)(struct nvkm_disp *);
void (*fini)(struct nvkm_disp *);
void (*intr)(struct nvkm_disp *);
void (*intr_error)(struct nvkm_disp *, int chid);
const struct nvkm_disp_oclass *root;
int (*init_)(struct nv50_disp *);
void (*fini_)(struct nv50_disp *);
void (*intr_)(struct nv50_disp *);
void (*intr_error)(struct nv50_disp *, int chid);
void (*super)(struct work_struct *);
const struct nvkm_event_func *uevent;
void (*super)(struct work_struct *);
struct {
int (*cnt)(struct nvkm_disp *, unsigned long *mask);
......@@ -34,6 +31,8 @@ struct nvkm_disp_func {
} wndw, head, dac, sor, pior;
u16 ramht_size;
const struct nvkm_disp_oclass *root;
};
int nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
......@@ -46,6 +45,47 @@ int nv50_disp_init_(struct nvkm_disp *);
void nv50_disp_fini_(struct nvkm_disp *);
void nv50_disp_intr_(struct nvkm_disp *);
void nv50_disp_super_1(struct nvkm_disp *);
void nv50_disp_super_1_0(struct nvkm_disp *, struct nvkm_head *);
void nv50_disp_super_2_0(struct nvkm_disp *, struct nvkm_head *);
void nv50_disp_super_2_1(struct nvkm_disp *, struct nvkm_head *);
void nv50_disp_super_2_2(struct nvkm_disp *, struct nvkm_head *);
void nv50_disp_super_3_0(struct nvkm_disp *, struct nvkm_head *);
int nv50_disp_new_(const struct nvkm_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_disp **);
int nv50_disp_init(struct nvkm_disp *);
void nv50_disp_fini(struct nvkm_disp *);
void nv50_disp_intr(struct nvkm_disp *);
void nv50_disp_super(struct work_struct *);
extern const struct nvkm_enum nv50_disp_intr_error_type[];
int gf119_disp_init(struct nvkm_disp *);
void gf119_disp_fini(struct nvkm_disp *);
void gf119_disp_intr(struct nvkm_disp *);
void gf119_disp_super(struct work_struct *);
void gf119_disp_intr_error(struct nvkm_disp *, int);
void gv100_disp_fini(struct nvkm_disp *);
void gv100_disp_intr(struct nvkm_disp *);
void gv100_disp_super(struct work_struct *);
int gv100_disp_wndw_cnt(struct nvkm_disp *, unsigned long *);
int tu102_disp_init(struct nvkm_disp *);
void nv50_disp_dptmds_war_2(struct nvkm_disp *, struct dcb_output *);
void nv50_disp_dptmds_war_3(struct nvkm_disp *, struct dcb_output *);
void nv50_disp_update_sppll1(struct nvkm_disp *);
extern const struct nvkm_event_func nv50_disp_chan_uevent;
int nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *);
void nv50_disp_chan_uevent_send(struct nvkm_disp *, int);
extern const struct nvkm_event_func gf119_disp_chan_uevent;
extern const struct nvkm_event_func gv100_disp_chan_uevent;
struct nvkm_disp_oclass {
int (*ctor)(struct nvkm_disp *, const struct nvkm_oclass *,
void *data, u32 size, struct nvkm_object **);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
View file @ 92fba5d3
......@@ -25,6 +25,7 @@
#include "channv50.h"
#include "head.h"
#include "ior.h"
#include "outp.h"
#include <core/client.h>
......@@ -40,7 +41,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
struct nv50_disp_mthd_v1 v1;
} *args = data;
struct nv50_disp_root *root = nv50_disp_root(object);
struct nv50_disp *disp = root->disp;
struct nvkm_disp *disp = root->disp;
struct nvkm_outp *temp, *outp = NULL;
struct nvkm_head *head;
u16 type, mask = 0;
......@@ -68,11 +69,11 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
} else
return ret;
if (!(head = nvkm_head_find(&disp->base, hidx)))
if (!(head = nvkm_head_find(disp, hidx)))
return -ENXIO;
if (mask) {
list_for_each_entry(temp, &disp->base.outp, head) {
list_for_each_entry(temp, &disp->outps, head) {
if ((temp->info.hasht == type) &&
(temp->info.hashm & mask) == mask) {
outp = temp;
......@@ -275,7 +276,7 @@ static int
nv50_disp_root_child_new_(const struct nvkm_oclass *oclass,
void *argv, u32 argc, struct nvkm_object **pobject)
{
struct nv50_disp *disp = nv50_disp_root(oclass->parent)->disp;
struct nvkm_disp *disp = nv50_disp_root(oclass->parent)->disp;
const struct nv50_disp_user *user = oclass->priv;
return user->ctor(oclass, argv, argc, disp, pobject);
}
......@@ -313,10 +314,9 @@ nv50_disp_root_ = {
int
nv50_disp_root_new_(const struct nv50_disp_root_func *func,
struct nvkm_disp *base, const struct nvkm_oclass *oclass,
struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
struct nv50_disp *disp = nv50_disp(base);
struct nv50_disp_root *root;
if (!(root = kzalloc(sizeof(*root), GFP_KERNEL)))
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
View file @ 92fba5d3
......@@ -3,11 +3,11 @@
#define __NV50_DISP_ROOT_H__
#define nv50_disp_root(p) container_of((p), struct nv50_disp_root, object)
#include <core/object.h>
#include "nv50.h"
#include "priv.h"
struct nv50_disp_root {
const struct nv50_disp_root_func *func;
struct nv50_disp *disp;
struct nvkm_disp *disp;
struct nvkm_object object;
};
......@@ -16,7 +16,7 @@ struct nv50_disp_root_func {
struct nv50_disp_user {
struct nvkm_sclass base;
int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
} user[];
};
......@@ -25,7 +25,7 @@ int nv50_disp_root_new_(const struct nv50_disp_root_func *, struct nvkm_disp *,
struct nvkm_object **);
int gv100_disp_caps_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
struct nvkm_disp *, struct nvkm_object **);
extern const struct nvkm_disp_oclass nv50_disp_root_oclass;
extern const struct nvkm_disp_oclass g84_disp_root_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
View file @ 92fba5d3
......@@ -155,7 +155,7 @@ g94_sor_war_update_sppll1(struct nvkm_disp *disp)
bool used = false;
u32 clksor;
list_for_each_entry(ior, &disp->ior, head) {
list_for_each_entry(ior, &disp->iors, head) {
if (ior->type != SOR)
continue;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
View file @ 92fba5d3
......@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
*/
#include "ior.h"
#include "outp.h"
void
gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
View file @ 92fba5d3
......@@ -19,7 +19,7 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "nv50.h"
#include "priv.h"
#include "head.h"
#include "ior.h"
#include "channv50.h"
......@@ -29,9 +29,9 @@
#include <subdev/timer.h>
int
tu102_disp_init(struct nv50_disp *disp)
tu102_disp_init(struct nvkm_disp *disp)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_device *device = disp->engine.subdev.device;
struct nvkm_head *head;
int i, j;
u32 tmp;
......@@ -58,7 +58,7 @@ tu102_disp_init(struct nv50_disp *disp)
}
/* Head capabilities. */
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
const int id = head->id;
/* RG. */
......@@ -119,7 +119,7 @@ tu102_disp_init(struct nv50_disp *disp)
nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */
/* HEAD_TIMING(n): VBLANK. */
list_for_each_entry(head, &disp->base.head, head) {
list_for_each_entry(head, &disp->heads, head) {
const u32 hoff = head->id * 4;
nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */
nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */
......@@ -135,19 +135,16 @@ static const struct nvkm_disp_func
tu102_disp = {
.dtor = nv50_disp_dtor_,
.oneinit = nv50_disp_oneinit_,
.init = nv50_disp_init_,
.fini = nv50_disp_fini_,
.intr = nv50_disp_intr_,
.init_ = tu102_disp_init,
.fini_ = gv100_disp_fini,
.intr_ = gv100_disp_intr,
.uevent = &gv100_disp_chan_uevent,
.init = tu102_disp_init,
.fini = gv100_disp_fini,
.intr = gv100_disp_intr,
.super = gv100_disp_super,
.root = &tu102_disp_root_oclass,
.uevent = &gv100_disp_chan_uevent,
.wndw = { .cnt = gv100_disp_wndw_cnt },
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
.sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new },
.ramht_size = 0x2000,
.root = &tu102_disp_root_oclass,
};
int
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c
View file @ 92fba5d3
......@@ -29,7 +29,7 @@
static void
gv100_disp_wimm_intr(struct nv50_disp_chan *chan, bool en)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 mask = 0x00000001 << chan->head;
const u32 data = en ? mask : 0;
nvkm_mask(device, 0x611da8, mask, data);
......@@ -46,7 +46,7 @@ gv100_disp_wimm = {
static int
gv100_disp_wimm_new_(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp *disp, int chid,
struct nvkm_disp *disp, int chid,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
......@@ -75,7 +75,7 @@ gv100_disp_wimm_new_(const struct nv50_disp_chan_func *func,
int
gv100_disp_wimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return gv100_disp_wimm_new_(&gv100_disp_wimm, NULL, disp, 33,
oclass, argv, argc, pobject);
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c
View file @ 92fba5d3
......@@ -130,7 +130,7 @@ gv100_disp_wndw_mthd = {
static void
gv100_disp_wndw_intr(struct nv50_disp_chan *chan, bool en)
{
struct nvkm_device *device = chan->disp->base.engine.subdev.device;
struct nvkm_device *device = chan->disp->engine.subdev.device;
const u32 mask = 0x00000001 << chan->head;
const u32 data = en ? mask : 0;
nvkm_mask(device, 0x611da4, mask, data);
......@@ -148,7 +148,7 @@ gv100_disp_wndw = {
static int
gv100_disp_wndw_new_(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp *disp, int chid,
struct nvkm_disp *disp, int chid,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
......@@ -177,7 +177,7 @@ gv100_disp_wndw_new_(const struct nv50_disp_chan_func *func,
int
gv100_disp_wndw_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
struct nvkm_disp *disp, struct nvkm_object **pobject)
{
return gv100_disp_wndw_new_(&gv100_disp_wndw, &gv100_disp_wndw_mthd,
disp, 1, oclass, argv, argc, pobject);
......
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