Commit 9386aae9 authored by Han Xu's avatar Han Xu Committed by Sasha Levin

mtd: fsl-quadspi: fix macro collision problems with READ/WRITE

[ Upstream commit 04850c4d ]

Change the READ/WRITE to FSL_READ/FSL_WRITE to resolve any possible
namespace collisions with READ/WRITE macros (e.g., from <linux/fs.h>).

Problems have been seen, for example, on mips:

>> drivers/mtd/spi-nor/fsl-quadspi.c:186:5: error: 'LUT_0' undeclared (first use in this function)
      ((LUT_##ins) << INSTR0_SHIFT))
        ^
>> drivers/mtd/spi-nor/fsl-quadspi.c:188:30: note: in expansion of macro 'LUT0'

On SPARC:

drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_init_lut':
drivers/mtd/spi-nor/fsl-quadspi.c:369:1: error: 'LUT_0' undeclared (first use in this function)
drivers/mtd/spi-nor/fsl-quadspi.c:418:1: error: pasting "LUT_" and "(" does not give a valid preprocessing token
drivers/mtd/spi-nor/fsl-quadspi.c:418:2: error: implicit declaration of function 'LUT_'

And surely on others.

Fixes: d26a22d0 ("mtd: fsl-quadspi: allow building for other ARCHes with COMPILE_TEST")
Reported-by: default avatarGuenter Roeck <linux@roeck-us.net>
Reported-by: default avatarkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: default avatarHan Xu <b45815@freescale.com>
[Brian: rewrote commit description]
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
parent 00da0a0a
...@@ -140,15 +140,15 @@ ...@@ -140,15 +140,15 @@
#define LUT_MODE 4 #define LUT_MODE 4
#define LUT_MODE2 5 #define LUT_MODE2 5
#define LUT_MODE4 6 #define LUT_MODE4 6
#define LUT_READ 7 #define LUT_FSL_READ 7
#define LUT_WRITE 8 #define LUT_FSL_WRITE 8
#define LUT_JMP_ON_CS 9 #define LUT_JMP_ON_CS 9
#define LUT_ADDR_DDR 10 #define LUT_ADDR_DDR 10
#define LUT_MODE_DDR 11 #define LUT_MODE_DDR 11
#define LUT_MODE2_DDR 12 #define LUT_MODE2_DDR 12
#define LUT_MODE4_DDR 13 #define LUT_MODE4_DDR 13
#define LUT_READ_DDR 14 #define LUT_FSL_READ_DDR 14
#define LUT_WRITE_DDR 15 #define LUT_FSL_WRITE_DDR 15
#define LUT_DATA_LEARN 16 #define LUT_DATA_LEARN 16
/* /*
...@@ -312,7 +312,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) ...@@ -312,7 +312,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base)); base + QUADSPI_LUT(lut_base));
writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo), writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1)); base + QUADSPI_LUT(lut_base + 1));
/* Write enable */ /* Write enable */
...@@ -333,11 +333,11 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) ...@@ -333,11 +333,11 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base)); base + QUADSPI_LUT(lut_base));
writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
/* Read Status */ /* Read Status */
lut_base = SEQID_RDSR * 4; lut_base = SEQID_RDSR * 4;
writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1), writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
base + QUADSPI_LUT(lut_base)); base + QUADSPI_LUT(lut_base));
/* Erase a sector */ /* Erase a sector */
...@@ -362,17 +362,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) ...@@ -362,17 +362,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
/* READ ID */ /* READ ID */
lut_base = SEQID_RDID * 4; lut_base = SEQID_RDID * 4;
writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8), writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8),
base + QUADSPI_LUT(lut_base)); base + QUADSPI_LUT(lut_base));
/* Write Register */ /* Write Register */
lut_base = SEQID_WRSR * 4; lut_base = SEQID_WRSR * 4;
writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2), writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2),
base + QUADSPI_LUT(lut_base)); base + QUADSPI_LUT(lut_base));
/* Read Configuration Register */ /* Read Configuration Register */
lut_base = SEQID_RDCR * 4; lut_base = SEQID_RDCR * 4;
writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1), writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1),
base + QUADSPI_LUT(lut_base)); base + QUADSPI_LUT(lut_base));
/* Write disable */ /* Write disable */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment