Commit 93982535 authored by Kristoffer Ericson's avatar Kristoffer Ericson Committed by Russell King

[ARM] 5336/1: Formatting/Whitespace cleanups in mach-sa1100

This patch fixes bad formatting found in
mach-sa1100 files.

What it does is to replace/delete things like
excessive spaces (start || endline). The code
looks the same just alot less junk.
Signed-off-by: default avatarKristoffer Ericson <Kristoffer.Ericson@gmail.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 799a0600
...@@ -68,23 +68,22 @@ struct platform_device colliescoop_device = { ...@@ -68,23 +68,22 @@ struct platform_device colliescoop_device = {
}; };
static struct scoop_pcmcia_dev collie_pcmcia_scoop[] = { static struct scoop_pcmcia_dev collie_pcmcia_scoop[] = {
{ {
.dev = &colliescoop_device.dev, .dev = &colliescoop_device.dev,
.irq = COLLIE_IRQ_GPIO_CF_IRQ, .irq = COLLIE_IRQ_GPIO_CF_IRQ,
.cd_irq = COLLIE_IRQ_GPIO_CF_CD, .cd_irq = COLLIE_IRQ_GPIO_CF_CD,
.cd_irq_str = "PCMCIA0 CD", .cd_irq_str = "PCMCIA0 CD",
}, },
}; };
static struct scoop_pcmcia_config collie_pcmcia_config = { static struct scoop_pcmcia_config collie_pcmcia_config = {
.devs = &collie_pcmcia_scoop[0], .devs = &collie_pcmcia_scoop[0],
.num_devs = 1, .num_devs = 1,
}; };
static struct mcp_plat_data collie_mcp_data = { static struct mcp_plat_data collie_mcp_data = {
.mccr0 = MCCR0_ADM | MCCR0_ExtClk, .mccr0 = MCCR0_ADM | MCCR0_ExtClk,
.sclk_rate = 9216000, .sclk_rate = 9216000,
}; };
#ifdef CONFIG_SHARP_LOCOMO #ifdef CONFIG_SHARP_LOCOMO
...@@ -95,14 +94,14 @@ struct platform_device collie_locomo_device; ...@@ -95,14 +94,14 @@ struct platform_device collie_locomo_device;
static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl) static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl)
{ {
if (mctrl & TIOCM_RTS) if (mctrl & TIOCM_RTS)
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0); locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0);
else else
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1); locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1);
if (mctrl & TIOCM_DTR) if (mctrl & TIOCM_DTR)
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0); locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0);
else else
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1); locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1);
} }
......
...@@ -263,24 +263,24 @@ static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev) ...@@ -263,24 +263,24 @@ static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev)
} }
static struct ucb1x00_driver collie_pm_ucb_driver = { static struct ucb1x00_driver collie_pm_ucb_driver = {
.add = collie_pm_ucb_add, .add = collie_pm_ucb_add,
}; };
static struct platform_device *collie_pm_device; static struct platform_device *collie_pm_device;
static int __init collie_pm_init(void) static int __init collie_pm_init(void)
{ {
int ret; int ret;
collie_pm_device = platform_device_alloc("sharpsl-pm", -1); collie_pm_device = platform_device_alloc("sharpsl-pm", -1);
if (!collie_pm_device) if (!collie_pm_device)
return -ENOMEM; return -ENOMEM;
collie_pm_device->dev.platform_data = &collie_pm_machinfo; collie_pm_device->dev.platform_data = &collie_pm_machinfo;
ret = platform_device_add(collie_pm_device); ret = platform_device_add(collie_pm_device);
if (ret) if (ret)
platform_device_put(collie_pm_device); platform_device_put(collie_pm_device);
if (!ret) if (!ret)
ret = ucb1x00_register_driver(&collie_pm_ucb_driver); ret = ucb1x00_register_driver(&collie_pm_ucb_driver);
...@@ -291,7 +291,7 @@ static int __init collie_pm_init(void) ...@@ -291,7 +291,7 @@ static int __init collie_pm_init(void)
static void __exit collie_pm_exit(void) static void __exit collie_pm_exit(void)
{ {
ucb1x00_unregister_driver(&collie_pm_ucb_driver); ucb1x00_unregister_driver(&collie_pm_ucb_driver);
platform_device_unregister(collie_pm_device); platform_device_unregister(collie_pm_device);
} }
module_init(collie_pm_init); module_init(collie_pm_init);
......
...@@ -3,17 +3,17 @@ ...@@ -3,17 +3,17 @@
* *
* Copyright (C) 2000 2001, The Delft University of Technology * Copyright (C) 2000 2001, The Delft University of Technology
* *
* Authors: * Authors:
* - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
* - Erik Mouw (J.A.K.Mouw@its.tudelft.nl): * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
* - major rewrite for linux-2.3.99 * - major rewrite for linux-2.3.99
* - rewritten for the more generic power management scheme in * - rewritten for the more generic power management scheme in
* linux-2.4.5-rmk1 * linux-2.4.5-rmk1
* *
* This software has been developed while working on the LART * This software has been developed while working on the LART
* computing board (http://www.lartmaker.nl/), which is * computing board (http://www.lartmaker.nl/), which is
* sponsored by the Mobile Multi-media Communications * sponsored by the Mobile Multi-media Communications
* (http://www.mmc.tudelft.nl/) and Ubiquitous Communications * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications
* (http://www.ubicom.tudelft.nl/) projects. * (http://www.ubicom.tudelft.nl/) projects.
* *
* The authors can be reached at: * The authors can be reached at:
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
...@@ -44,7 +44,7 @@ ...@@ -44,7 +44,7 @@
* *
* Theory of operations * Theory of operations
* ==================== * ====================
* *
* Clock scaling can be used to lower the power consumption of the CPU * Clock scaling can be used to lower the power consumption of the CPU
* core. This will give you a somewhat longer running time. * core. This will give you a somewhat longer running time.
* *
...@@ -58,11 +58,11 @@ ...@@ -58,11 +58,11 @@
* MDCNFG 0xA0000000 DRAM config * MDCNFG 0xA0000000 DRAM config
* MDCAS0 0xA0000004 Access waveform * MDCAS0 0xA0000004 Access waveform
* MDCAS1 0xA0000008 Access waveform * MDCAS1 0xA0000008 Access waveform
* MDCAS2 0xA000000C Access waveform * MDCAS2 0xA000000C Access waveform
* *
* Care must be taken to change the DRAM parameters the correct way, * Care must be taken to change the DRAM parameters the correct way,
* because otherwise the DRAM becomes unusable and the kernel will * because otherwise the DRAM becomes unusable and the kernel will
* crash. * crash.
* *
* The simple solution to avoid a kernel crash is to put the actual * The simple solution to avoid a kernel crash is to put the actual
* clock change in ROM and jump to that code from the kernel. The main * clock change in ROM and jump to that code from the kernel. The main
...@@ -75,7 +75,7 @@ ...@@ -75,7 +75,7 @@
* as long as all re-configuration steps yield a valid DRAM * as long as all re-configuration steps yield a valid DRAM
* configuration. The advantages are clear: it will run on all SA-1100 * configuration. The advantages are clear: it will run on all SA-1100
* platforms, and the code is very simple. * platforms, and the code is very simple.
* *
* If you really want to understand what is going on in * If you really want to understand what is going on in
* sa1100_update_dram_timings(), you'll have to read sections 8.2, * sa1100_update_dram_timings(), you'll have to read sections 8.2,
* 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor
...@@ -97,7 +97,7 @@ ...@@ -97,7 +97,7 @@
typedef struct { typedef struct {
int speed; int speed;
u32 mdcnfg; u32 mdcnfg;
u32 mdcas0; u32 mdcas0;
u32 mdcas1; u32 mdcas1;
u32 mdcas2; u32 mdcas2;
} sa1100_dram_regs_t; } sa1100_dram_regs_t;
...@@ -147,7 +147,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed) ...@@ -147,7 +147,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed)
/* No risk, no fun: run with interrupts on! */ /* No risk, no fun: run with interrupts on! */
if (new_speed > current_speed) { if (new_speed > current_speed) {
/* We're going FASTER, so first relax the memory /* We're going FASTER, so first relax the memory
* timings before changing the core frequency * timings before changing the core frequency
*/ */
/* Half the memory access clock */ /* Half the memory access clock */
......
...@@ -81,14 +81,14 @@ static struct sdram_params sdram_tbl[] __initdata = { ...@@ -81,14 +81,14 @@ static struct sdram_params sdram_tbl[] __initdata = {
.twr = 9, .twr = 9,
.refresh = 64000, .refresh = 64000,
.cas_latency = 3, .cas_latency = 3,
}, { /* Samsung K4S281632B-1H */ }, { /* Samsung K4S281632B-1H */
.name = "K4S281632B-1H", .name = "K4S281632B-1H",
.rows = 12, .rows = 12,
.tck = 10, .tck = 10,
.trp = 20, .trp = 20,
.twr = 10, .twr = 10,
.refresh = 64000, .refresh = 64000,
.cas_latency = 3, .cas_latency = 3,
}, { /* Samsung KM416S4030CT */ }, { /* Samsung KM416S4030CT */
.name = "KM416S4030CT", .name = "KM416S4030CT",
.rows = 13, .rows = 13,
...@@ -220,7 +220,7 @@ sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram) ...@@ -220,7 +220,7 @@ sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
} }
/* /*
* Ok, set the CPU frequency. * Ok, set the CPU frequency.
*/ */
static int sa1110_target(struct cpufreq_policy *policy, static int sa1110_target(struct cpufreq_policy *policy,
unsigned int target_freq, unsigned int target_freq,
......
...@@ -113,10 +113,10 @@ int sa1100_request_dma (dma_device_t device, const char *device_id, ...@@ -113,10 +113,10 @@ int sa1100_request_dma (dma_device_t device, const char *device_id,
} }
} }
if (!err) { if (!err) {
if (dma) if (dma)
dma->device = device; dma->device = device;
else else
err = -ENOSR; err = -ENOSR;
} }
spin_unlock(&dma_list_lock); spin_unlock(&dma_list_lock);
if (err) if (err)
......
...@@ -32,14 +32,14 @@ typedef int __bitwise pm_request_t; ...@@ -32,14 +32,14 @@ typedef int __bitwise pm_request_t;
#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800())
/* Physical memory regions corresponding to chip selects */ /* Physical memory regions corresponding to chip selects */
#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000)
#define H3600_BANK_2_PHYS SA1100_CS2_PHYS #define H3600_BANK_2_PHYS SA1100_CS2_PHYS
#define H3600_BANK_4_PHYS SA1100_CS4_PHYS #define H3600_BANK_4_PHYS SA1100_CS4_PHYS
/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ /* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
#define H3600_EGPIO_VIRT 0xf0000000 #define H3600_EGPIO_VIRT 0xf0000000
#define H3600_BANK_2_VIRT 0xf1000000 #define H3600_BANK_2_VIRT 0xf1000000
#define H3600_BANK_4_VIRT 0xf3800000 #define H3600_BANK_4_VIRT 0xf3800000
/* /*
Machine-independent GPIO definitions Machine-independent GPIO definitions
......
...@@ -122,12 +122,12 @@ static void __init pleb_map_io(void) ...@@ -122,12 +122,12 @@ static void __init pleb_map_io(void)
sa1100_map_io(); sa1100_map_io();
sa1100_register_uart(0, 3); sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1); sa1100_register_uart(1, 1);
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD); GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD; GPDR |= GPIO_UART_TXD;
GPDR &= ~GPIO_UART_RXD; GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR; PPAR |= PPAR_UPR;
/* /*
* Fix expansion memory timing for network card * Fix expansion memory timing for network card
......
...@@ -33,7 +33,7 @@ static struct mtd_partition shannon_partitions[] = { ...@@ -33,7 +33,7 @@ static struct mtd_partition shannon_partitions[] = {
.offset = MTDPART_OFS_APPEND, .offset = MTDPART_OFS_APPEND,
.size = 0xe0000 .size = 0xe0000
}, },
{ {
.name = "initrd", .name = "initrd",
.offset = MTDPART_OFS_APPEND, .offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL .size = MTDPART_SIZ_FULL
......
...@@ -100,36 +100,36 @@ ENTRY(sa1100_cpu_suspend) ...@@ -100,36 +100,36 @@ ENTRY(sa1100_cpu_suspend)
ldr r1, =MSC1 ldr r1, =MSC1
ldr r2, =MSC2 ldr r2, =MSC2
ldr r3, [r0] ldr r3, [r0]
bic r3, r3, #FMsk(MSC_RT) bic r3, r3, #FMsk(MSC_RT)
bic r3, r3, #FMsk(MSC_RT)<<16 bic r3, r3, #FMsk(MSC_RT)<<16
ldr r4, [r1] ldr r4, [r1]
bic r4, r4, #FMsk(MSC_RT) bic r4, r4, #FMsk(MSC_RT)
bic r4, r4, #FMsk(MSC_RT)<<16 bic r4, r4, #FMsk(MSC_RT)<<16
ldr r5, [r2] ldr r5, [r2]
bic r5, r5, #FMsk(MSC_RT) bic r5, r5, #FMsk(MSC_RT)
bic r5, r5, #FMsk(MSC_RT)<<16 bic r5, r5, #FMsk(MSC_RT)<<16
ldr r6, =MDREFR ldr r6, =MDREFR
ldr r7, [r6] ldr r7, [r6]
bic r7, r7, #0x0000FF00 bic r7, r7, #0x0000FF00
bic r7, r7, #0x000000F0 bic r7, r7, #0x000000F0
orr r8, r7, #MDREFR_SLFRSH orr r8, r7, #MDREFR_SLFRSH
ldr r9, =MDCNFG ldr r9, =MDCNFG
ldr r10, [r9] ldr r10, [r9]
bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1) bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3) bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
bic r11, r8, #MDREFR_SLFRSH bic r11, r8, #MDREFR_SLFRSH
bic r11, r11, #MDREFR_E1PIN bic r11, r11, #MDREFR_E1PIN
ldr r12, =PMCR ldr r12, =PMCR
mov r13, #PMCR_SF mov r13, #PMCR_SF
b sa1110_sdram_controller_fix b sa1110_sdram_controller_fix
...@@ -188,10 +188,10 @@ ENTRY(sa1100_cpu_resume) ...@@ -188,10 +188,10 @@ ENTRY(sa1100_cpu_resume)
mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
mcr p15, 0, r1, c9, c0, 0 @ invalidate RB mcr p15, 0, r1, c9, c0, 0 @ invalidate RB
mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
mcr p15, 0, r4, c3, c0, 0 @ domain ID mcr p15, 0, r4, c3, c0, 0 @ domain ID
mcr p15, 0, r5, c2, c0, 0 @ translation table base addr mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
mcr p15, 0, r6, c13, c0, 0 @ PID mcr p15, 0, r6, c13, c0, 0 @ PID
b resume_turn_on_mmu @ cache align execution b resume_turn_on_mmu @ cache align execution
...@@ -209,7 +209,7 @@ sleep_save_sp: ...@@ -209,7 +209,7 @@ sleep_save_sp:
.text .text
resume_after_mmu: resume_after_mmu:
mcr p15, 0, r1, c15, c1, 2 @ enable clock switching mcr p15, 0, r1, c15, c1, 2 @ enable clock switching
ldmfd sp!, {r4 - r12, pc} @ return to caller ldmfd sp!, {r4 - r12, pc} @ return to caller
...@@ -2,8 +2,8 @@ ...@@ -2,8 +2,8 @@
* linux/arch/arm/mach-sa1100/time.c * linux/arch/arm/mach-sa1100/time.c
* *
* Copyright (C) 1998 Deborah Wallach. * Copyright (C) 1998 Deborah Wallach.
* Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com> * Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com>
* *
* 2000/03/29 (C) Nicolas Pitre <nico@cam.org> * 2000/03/29 (C) Nicolas Pitre <nico@cam.org>
* Rewritten: big cleanup, much simpler, better HZ accuracy. * Rewritten: big cleanup, much simpler, better HZ accuracy.
* *
......
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