Commit 93f7d6f3 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by Kalle Valo

ath9k: Check allowed PCIE powersave configuration

When assigning the initvals for PCIE sleep/awake
registers, check the configuration that has been
assigned to pll_pwrsave during initialization. Also,
display a warning if we don't have valid arrays.
Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 656cd75c
...@@ -231,10 +231,20 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -231,10 +231,20 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9462_2p1_modes_fast_clock); ar9462_2p1_modes_fast_clock);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484, INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9462_2p1_baseband_core_txfir_coeff_japan_2484); ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9462_2p1_pciephy_clkreq_disable_L1); /* Awake -> Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
ar9462_2p1_pciephy_clkreq_disable_L1); (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9462_2p1_pciephy_clkreq_disable_L1);
}
/* Sleep -> Awake Setting */
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9462_2p1_pciephy_clkreq_disable_L1);
}
} else if (AR_SREV_9462_20(ah)) { } else if (AR_SREV_9462_20(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core); INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
...@@ -262,11 +272,18 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -262,11 +272,18 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9462_2p0_common_rx_gain); ar9462_2p0_common_rx_gain);
/* Awake -> Sleep Setting */ /* Awake -> Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdes, if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
ar9462_2p0_pciephy_clkreq_disable_L1); (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9462_2p0_pciephy_clkreq_disable_L1);
}
/* Sleep -> Awake Setting */ /* Sleep -> Awake Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
ar9462_2p0_pciephy_clkreq_disable_L1); (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9462_2p0_pciephy_clkreq_disable_L1);
}
/* Fast clock modal settings */ /* Fast clock modal settings */
INIT_INI_ARRAY(&ah->iniModesFastClock, INIT_INI_ARRAY(&ah->iniModesFastClock,
...@@ -456,10 +473,19 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -456,10 +473,19 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9565_1p1_Modes_lowest_ob_db_tx_gain_table); ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
INIT_INI_ARRAY(&ah->iniPcieSerdes, /* Awake -> Sleep Setting */
ar9565_1p1_pciephy_clkreq_disable_L1); if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
ar9565_1p1_pciephy_clkreq_disable_L1); INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9565_1p1_pciephy_clkreq_disable_L1);
}
/* Sleep -> Awake Setting */
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9565_1p1_pciephy_clkreq_disable_L1);
}
INIT_INI_ARRAY(&ah->iniModesFastClock, INIT_INI_ARRAY(&ah->iniModesFastClock,
ar9565_1p1_modes_fast_clock); ar9565_1p1_modes_fast_clock);
...@@ -491,10 +517,19 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -491,10 +517,19 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9565_1p0_Modes_lowest_ob_db_tx_gain_table); ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
INIT_INI_ARRAY(&ah->iniPcieSerdes, /* Awake -> Sleep Setting */
ar9565_1p0_pciephy_clkreq_disable_L1); if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
ar9565_1p0_pciephy_clkreq_disable_L1); INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9565_1p0_pciephy_clkreq_disable_L1);
}
/* Sleep -> Awake Setting */
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9565_1p0_pciephy_clkreq_disable_L1);
}
INIT_INI_ARRAY(&ah->iniModesFastClock, INIT_INI_ARRAY(&ah->iniModesFastClock,
ar9565_1p0_modes_fast_clock); ar9565_1p0_modes_fast_clock);
...@@ -1130,6 +1165,12 @@ void ar9003_hw_attach_ops(struct ath_hw *ah) ...@@ -1130,6 +1165,12 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
struct ath_hw_ops *ops = ath9k_hw_ops(ah); struct ath_hw_ops *ops = ath9k_hw_ops(ah);
ar9003_hw_init_mode_regs(ah); ar9003_hw_init_mode_regs(ah);
if (AR_SREV_9003_PCOEM(ah)) {
WARN_ON(!ah->iniPcieSerdes.ia_array);
WARN_ON(!ah->iniPcieSerdesLowPower.ia_array);
}
priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
priv_ops->init_hang_checks = ar9003_hw_init_hang_checks; priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang; priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
......
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