Commit 982ac2a7 authored by Rob Herring's avatar Rob Herring Committed by Robert Richter

ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsi

The DDR controller is slightly different in ECX-2000 and ECX-1000, so we
need to have different nodes for each platform.
Signed-off-by: default avatarRob Herring <rob.herring@calxeda.com>
[Device Tree documentation updated.]
Signed-off-by: default avatarRobert Richter <rric@kernel.org>
parent a72b8859
Calxeda DDR memory controller
Properties:
- compatible : Should be "calxeda,hb-ddr-ctrl"
- compatible : Should be:
- "calxeda,hb-ddr-ctrl" for ECX-1000
- "calxeda,ecx-2000-ddr-ctrl" for ECX-2000
- reg : Address and size for DDR controller registers.
- interrupts : Interrupt for DDR controller.
......
......@@ -85,6 +85,12 @@ timer {
<1 10 0xf08>;
};
memory-controller@fff00000 {
compatible = "calxeda,ecx-2000-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
......
......@@ -45,12 +45,6 @@ sdhci@ffe0e000 {
status = "disabled";
};
memory-controller@fff00000 {
compatible = "calxeda,hb-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};
ipc@fff20000 {
compatible = "arm,pl320", "arm,primecell";
reg = <0xfff20000 0x1000>;
......
......@@ -86,6 +86,12 @@ memory {
soc {
ranges = <0x00000000 0x00000000 0xffffffff>;
memory-controller@fff00000 {
compatible = "calxeda,hb-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};
timer@fff10600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfff10600 0x20>;
......
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