Commit 98f80899 authored by Kalle Valo's avatar Kalle Valo

Merge tag 'mt76-for-kvalo-2020-07-21' of https://github.com/nbd168/wireless

mt76 patches for 5.9

* locking fixes
* tx queue mapping fixes for 7615/7915
* ARP filter offload for 7663
* runtime power management for 7663
* testmode support for mfg calibration
* memory leak fixes
* support for more channels

# gpg: Signature made Tue 21 Jul 2020 08:01:28 PM EEST using DSA key ID 02A76EF5
# gpg: Good signature from "Felix Fietkau <nbd@nbd.name>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 75D1 1A7D 91A7 710F 4900  42EF D77D 141D 02A7 6EF5
parents dfecd3e0 5648d1c9
......@@ -12,6 +12,10 @@ config MT76_USB
tristate
depends on MT76_CORE
config MT76_SDIO
tristate
depends on MT76_CORE
config MT76x02_LIB
tristate
select MT76_CORE
......
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MT76_CORE) += mt76.o
obj-$(CONFIG_MT76_USB) += mt76-usb.o
obj-$(CONFIG_MT76_SDIO) += mt76-sdio.o
obj-$(CONFIG_MT76x02_LIB) += mt76x02-lib.o
obj-$(CONFIG_MT76x02_USB) += mt76x02-usb.o
......@@ -9,8 +10,10 @@ mt76-y := \
tx.o agg-rx.o mcu.o
mt76-$(CONFIG_PCI) += pci.o
mt76-$(CONFIG_NL80211_TESTMODE) += testmode.o
mt76-usb-y := usb.o usb_trace.o
mt76-sdio-y := sdio.o
CFLAGS_trace.o := -I$(src)
CFLAGS_usb_trace.o := -I$(src)
......
......@@ -9,7 +9,7 @@ mt76_reg_set(void *data, u64 val)
{
struct mt76_dev *dev = data;
dev->bus->wr(dev, dev->debugfs_reg, val);
__mt76_wr(dev, dev->debugfs_reg, val);
return 0;
}
......@@ -18,7 +18,7 @@ mt76_reg_get(void *data, u64 *val)
{
struct mt76_dev *dev = data;
*val = dev->bus->rr(dev, dev->debugfs_reg);
*val = __mt76_rr(dev, dev->debugfs_reg);
return 0;
}
......@@ -54,9 +54,6 @@ static int mt76_rx_queues_read(struct seq_file *s, void *data)
mt76_for_each_q_rx(dev, i) {
struct mt76_queue *q = &dev->q_rx[i];
if (!q->ndesc)
continue;
queued = mt76_is_usb(dev) ? q->ndesc - q->queued : q->queued;
seq_printf(s, "%d: queued=%d head=%d tail=%d\n",
i, queued, q->head, q->tail);
......
......@@ -370,6 +370,12 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, enum mt76_txq_id qid,
tx_info.buf[n].len, DMA_TO_DEVICE);
free:
#ifdef CONFIG_NL80211_TESTMODE
/* fix tx_done accounting on queue overflow */
if (tx_info.skb == dev->test.tx_skb)
dev->test.tx_done--;
#endif
e.skb = tx_info.skb;
e.txwi = t;
dev->drv->tx_complete_skb(dev, qid, &e);
......
......@@ -74,6 +74,11 @@ mt76_get_of_eeprom(struct mt76_dev *dev, int len)
&data[i]);
}
#ifdef CONFIG_NL80211_TESTMODE
dev->test.mtd_name = devm_kstrdup(dev->dev, part, GFP_KERNEL);
dev->test.mtd_offset = offset;
#endif
out_put_node:
of_node_put(np);
return ret;
......
......@@ -58,12 +58,15 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
CHAN5G(132, 5660),
CHAN5G(136, 5680),
CHAN5G(140, 5700),
CHAN5G(144, 5720),
CHAN5G(149, 5745),
CHAN5G(153, 5765),
CHAN5G(157, 5785),
CHAN5G(161, 5805),
CHAN5G(165, 5825),
CHAN5G(169, 5845),
CHAN5G(173, 5865),
};
static const struct ieee80211_tpt_blink mt76_tpt_blink[] = {
......@@ -279,7 +282,8 @@ mt76_phy_init(struct mt76_dev *dev, struct ieee80211_hw *hw)
wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH |
WIPHY_FLAG_SUPPORTS_TDLS;
WIPHY_FLAG_SUPPORTS_TDLS |
WIPHY_FLAG_AP_UAPSD;
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS);
......@@ -289,6 +293,7 @@ mt76_phy_init(struct mt76_dev *dev, struct ieee80211_hw *hw)
wiphy->available_antennas_rx = dev->phy.antenna_mask;
hw->txq_data_size = sizeof(struct mt76_txq);
hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
if (!hw->max_tx_fragments)
hw->max_tx_fragments = 16;
......@@ -300,7 +305,11 @@ mt76_phy_init(struct mt76_dev *dev, struct ieee80211_hw *hw)
ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
ieee80211_hw_set(hw, TX_AMSDU);
ieee80211_hw_set(hw, TX_FRAG_LIST);
/* TODO: avoid linearization for SDIO */
if (!mt76_is_sdio(dev))
ieee80211_hw_set(hw, TX_FRAG_LIST);
ieee80211_hw_set(hw, MFP_CAPABLE);
ieee80211_hw_set(hw, AP_LINK_PS);
ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
......@@ -432,6 +441,12 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
tasklet_init(&dev->tx_tasklet, mt76_tx_tasklet, (unsigned long)dev);
dev->wq = alloc_ordered_workqueue("mt76", 0);
if (!dev->wq) {
ieee80211_free_hw(hw);
return NULL;
}
return dev;
}
EXPORT_SYMBOL_GPL(mt76_alloc_device);
......@@ -485,7 +500,12 @@ EXPORT_SYMBOL_GPL(mt76_unregister_device);
void mt76_free_device(struct mt76_dev *dev)
{
mt76_tx_free(dev);
if (dev->wq) {
destroy_workqueue(dev->wq);
dev->wq = NULL;
}
if (mt76_is_mmio(dev))
mt76_tx_free(dev);
ieee80211_free_hw(dev->hw);
}
EXPORT_SYMBOL_GPL(mt76_free_device);
......@@ -500,6 +520,13 @@ void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb)
return;
}
#ifdef CONFIG_NL80211_TESTMODE
if (dev->test.state == MT76_TM_STATE_RX_FRAMES) {
dev->test.rx_stats.packets[q]++;
if (status->flag & RX_FLAG_FAILED_FCS_CRC)
dev->test.rx_stats.fcs_error[q]++;
}
#endif
__skb_queue_tail(&dev->rx_skb[q], skb);
}
EXPORT_SYMBOL_GPL(mt76_rx);
......@@ -537,8 +564,7 @@ mt76_channel_state(struct mt76_phy *phy, struct ieee80211_channel *c)
return &msband->chan[idx];
}
static void
mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time)
void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time)
{
struct mt76_channel_state *state = phy->chan_state;
......@@ -546,6 +572,7 @@ mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time)
phy->survey_time));
phy->survey_time = time;
}
EXPORT_SYMBOL_GPL(mt76_update_survey_active_time);
void mt76_update_survey(struct mt76_dev *dev)
{
......
......@@ -15,6 +15,7 @@
#include <linux/average.h>
#include <net/mac80211.h>
#include "util.h"
#include "testmode.h"
#define MT_TX_RING_SIZE 256
#define MT_MCU_RING_SIZE 32
......@@ -33,6 +34,7 @@ struct mt76_reg_pair {
enum mt76_bus_type {
MT76_BUS_MMIO,
MT76_BUS_USB,
MT76_BUS_SDIO,
};
struct mt76_bus_ops {
......@@ -52,6 +54,7 @@ struct mt76_bus_ops {
#define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
#define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
#define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)
enum mt76_txq_id {
MT_TXQ_VO = IEEE80211_AC_VO,
......@@ -94,6 +97,7 @@ struct mt76_queue_entry {
union {
struct mt76_txwi_cache *txwi;
struct urb *urb;
int buf_sz;
};
enum mt76_txq_id qid;
bool skip_buf0:1;
......@@ -146,6 +150,8 @@ struct mt76_mcu_ops {
int len, bool wait_resp);
int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,
int cmd, bool wait_resp);
u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);
void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);
int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
const struct mt76_reg_pair *rp, int len);
int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
......@@ -290,6 +296,7 @@ enum {
MT76_STATE_POWER_OFF,
MT76_STATE_SUSPEND,
MT76_STATE_ROC,
MT76_STATE_PM,
};
struct mt76_hw_cap {
......@@ -301,6 +308,7 @@ struct mt76_hw_cap {
#define MT_DRV_TX_ALIGNED4_SKBS BIT(1)
#define MT_DRV_SW_RX_AIRTIME BIT(2)
#define MT_DRV_RX_DMA_HDR BIT(3)
#define MT_DRV_HW_MGMT_TXQ BIT(4)
struct mt76_driver_ops {
u32 drv_flags;
......@@ -421,7 +429,6 @@ struct mt76_usb {
u16 data_len;
struct tasklet_struct rx_tasklet;
struct workqueue_struct *wq;
struct work_struct stat_work;
u8 out_ep[__MT_EP_OUT_MAX];
......@@ -438,6 +445,24 @@ struct mt76_usb {
} mcu;
};
struct mt76_sdio {
struct task_struct *tx_kthread;
struct task_struct *kthread;
struct work_struct stat_work;
unsigned long state;
struct sdio_func *func;
struct {
struct mutex lock;
int pse_data_quota;
int ple_data_quota;
int pse_mcu_quota;
int deficit;
} sched;
};
struct mt76_mmio {
void __iomem *regs;
spinlock_t irq_lock;
......@@ -474,6 +499,47 @@ struct mt76_rx_status {
s8 chain_signal[IEEE80211_MAX_CHAINS];
};
struct mt76_testmode_ops {
int (*set_state)(struct mt76_dev *dev, enum mt76_testmode_state state);
int (*set_params)(struct mt76_dev *dev, struct nlattr **tb,
enum mt76_testmode_state new_state);
int (*dump_stats)(struct mt76_dev *dev, struct sk_buff *msg);
};
struct mt76_testmode_data {
enum mt76_testmode_state state;
u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
struct sk_buff *tx_skb;
u32 tx_count;
u16 tx_msdu_len;
u8 tx_rate_mode;
u8 tx_rate_idx;
u8 tx_rate_nss;
u8 tx_rate_sgi;
u8 tx_rate_ldpc;
u8 tx_antenna_mask;
u32 freq_offset;
u8 tx_power[4];
u8 tx_power_control;
const char *mtd_name;
u32 mtd_offset;
u32 tx_pending;
u32 tx_queued;
u32 tx_done;
struct {
u64 packets[__MT_RXQ_MAX];
u64 fcs_error[__MT_RXQ_MAX];
} rx_stats;
};
struct mt76_phy {
struct ieee80211_hw *hw;
struct mt76_dev *dev;
......@@ -490,6 +556,8 @@ struct mt76_phy {
struct mt76_sband sband_2g;
struct mt76_sband sband_5g;
u32 vif_mask;
int txpower_cur;
u8 antenna_mask;
};
......@@ -571,9 +639,17 @@ struct mt76_dev {
u32 rxfilter;
#ifdef CONFIG_NL80211_TESTMODE
const struct mt76_testmode_ops *test_ops;
struct mt76_testmode_data test;
#endif
struct workqueue_struct *wq;
union {
struct mt76_mmio mmio;
struct mt76_usb usb;
struct mt76_sdio sdio;
};
};
......@@ -804,6 +880,15 @@ static inline u8 mt76_tx_power_nss_delta(u8 nss)
return nss_delta[nss - 1];
}
static inline bool mt76_testmode_enabled(struct mt76_dev *dev)
{
#ifdef CONFIG_NL80211_TESTMODE
return dev->test.state != MT76_TM_STATE_OFF;
#else
return false;
#endif
}
void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,
struct mt76_wcid *wcid, struct sk_buff *skb);
......@@ -823,6 +908,7 @@ void mt76_release_buffered_frames(struct ieee80211_hw *hw,
bool mt76_has_tx_pending(struct mt76_phy *phy);
void mt76_set_channel(struct mt76_phy *phy);
void mt76_update_survey(struct mt76_dev *dev);
void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);
int mt76_get_survey(struct ieee80211_hw *hw, int idx,
struct survey_info *survey);
void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);
......@@ -876,6 +962,24 @@ void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
const u8 *mac);
void mt76_sw_scan_complete(struct ieee80211_hw *hw,
struct ieee80211_vif *vif);
int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
void *data, int len);
int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
struct netlink_callback *cb, void *data, int len);
int mt76_testmode_set_state(struct mt76_dev *dev, enum mt76_testmode_state state);
static inline void mt76_testmode_reset(struct mt76_dev *dev, bool disable)
{
#ifdef CONFIG_NL80211_TESTMODE
enum mt76_testmode_state state = MT76_TM_STATE_IDLE;
if (disable || dev->test.state == MT76_TM_STATE_OFF)
state = MT76_TM_STATE_OFF;
mt76_testmode_set_state(dev, state);
#endif
}
/* internal */
static inline struct ieee80211_hw *
......@@ -900,6 +1004,7 @@ void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
struct napi_struct *napi);
void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
void mt76_testmode_tx_pending(struct mt76_dev *dev);
/* usb */
static inline bool mt76u_urb_error(struct urb *urb)
......@@ -934,13 +1039,12 @@ mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);
}
int mt76u_skb_dma_info(struct sk_buff *skb, u32 info);
int mt76_skb_adjust_pad(struct sk_buff *skb);
int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
u8 req_type, u16 val, u16 offset,
void *buf, size_t len);
void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
const u16 offset, const u32 val);
void mt76u_deinit(struct mt76_dev *dev);
int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,
bool ext);
int mt76u_alloc_mcu_queue(struct mt76_dev *dev);
......@@ -950,6 +1054,12 @@ void mt76u_stop_rx(struct mt76_dev *dev);
int mt76u_resume_rx(struct mt76_dev *dev);
void mt76u_queues_deinit(struct mt76_dev *dev);
int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,
const struct mt76_bus_ops *bus_ops);
int mt76s_alloc_queues(struct mt76_dev *dev);
void mt76s_stop_txrx(struct mt76_dev *dev);
void mt76s_deinit(struct mt76_dev *dev);
struct sk_buff *
mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
int data_len);
......
......@@ -44,7 +44,7 @@ mt7603_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
mutex_lock(&dev->mt76.mutex);
mvif->idx = ffs(~dev->vif_mask) - 1;
mvif->idx = ffs(~dev->mphy.vif_mask) - 1;
if (mvif->idx >= MT7603_MAX_INTERFACES) {
ret = -ENOSPC;
goto out;
......@@ -65,7 +65,7 @@ mt7603_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
}
idx = MT7603_WTBL_RESERVED - 1 - mvif->idx;
dev->vif_mask |= BIT(mvif->idx);
dev->mphy.vif_mask |= BIT(mvif->idx);
INIT_LIST_HEAD(&mvif->sta.poll_list);
mvif->sta.wcid.idx = idx;
mvif->sta.wcid.hw_key_idx = -1;
......@@ -107,7 +107,7 @@ mt7603_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
spin_unlock_bh(&dev->sta_poll_lock);
mutex_lock(&dev->mt76.mutex);
dev->vif_mask &= ~BIT(mvif->idx);
dev->mphy.vif_mask &= ~BIT(mvif->idx);
mutex_unlock(&dev->mt76.mutex);
}
......@@ -642,8 +642,10 @@ mt7603_set_coverage_class(struct ieee80211_hw *hw, s16 coverage_class)
{
struct mt7603_dev *dev = hw->priv;
mutex_lock(&dev->mt76.mutex);
dev->coverage_class = max_t(s16, coverage_class, 0);
mt7603_mac_set_timing(dev);
mutex_unlock(&dev->mt76.mutex);
}
static void mt7603_tx(struct ieee80211_hw *hw,
......
......@@ -108,8 +108,6 @@ struct mt7603_dev {
u32 rxfilter;
u8 vif_mask;
struct list_head sta_poll_list;
spinlock_t sta_poll_lock;
......
......@@ -28,13 +28,28 @@ config MT7622_WMAC
which has the same feature set as a MT7615, but limited to
2.4 GHz only.
config MT7663_USB_SDIO_COMMON
tristate
select MT7615_COMMON
config MT7663U
tristate "MediaTek MT7663U (USB) support"
select MT76_USB
select MT7615_COMMON
select MT7663_USB_SDIO_COMMON
depends on MAC80211
depends on USB
help
This adds support for MT7663U 802.11ax 2x2:2 wireless devices.
This adds support for MT7663U 802.11ac 2x2:2 wireless devices.
To compile this driver as a module, choose M here.
config MT7663S
tristate "MediaTek MT7663S (SDIO) support"
select MT76_SDIO
select MT7663_USB_SDIO_COMMON
depends on MAC80211
depends on MMC
help
This adds support for MT7663S 802.11ac 2x2:2 wireless devices.
To compile this driver as a module, choose M here.
......@@ -2,14 +2,19 @@
obj-$(CONFIG_MT7615_COMMON) += mt7615-common.o
obj-$(CONFIG_MT7615E) += mt7615e.o
obj-$(CONFIG_MT7663_USB_SDIO_COMMON) += mt7663-usb-sdio-common.o
obj-$(CONFIG_MT7663U) += mt7663u.o
obj-$(CONFIG_MT7663S) += mt7663s.o
CFLAGS_trace.o := -I$(src)
mt7615-common-y := main.o init.o mcu.o eeprom.o mac.o \
debugfs.o trace.o
mt7615-common-$(CONFIG_NL80211_TESTMODE) += testmode.o
mt7615e-y := pci.o pci_init.o dma.o pci_mac.o mmio.o
mt7615e-$(CONFIG_MT7622_WMAC) += soc.o
mt7663u-y := usb.o usb_mcu.o usb_init.o
mt7663-usb-sdio-common-y := usb_sdio.o
mt7663u-y := usb.o usb_mcu.o
mt7663s-y := sdio.o sdio_mcu.o sdio_txrx.o
......@@ -6,11 +6,16 @@ static int
mt7615_radar_pattern_set(void *data, u64 val)
{
struct mt7615_dev *dev = data;
int err;
if (!mt7615_wait_for_mcu_init(dev))
return 0;
return mt7615_mcu_rdd_send_pattern(dev);
mt7615_mutex_acquire(dev);
err = mt7615_mcu_rdd_send_pattern(dev);
mt7615_mutex_release(dev);
return err;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_pattern, NULL,
......@@ -46,6 +51,52 @@ mt7615_scs_get(void *data, u64 *val)
DEFINE_DEBUGFS_ATTRIBUTE(fops_scs, mt7615_scs_get,
mt7615_scs_set, "%lld\n");
static int
mt7615_pm_set(void *data, u64 val)
{
struct mt7615_dev *dev = data;
if (!mt7615_wait_for_mcu_init(dev))
return 0;
return mt7615_pm_set_enable(dev, val);
}
static int
mt7615_pm_get(void *data, u64 *val)
{
struct mt7615_dev *dev = data;
*val = dev->pm.enable;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_pm, mt7615_pm_get, mt7615_pm_set, "%lld\n");
static int
mt7615_pm_idle_timeout_set(void *data, u64 val)
{
struct mt7615_dev *dev = data;
dev->pm.idle_timeout = msecs_to_jiffies(val);
return 0;
}
static int
mt7615_pm_idle_timeout_get(void *data, u64 *val)
{
struct mt7615_dev *dev = data;
*val = jiffies_to_msecs(dev->pm.idle_timeout);
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_pm_idle_timeout, mt7615_pm_idle_timeout_get,
mt7615_pm_idle_timeout_set, "%lld\n");
static int
mt7615_dbdc_set(void *data, u64 val)
{
......@@ -84,7 +135,10 @@ mt7615_fw_debug_set(void *data, u64 val)
return 0;
dev->fw_debug = val;
mt7615_mutex_acquire(dev);
mt7615_mcu_fw_log_2_host(dev, dev->fw_debug ? 2 : 0);
mt7615_mutex_release(dev);
return 0;
}
......@@ -111,6 +165,8 @@ mt7615_reset_test_set(void *data, u64 val)
if (!mt7615_wait_for_mcu_init(dev))
return 0;
mt7615_mutex_acquire(dev);
skb = alloc_skb(1, GFP_KERNEL);
if (!skb)
return -ENOMEM;
......@@ -118,6 +174,8 @@ mt7615_reset_test_set(void *data, u64 val)
skb_put(skb, 1);
mt76_tx_queue_skb_raw(dev, 0, skb, 0);
mt7615_mutex_release(dev);
return 0;
}
......@@ -167,9 +225,13 @@ mt7615_ampdu_stat_read(struct seq_file *file, void *data)
{
struct mt7615_dev *dev = file->private;
mt7615_mutex_acquire(dev);
mt7615_ampdu_stat_read_phy(&dev->phy, file);
mt7615_ampdu_stat_read_phy(mt7615_ext_phy(dev), file);
mt7615_mutex_release(dev);
return 0;
}
......@@ -221,7 +283,10 @@ static int mt7615_read_temperature(struct seq_file *s, void *data)
return 0;
/* cpu */
mt7615_mutex_acquire(dev);
temp = mt7615_mcu_get_temperature(dev, 0);
mt7615_mutex_release(dev);
seq_printf(s, "Temperature: %d\n", temp);
return 0;
......@@ -233,11 +298,14 @@ mt7615_queues_acq(struct seq_file *s, void *data)
struct mt7615_dev *dev = dev_get_drvdata(s->private);
int i;
mt7615_mutex_acquire(dev);
for (i = 0; i < 16; i++) {
int j, acs = i / 4, index = i % 4;
int j, wmm_idx = i % MT7615_MAX_WMM_SETS;
int acs = i / MT7615_MAX_WMM_SETS;
u32 ctrl, val, qlen = 0;
val = mt76_rr(dev, MT_PLE_AC_QEMPTY(acs, index));
val = mt76_rr(dev, MT_PLE_AC_QEMPTY(acs, wmm_idx));
ctrl = BIT(31) | BIT(15) | (acs << 8);
for (j = 0; j < 32; j++) {
......@@ -245,13 +313,15 @@ mt7615_queues_acq(struct seq_file *s, void *data)
continue;
mt76_wr(dev, MT_PLE_FL_Q0_CTRL,
ctrl | (j + (index << 5)));
ctrl | (j + (wmm_idx << 5)));
qlen += mt76_get_field(dev, MT_PLE_FL_Q3_CTRL,
GENMASK(11, 0));
}
seq_printf(s, "AC%d%d: queued=%d\n", acs, index, qlen);
seq_printf(s, "AC%d%d: queued=%d\n", wmm_idx, acs, qlen);
}
mt7615_mutex_release(dev);
return 0;
}
......@@ -284,6 +354,29 @@ mt7615_queues_read(struct seq_file *s, void *data)
return 0;
}
static int
mt7615_rf_reg_set(void *data, u64 val)
{
struct mt7615_dev *dev = data;
mt7615_rf_wr(dev, dev->debugfs_rf_wf, dev->debugfs_rf_reg, val);
return 0;
}
static int
mt7615_rf_reg_get(void *data, u64 *val)
{
struct mt7615_dev *dev = data;
*val = mt7615_rf_rr(dev, dev->debugfs_rf_wf, dev->debugfs_rf_reg);
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_reg, mt7615_rf_reg_get, mt7615_rf_reg_set,
"0x%08llx\n");
int mt7615_init_debugfs(struct mt7615_dev *dev)
{
struct dentry *dir;
......@@ -304,6 +397,9 @@ int mt7615_init_debugfs(struct mt7615_dev *dev)
debugfs_create_file("scs", 0600, dir, dev, &fops_scs);
debugfs_create_file("dbdc", 0600, dir, dev, &fops_dbdc);
debugfs_create_file("fw_debug", 0600, dir, dev, &fops_fw_debug);
debugfs_create_file("runtime-pm", 0600, dir, dev, &fops_pm);
debugfs_create_file("idle-timeout", 0600, dir, dev,
&fops_pm_idle_timeout);
debugfs_create_devm_seqfile(dev->mt76.dev, "radio", dir,
mt7615_radio_read);
debugfs_create_u32("dfs_hw_pattern", 0400, dir, &dev->hw_pattern);
......@@ -323,6 +419,11 @@ int mt7615_init_debugfs(struct mt7615_dev *dev)
debugfs_create_devm_seqfile(dev->mt76.dev, "temperature", dir,
mt7615_read_temperature);
debugfs_create_u32("rf_wfidx", 0600, dir, &dev->debugfs_rf_wf);
debugfs_create_u32("rf_regidx", 0600, dir, &dev->debugfs_rf_reg);
debugfs_create_file_unsafe("rf_regval", 0600, dir, dev,
&fops_rf_reg);
return 0;
}
EXPORT_SYMBOL_GPL(mt7615_init_debugfs);
......@@ -36,10 +36,10 @@ static int
mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
{
static const u8 wmm_queue_map[] = {
MT7622_TXQ_AC0,
MT7622_TXQ_AC1,
MT7622_TXQ_AC2,
MT7622_TXQ_AC3,
[IEEE80211_AC_BK] = MT7622_TXQ_AC0,
[IEEE80211_AC_BE] = MT7622_TXQ_AC1,
[IEEE80211_AC_VI] = MT7622_TXQ_AC2,
[IEEE80211_AC_VO] = MT7622_TXQ_AC3,
};
int ret;
int i;
......@@ -100,6 +100,7 @@ mt7615_tx_cleanup(struct mt7615_dev *dev)
int i;
mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false);
mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false);
if (is_mt7615(&dev->mt76)) {
mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false);
} else {
......@@ -121,10 +122,6 @@ static int mt7615_poll_tx(struct napi_struct *napi, int budget)
mt7615_tx_cleanup(dev);
rcu_read_lock();
mt7615_mac_sta_poll(dev);
rcu_read_unlock();
tasklet_schedule(&dev->mt76.tx_tasklet);
return 0;
......
......@@ -285,7 +285,9 @@ mt7615_regd_notifier(struct wiphy *wiphy,
if (!(chandef->chan->flags & IEEE80211_CHAN_RADAR))
return;
mt7615_mutex_acquire(dev);
mt7615_dfs_init_radar_detector(phy);
mt7615_mutex_release(dev);
}
static void
......@@ -321,6 +323,7 @@ mt7615_init_wiphy(struct ieee80211_hw *hw)
ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN);
ieee80211_hw_set(hw, WANT_MONITOR_VIF);
if (is_mt7615(&phy->dev->mt76))
hw->max_tx_fragments = MT_TXP_MAX_BUF_NUM;
......@@ -405,9 +408,6 @@ int mt7615_register_ext_phy(struct mt7615_dev *dev)
mphy->sband_2g.sband.n_channels = 0;
mphy->hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
/* The second interface does not get any packets unless it has a vif */
ieee80211_hw_set(mphy->hw, WANT_MONITOR_VIF);
ret = mt76_register_phy(mphy);
if (ret)
ieee80211_free_hw(mphy->hw);
......@@ -437,6 +437,12 @@ void mt7615_init_device(struct mt7615_dev *dev)
dev->phy.dev = dev;
dev->phy.mt76 = &dev->mt76.phy;
dev->mt76.phy.priv = &dev->phy;
INIT_DELAYED_WORK(&dev->pm.ps_work, mt7615_pm_power_save_work);
INIT_WORK(&dev->pm.wake_work, mt7615_pm_wake_work);
init_completion(&dev->pm.wake_cmpl);
spin_lock_init(&dev->pm.txq_lock);
set_bit(MT76_STATE_PM, &dev->mphy.state);
INIT_DELAYED_WORK(&dev->phy.mac_work, mt7615_mac_work);
INIT_DELAYED_WORK(&dev->phy.scan_work, mt7615_scan_work);
skb_queue_head_init(&dev->phy.scan_event_list);
......@@ -450,6 +456,7 @@ void mt7615_init_device(struct mt7615_dev *dev)
timer_setup(&dev->phy.roc_timer, mt7615_roc_timer, 0);
mt7615_init_wiphy(hw);
dev->pm.idle_timeout = MT7615_PM_TIMEOUT;
dev->mphy.sband_2g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
dev->mphy.sband_5g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
dev->mphy.sband_5g.sband.vht_cap.cap |=
......@@ -457,5 +464,9 @@ void mt7615_init_device(struct mt7615_dev *dev)
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
mt7615_cap_dbdc_disable(dev);
dev->phy.dfs_state = -1;
#ifdef CONFIG_NL80211_TESTMODE
dev->mt76.test_ops = &mt7615_testmode_ops;
#endif
}
EXPORT_SYMBOL_GPL(mt7615_init_device);
......@@ -100,11 +100,16 @@ enum rx_pkt_type {
#define MT_RXV2_GROUP_ID GENMASK(26, 21)
#define MT_RXV2_LENGTH GENMASK(20, 0)
#define MT_RXV3_WB_RSSI GENMASK(31, 24)
#define MT_RXV3_IB_RSSI GENMASK(23, 16)
#define MT_RXV4_RCPI3 GENMASK(31, 24)
#define MT_RXV4_RCPI2 GENMASK(23, 16)
#define MT_RXV4_RCPI1 GENMASK(15, 8)
#define MT_RXV4_RCPI0 GENMASK(7, 0)
#define MT_RXV5_FOE GENMASK(11, 0)
#define MT_RXV6_NF3 GENMASK(31, 24)
#define MT_RXV6_NF2 GENMASK(23, 16)
#define MT_RXV6_NF1 GENMASK(15, 8)
......@@ -124,21 +129,6 @@ enum tx_pkt_type {
MT_TX_TYPE_FW,
};
enum tx_pkt_queue_idx {
MT_LMAC_AC00,
MT_LMAC_AC01,
MT_LMAC_AC02,
MT_LMAC_AC03,
MT_LMAC_ALTX0 = 0x10,
MT_LMAC_BMC0,
MT_LMAC_BCN0,
MT_LMAC_PSMP0,
MT_LMAC_ALTX1,
MT_LMAC_BMC1,
MT_LMAC_BCN1,
MT_LMAC_PSMP1,
};
enum tx_port_idx {
MT_TX_PORT_IDX_LMAC,
MT_TX_PORT_IDX_MCU
......
......@@ -81,6 +81,7 @@ enum {
MCU_EVENT_GENERIC = 0x01,
MCU_EVENT_ACCESS_REG = 0x02,
MCU_EVENT_MT_PATCH_SEM = 0x04,
MCU_EVENT_REG_ACCESS = 0x05,
MCU_EVENT_SCAN_DONE = 0x0d,
MCU_EVENT_ROC = 0x10,
MCU_EVENT_BSS_ABSENCE = 0x11,
......@@ -238,8 +239,11 @@ enum {
#define MCU_FW_PREFIX BIT(31)
#define MCU_UNI_PREFIX BIT(30)
#define MCU_CE_PREFIX BIT(29)
#define MCU_QUERY_PREFIX BIT(28)
#define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \
MCU_CE_PREFIX)
MCU_CE_PREFIX | MCU_QUERY_PREFIX)
#define MCU_QUERY_MASK BIT(16)
enum {
MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01,
......@@ -254,6 +258,7 @@ enum {
};
enum {
MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
......@@ -266,6 +271,7 @@ enum {
MCU_EXT_CMD_GET_TEMP = 0x2c,
MCU_EXT_CMD_WTBL_UPDATE = 0x32,
MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
MCU_EXT_CMD_ATE_CTRL = 0x3d,
MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
MCU_EXT_CMD_DBDC_CTRL = 0x45,
MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
......@@ -287,6 +293,11 @@ enum {
MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07,
};
enum {
MCU_ATE_SET_FREQ_OFFSET = 0xa,
MCU_ATE_SET_TX_POWER_CONTROL = 0x15,
};
struct mt7615_mcu_uni_event {
u8 cid;
u8 pad[3];
......@@ -421,6 +432,11 @@ struct nt7615_sched_scan_done {
__le16 pad;
} __packed;
struct mt7615_mcu_reg_event {
__le32 reg;
__le32 val;
} __packed;
struct mt7615_mcu_bss_event {
u8 bss_idx;
u8 is_absent;
......@@ -454,6 +470,13 @@ struct mt7615_bss_basic_tlv {
u8 pad[3];
} __packed;
struct mt7615_bss_qos_tlv {
__le16 tag;
__le16 len;
u8 qos;
u8 pad[3];
} __packed;
struct mt7615_wow_ctrl_tlv {
__le16 tag;
__le16 len;
......@@ -545,6 +568,15 @@ struct mt7615_roc_tlv {
u8 rsv1[8];
} __packed;
struct mt7615_arpns_tlv {
__le16 tag;
__le16 len;
u8 mode;
u8 ips_num;
u8 option;
u8 pad[1];
} __packed;
/* offload mcu commands */
enum {
MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03,
......@@ -557,6 +589,8 @@ enum {
MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33,
MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61,
MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62,
MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0,
MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0,
};
#define MCU_CMD_ACK BIT(0)
......@@ -569,6 +603,8 @@ enum {
UNI_BSS_INFO_BASIC = 0,
UNI_BSS_INFO_RLM = 2,
UNI_BSS_INFO_BCN_CONTENT = 7,
UNI_BSS_INFO_QBSS = 15,
UNI_BSS_INFO_UAPSD = 19,
};
enum {
......@@ -580,8 +616,8 @@ enum {
};
enum {
UNI_OFFLOAD_OFFLOAD_ARPNS_IPV4,
UNI_OFFLOAD_OFFLOAD_ARPNS_IPV6,
UNI_OFFLOAD_OFFLOAD_ARP,
UNI_OFFLOAD_OFFLOAD_ND,
UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
};
......@@ -882,6 +918,7 @@ struct wtbl_raw {
sizeof(struct sta_rec_basic) + \
sizeof(struct sta_rec_ht) + \
sizeof(struct sta_rec_vht) + \
sizeof(struct sta_rec_uapsd) + \
sizeof(struct tlv) + \
MT7615_WTBL_UPDATE_MAX_SIZE)
......@@ -971,6 +1008,17 @@ struct sta_rec_ba {
__le16 winsize;
} __packed;
struct sta_rec_uapsd {
__le16 tag;
__le16 len;
u8 dac_map;
u8 tac_map;
u8 max_sp;
u8 rsv0;
__le16 listen_interval;
u8 rsv1[2];
} __packed;
enum {
STA_REC_BASIC,
STA_REC_RA,
......
......@@ -17,7 +17,6 @@ const u32 mt7615e_reg_map[] = {
[MT_CSR_BASE] = 0x07000,
[MT_PLE_BASE] = 0x08000,
[MT_PSE_BASE] = 0x0c000,
[MT_PHY_BASE] = 0x10000,
[MT_CFG_BASE] = 0x20200,
[MT_AGG_BASE] = 0x20a00,
[MT_TMAC_BASE] = 0x21000,
......@@ -44,7 +43,7 @@ const u32 mt7663e_reg_map[] = {
[MT_CSR_BASE] = 0x07000,
[MT_PLE_BASE] = 0x08000,
[MT_PSE_BASE] = 0x0c000,
[MT_PHY_BASE] = 0x10000,
[MT_PP_BASE] = 0x0e000,
[MT_CFG_BASE] = 0x20000,
[MT_AGG_BASE] = 0x22000,
[MT_TMAC_BASE] = 0x24000,
......@@ -140,13 +139,45 @@ static void mt7615_irq_tasklet(unsigned long data)
mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
}
static u32 __mt7615_reg_addr(struct mt7615_dev *dev, u32 addr)
{
if (addr < 0x100000)
return addr;
return mt7615_reg_map(dev, addr);
}
static u32 mt7615_rr(struct mt76_dev *mdev, u32 offset)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
u32 addr = __mt7615_reg_addr(dev, offset);
return dev->bus_ops->rr(mdev, addr);
}
static void mt7615_wr(struct mt76_dev *mdev, u32 offset, u32 val)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
u32 addr = __mt7615_reg_addr(dev, offset);
dev->bus_ops->wr(mdev, addr, val);
}
static u32 mt7615_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
u32 addr = __mt7615_reg_addr(dev, offset);
return dev->bus_ops->rmw(mdev, addr, mask, val);
}
int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base,
int irq, const u32 *map)
{
static const struct mt76_driver_ops drv_ops = {
/* txwi_size = txd size + txp size */
.txwi_size = MT_TXD_SIZE + sizeof(struct mt7615_txp_common),
.drv_flags = MT_DRV_TXWI_NO_FREE,
.drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
.survey_flags = SURVEY_INFO_TIME_TX |
SURVEY_INFO_TIME_RX |
SURVEY_INFO_TIME_BSS_RX,
......@@ -159,6 +190,7 @@ int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base,
.sta_remove = mt7615_mac_sta_remove,
.update_survey = mt7615_update_channel,
};
struct mt76_bus_ops *bus_ops;
struct ieee80211_ops *ops;
struct mt7615_dev *dev;
struct mt76_dev *mdev;
......@@ -182,6 +214,19 @@ int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base,
(mt76_rr(dev, MT_HW_REV) & 0xff);
dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
dev->bus_ops = dev->mt76.bus;
bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
GFP_KERNEL);
if (!bus_ops) {
ret = -ENOMEM;
goto error;
}
bus_ops->rr = mt7615_rr;
bus_ops->wr = mt7615_wr;
bus_ops->rmw = mt7615_rmw;
dev->mt76.bus = bus_ops;
ret = devm_request_irq(mdev->dev, irq, mt7615_irq_handler,
IRQF_SHARED, KBUILD_MODNAME, dev);
if (ret)
......
......@@ -4,6 +4,7 @@
#ifndef __MT7615_H
#define __MT7615_H
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/ktime.h>
#include <linux/regmap.h>
......@@ -18,6 +19,7 @@
#define MT7615_WTBL_STA (MT7615_WTBL_RESERVED - \
MT7615_MAX_INTERFACES)
#define MT7615_PM_TIMEOUT (HZ / 12)
#define MT7615_WATCHDOG_TIME (HZ / 10)
#define MT7615_HW_SCAN_TIMEOUT (HZ / 10)
#define MT7615_RESET_TIMEOUT (30 * HZ)
......@@ -31,6 +33,8 @@
#define MT7615_RX_RING_SIZE 1024
#define MT7615_RX_MCU_RING_SIZE 512
#define MT7615_DRV_OWN_RETRY_COUNT 10
#define MT7615_FIRMWARE_CR4 "mediatek/mt7615_cr4.bin"
#define MT7615_FIRMWARE_N9 "mediatek/mt7615_n9.bin"
#define MT7615_ROM_PATCH "mediatek/mt7615_rom_patch.bin"
......@@ -169,6 +173,8 @@ struct mt7615_phy {
struct mt76_phy *mt76;
struct mt7615_dev *dev;
struct ieee80211_vif *monitor_vif;
u32 rxfilter;
u32 omac_mask;
......@@ -240,10 +246,10 @@ struct mt7615_dev {
struct mt76_phy mphy;
};
const struct mt76_bus_ops *bus_ops;
struct tasklet_struct irq_tasklet;
struct mt7615_phy phy;
u32 vif_mask;
u32 omac_mask;
u16 chainmask;
......@@ -280,6 +286,52 @@ struct mt7615_dev {
struct work_struct wtbl_work;
struct list_head wd_head;
u32 debugfs_rf_wf;
u32 debugfs_rf_reg;
#ifdef CONFIG_NL80211_TESTMODE
struct {
u32 *reg_backup;
s16 last_freq_offset;
u8 last_rcpi[4];
s8 last_ib_rssi;
s8 last_wb_rssi;
} test;
#endif
struct {
bool enable;
spinlock_t txq_lock;
struct {
struct mt7615_sta *msta;
struct sk_buff *skb;
} tx_q[IEEE80211_NUM_ACS];
struct work_struct wake_work;
struct completion wake_cmpl;
struct delayed_work ps_work;
unsigned long last_activity;
unsigned long idle_timeout;
} pm;
};
enum tx_pkt_queue_idx {
MT_LMAC_AC00,
MT_LMAC_AC01,
MT_LMAC_AC02,
MT_LMAC_AC03,
MT_LMAC_ALTX0 = 0x10,
MT_LMAC_BMC0,
MT_LMAC_BCN0,
MT_LMAC_PSMP0,
MT_LMAC_ALTX1,
MT_LMAC_BMC1,
MT_LMAC_BCN1,
MT_LMAC_PSMP1,
};
enum {
......@@ -357,8 +409,10 @@ extern struct ieee80211_rate mt7615_rates[12];
extern const struct ieee80211_ops mt7615_ops;
extern const u32 mt7615e_reg_map[__MT_BASE_MAX];
extern const u32 mt7663e_reg_map[__MT_BASE_MAX];
extern const u32 mt7663_usb_sdio_reg_map[__MT_BASE_MAX];
extern struct pci_driver mt7615_pci_driver;
extern struct platform_driver mt7622_wmac_driver;
extern const struct mt76_testmode_ops mt7615_testmode_ops;
#ifdef CONFIG_MT7622_WMAC
int mt7622_wmac_init(struct mt7615_dev *dev);
......@@ -393,6 +447,11 @@ bool mt7615_wait_for_mcu_init(struct mt7615_dev *dev);
void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
struct ieee80211_tx_rate *probe_rate,
struct ieee80211_tx_rate *rates);
int mt7615_pm_set_enable(struct mt7615_dev *dev, bool enable);
void mt7615_pm_wake_work(struct work_struct *work);
int mt7615_pm_wake(struct mt7615_dev *dev);
void mt7615_pm_power_save_sched(struct mt7615_dev *dev);
void mt7615_pm_power_save_work(struct work_struct *work);
int mt7615_mcu_del_wtbl_all(struct mt7615_dev *dev);
int mt7615_mcu_set_chan_info(struct mt7615_phy *phy, int cmd);
int mt7615_mcu_set_wmm(struct mt7615_dev *dev, u8 queue,
......@@ -447,6 +506,35 @@ static inline u16 mt7615_wtbl_size(struct mt7615_dev *dev)
return MT7615_WTBL_SIZE;
}
static inline void mt7615_mutex_acquire(struct mt7615_dev *dev)
__acquires(&dev->mt76.mutex)
{
mutex_lock(&dev->mt76.mutex);
mt7615_pm_wake(dev);
}
static inline void mt7615_mutex_release(struct mt7615_dev *dev)
__releases(&dev->mt76.mutex)
{
mt7615_pm_power_save_sched(dev);
mutex_unlock(&dev->mt76.mutex);
}
static inline u8 mt7615_lmac_mapping(struct mt7615_dev *dev, u8 ac)
{
static const u8 lmac_queue_map[] = {
[IEEE80211_AC_BK] = MT_LMAC_AC00,
[IEEE80211_AC_BE] = MT_LMAC_AC01,
[IEEE80211_AC_VI] = MT_LMAC_AC02,
[IEEE80211_AC_VO] = MT_LMAC_AC03,
};
if (WARN_ON_ONCE(ac >= ARRAY_SIZE(lmac_queue_map)))
return MT_LMAC_AC01; /* BE */
return lmac_queue_map[ac];
}
void mt7615_dma_reset(struct mt7615_dev *dev);
void mt7615_scan_work(struct work_struct *work);
void mt7615_roc_work(struct work_struct *work);
......@@ -455,6 +543,7 @@ void mt7615_init_txpower(struct mt7615_dev *dev,
struct ieee80211_supported_band *sband);
void mt7615_phy_init(struct mt7615_dev *dev);
void mt7615_mac_init(struct mt7615_dev *dev);
int mt7615_set_channel(struct mt7615_phy *phy);
int mt7615_mcu_restart(struct mt76_dev *dev);
void mt7615_update_channel(struct mt76_dev *mdev);
......@@ -486,15 +575,19 @@ int mt7615_mac_wtbl_update_key(struct mt7615_dev *dev,
enum mt7615_cipher_type cipher,
enum set_key_cmd cmd);
void mt7615_mac_reset_work(struct work_struct *work);
u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid);
int mt7615_mcu_wait_response(struct mt7615_dev *dev, int cmd, int seq);
int mt7615_mcu_msg_send(struct mt76_dev *mdev, int cmd, const void *data,
int len, bool wait_resp);
u32 mt7615_rf_rr(struct mt7615_dev *dev, u32 wf, u32 reg);
int mt7615_rf_wr(struct mt7615_dev *dev, u32 wf, u32 reg, u32 val);
int mt7615_mcu_set_dbdc(struct mt7615_dev *dev);
int mt7615_mcu_set_eeprom(struct mt7615_dev *dev);
int mt7615_mcu_set_mac_enable(struct mt7615_dev *dev, int band, bool enable);
int mt7615_mcu_set_rts_thresh(struct mt7615_phy *phy, u32 val);
int mt7615_mcu_get_temperature(struct mt7615_dev *dev, int index);
int mt7615_mcu_set_tx_power(struct mt7615_phy *phy);
void mt7615_mcu_exit(struct mt7615_dev *dev);
void mt7615_mcu_fill_msg(struct mt7615_dev *dev, struct sk_buff *skb,
int cmd, int *wait_seq);
......@@ -533,6 +626,8 @@ int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev,
const struct mt7615_dfs_pulse *pulse);
int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index,
const struct mt7615_dfs_pattern *pattern);
int mt7615_mcu_set_test_param(struct mt7615_dev *dev, u8 param, bool test_mode,
u32 val);
int mt7615_mcu_set_sku_en(struct mt7615_phy *phy, bool enable);
int mt7615_mcu_apply_rx_dcoc(struct mt7615_phy *phy);
int mt7615_mcu_apply_tx_dpd(struct mt7615_phy *phy);
......@@ -549,18 +644,40 @@ int mt7615_driver_own(struct mt7615_dev *dev);
int mt7615_init_debugfs(struct mt7615_dev *dev);
int mt7615_mcu_wait_response(struct mt7615_dev *dev, int cmd, int seq);
int mt7615_mcu_set_bss_pm(struct mt7615_dev *dev, struct ieee80211_vif *vif,
bool enable);
int mt7615_mcu_set_hif_suspend(struct mt7615_dev *dev, bool suspend);
void mt7615_mcu_set_suspend_iter(void *priv, u8 *mac,
struct ieee80211_vif *vif);
int mt7615_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct cfg80211_gtk_rekey_data *key);
int mt7615_mcu_update_arp_filter(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *info);
int __mt7663_load_firmware(struct mt7615_dev *dev);
u32 mt7615_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
void mt7615_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
/* usb */
void mt7663u_wtbl_work(struct work_struct *work);
int mt7663_usb_sdio_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
enum mt76_txq_id qid, struct mt76_wcid *wcid,
struct ieee80211_sta *sta,
struct mt76_tx_info *tx_info);
bool mt7663_usb_sdio_tx_status_data(struct mt76_dev *mdev, u8 *update);
void mt7663_usb_sdio_tx_complete_skb(struct mt76_dev *mdev,
enum mt76_txq_id qid,
struct mt76_queue_entry *e);
void mt7663_usb_sdio_wtbl_work(struct work_struct *work);
int mt7663_usb_sdio_register_device(struct mt7615_dev *dev);
int mt7663u_mcu_init(struct mt7615_dev *dev);
int mt7663u_register_device(struct mt7615_dev *dev);
/* sdio */
u32 mt7663s_read_pcr(struct mt7615_dev *dev);
int mt7663s_mcu_init(struct mt7615_dev *dev);
int mt7663s_driver_own(struct mt7615_dev *dev);
int mt7663s_firmware_own(struct mt7615_dev *dev);
int mt7663s_kthread_run(void *data);
void mt7663s_sdio_irq(struct sdio_func *func);
#endif
......@@ -75,6 +75,10 @@ static int mt7615_pci_suspend(struct pci_dev *pdev, pm_message_t state)
bool hif_suspend;
int i, err;
err = mt7615_pm_wake(dev);
if (err < 0)
return err;
hif_suspend = !test_bit(MT76_STATE_SUSPEND, &dev->mphy.state) &&
mt7615_firmware_offload(dev);
if (hif_suspend) {
......
......@@ -70,6 +70,10 @@ mt7615_led_set_config(struct led_classdev *led_cdev,
mt76 = container_of(led_cdev, struct mt76_dev, led_cdev);
dev = container_of(mt76, struct mt7615_dev, mt76);
if (test_bit(MT76_STATE_PM, &mt76->phy.state))
return;
val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |
FIELD_PREP(MT_LED_STATUS_OFF, delay_off) |
FIELD_PREP(MT_LED_STATUS_ON, delay_on);
......
......@@ -155,7 +155,6 @@ int mt7615_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
spin_lock_bh(&dev->mt76.lock);
mt7615_mac_set_rates(phy, msta, &info->control.rates[0],
msta->rates);
msta->rate_probe = true;
spin_unlock_bh(&dev->mt76.lock);
}
......
......@@ -14,7 +14,6 @@ enum mt7615_reg_base {
MT_CSR_BASE,
MT_PLE_BASE,
MT_PSE_BASE,
MT_PHY_BASE,
MT_CFG_BASE,
MT_AGG_BASE,
MT_TMAC_BASE,
......@@ -29,6 +28,7 @@ enum mt7615_reg_base {
MT_PCIE_REMAP_BASE2,
MT_TOP_MISC_BASE,
MT_EFUSE_ADDR_BASE,
MT_PP_BASE,
__MT_BASE_MAX,
};
......@@ -153,6 +153,8 @@ enum mt7615_reg_base {
#define MT_PLE(ofs) ((dev)->reg_map[MT_PLE_BASE] + (ofs))
#define MT_PLE_PG_HIF0_GROUP MT_PLE(0x110)
#define MT_HIF0_MIN_QUOTA GENMASK(11, 0)
#define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
#define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
#define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
......@@ -162,6 +164,10 @@ enum mt7615_reg_base {
((n) << 2))
#define MT_PSE(ofs) ((dev)->reg_map[MT_PSE_BASE] + (ofs))
#define MT_PSE_PG_HIF0_GROUP MT_PSE(0x110)
#define MT_HIF0_MIN_QUOTA GENMASK(11, 0)
#define MT_PSE_PG_HIF1_GROUP MT_PSE(0x118)
#define MT_HIF1_MIN_QUOTA GENMASK(11, 0)
#define MT_PSE_QUEUE_EMPTY MT_PSE(0x0b4)
#define MT_HIF_0_EMPTY_MASK BIT(16)
#define MT_HIF_1_EMPTY_MASK BIT(17)
......@@ -169,7 +175,12 @@ enum mt7615_reg_base {
#define MT_PSE_PG_INFO MT_PSE(0x194)
#define MT_PSE_SRC_CNT GENMASK(27, 16)
#define MT_WF_PHY_BASE ((dev)->reg_map[MT_PHY_BASE])
#define MT_PP(ofs) ((dev)->reg_map[MT_PP_BASE] + (ofs))
#define MT_PP_TXDWCNT MT_PP(0x0)
#define MT_PP_TXDWCNT_TX0_ADD_DW_CNT GENMASK(7, 0)
#define MT_PP_TXDWCNT_TX1_ADD_DW_CNT GENMASK(15, 8)
#define MT_WF_PHY_BASE 0x82070000
#define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
#define MT_WF_PHY_WF2_RFCTRL0(n) MT_WF_PHY(0x1900 + (n) * 0x400)
......@@ -213,6 +224,9 @@ enum mt7615_reg_base {
#define MT_WF_PHY_RXTD2_BASE MT_WF_PHY(0x2a00)
#define MT_WF_PHY_RXTD2(_n) (MT_WF_PHY_RXTD2_BASE + ((_n) << 2))
#define MT_WF_PHY_RFINTF3_0(_n) MT_WF_PHY(0x1100 + (_n) * 0x400)
#define MT_WF_PHY_RFINTF3_0_ANT GENMASK(7, 4)
#define MT_WF_CFG_BASE ((dev)->reg_map[MT_CFG_BASE])
#define MT_WF_CFG(ofs) (MT_WF_CFG_BASE + (ofs))
......@@ -256,6 +270,13 @@ enum mt7615_reg_base {
#define MT_WF_ARB_BASE ((dev)->reg_map[MT_ARB_BASE])
#define MT_WF_ARB(ofs) (MT_WF_ARB_BASE + (ofs))
#define MT_ARB_RQCR MT_WF_ARB(0x070)
#define MT_ARB_RQCR_RX_START BIT(0)
#define MT_ARB_RQCR_RXV_START BIT(4)
#define MT_ARB_RQCR_RXV_R_EN BIT(7)
#define MT_ARB_RQCR_RXV_T_EN BIT(8)
#define MT_ARB_RQCR_BAND_SHIFT 16
#define MT_ARB_SCR MT_WF_ARB(0x080)
#define MT_ARB_SCR_TX0_DISABLE BIT(8)
#define MT_ARB_SCR_RX0_DISABLE BIT(9)
......@@ -417,6 +438,7 @@ enum mt7615_reg_base {
#define MT_LPON_T0CR MT_LPON(0x010)
#define MT_LPON_T0CR_MODE GENMASK(1, 0)
#define MT_LPON_T0CR_WRITE BIT(0)
#define MT_LPON_UTTR0 MT_LPON(0x018)
#define MT_LPON_UTTR1 MT_LPON(0x01c)
......@@ -550,4 +572,11 @@ enum mt7615_reg_base {
#define MT_WL_RX_BUSY BIT(30)
#define MT_WL_TX_BUSY BIT(31)
#define MT_MCU_PTA_BASE 0x81060000
#define MT_MCU_PTA(_n) (MT_MCU_PTA_BASE + (_n))
#define MT_ANT_SWITCH_CON(n) MT_MCU_PTA(0x0c8)
#define MT_ANT_SWITCH_CON_MODE(_n) (GENMASK(4, 0) << (_n * 8))
#define MT_ANT_SWITCH_CON_MODE1(_n) (GENMASK(3, 0) << (_n * 8))
#endif
This diff is collapsed.
// SPDX-License-Identifier: ISC
/* Copyright (C) 2020 MediaTek Inc.
*
* Author: Sean Wang <sean.wang@mediatek.com>
*/
#ifndef __MT76S_H
#define __MT76S_H
#define MT_PSE_PAGE_SZ 128
#define MCR_WCIR 0x0000
#define MCR_WHLPCR 0x0004
#define WHLPCR_FW_OWN_REQ_CLR BIT(9)
#define WHLPCR_FW_OWN_REQ_SET BIT(8)
#define WHLPCR_IS_DRIVER_OWN BIT(8)
#define WHLPCR_INT_EN_CLR BIT(1)
#define WHLPCR_INT_EN_SET BIT(0)
#define MCR_WSDIOCSR 0x0008
#define MCR_WHCR 0x000C
#define W_INT_CLR_CTRL BIT(1)
#define RECV_MAILBOX_RD_CLR_EN BIT(2)
#define MAX_HIF_RX_LEN_NUM GENMASK(13, 8)
#define RX_ENHANCE_MODE BIT(16)
#define MCR_WHISR 0x0010
#define MCR_WHIER 0x0014
#define WHIER_D2H_SW_INT GENMASK(31, 8)
#define WHIER_FW_OWN_BACK_INT_EN BIT(7)
#define WHIER_ABNORMAL_INT_EN BIT(6)
#define WHIER_RX1_DONE_INT_EN BIT(2)
#define WHIER_RX0_DONE_INT_EN BIT(1)
#define WHIER_TX_DONE_INT_EN BIT(0)
#define WHIER_DEFAULT (WHIER_RX0_DONE_INT_EN | \
WHIER_RX1_DONE_INT_EN | \
WHIER_TX_DONE_INT_EN | \
WHIER_ABNORMAL_INT_EN | \
WHIER_D2H_SW_INT)
#define MCR_WASR 0x0020
#define MCR_WSICR 0x0024
#define MCR_WTSR0 0x0028
#define TQ0_CNT GENMASK(7, 0)
#define TQ1_CNT GENMASK(15, 8)
#define TQ2_CNT GENMASK(23, 16)
#define TQ3_CNT GENMASK(31, 24)
#define MCR_WTSR1 0x002c
#define TQ4_CNT GENMASK(7, 0)
#define TQ5_CNT GENMASK(15, 8)
#define TQ6_CNT GENMASK(23, 16)
#define TQ7_CNT GENMASK(31, 24)
#define MCR_WTDR1 0x0034
#define MCR_WRDR0 0x0050
#define MCR_WRDR1 0x0054
#define MCR_WRDR(p) (0x0050 + 4 * (p))
#define MCR_H2DSM0R 0x0070
#define H2D_SW_INT_READ BIT(16)
#define H2D_SW_INT_WRITE BIT(17)
#define MCR_H2DSM1R 0x0074
#define MCR_D2HRM0R 0x0078
#define MCR_D2HRM1R 0x007c
#define MCR_D2HRM2R 0x0080
#define MCR_WRPLR 0x0090
#define RX0_PACKET_LENGTH GENMASK(15, 0)
#define RX1_PACKET_LENGTH GENMASK(31, 16)
#define MCR_WTMDR 0x00b0
#define MCR_WTMCR 0x00b4
#define MCR_WTMDPCR0 0x00b8
#define MCR_WTMDPCR1 0x00bc
#define MCR_WPLRCR 0x00d4
#define MCR_WSR 0x00D8
#define MCR_CLKIOCR 0x0100
#define MCR_CMDIOCR 0x0104
#define MCR_DAT0IOCR 0x0108
#define MCR_DAT1IOCR 0x010C
#define MCR_DAT2IOCR 0x0110
#define MCR_DAT3IOCR 0x0114
#define MCR_CLKDLYCR 0x0118
#define MCR_CMDDLYCR 0x011C
#define MCR_ODATDLYCR 0x0120
#define MCR_IDATDLYCR1 0x0124
#define MCR_IDATDLYCR2 0x0128
#define MCR_ILCHCR 0x012C
#define MCR_WTQCR0 0x0130
#define MCR_WTQCR1 0x0134
#define MCR_WTQCR2 0x0138
#define MCR_WTQCR3 0x013C
#define MCR_WTQCR4 0x0140
#define MCR_WTQCR5 0x0144
#define MCR_WTQCR6 0x0148
#define MCR_WTQCR7 0x014C
#define MCR_WTQCR(x) (0x130 + 4 * (x))
#define TXQ_CNT_L GENMASK(15, 0)
#define TXQ_CNT_H GENMASK(31, 16)
#define MCR_SWPCDBGR 0x0154
struct mt76s_intr {
u32 isr;
struct {
u32 wtqcr[8];
} tx;
struct {
u16 num[2];
u16 len[2][16];
} rx;
u32 rec_mb[2];
} __packed;
#endif
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2020 MediaTek Inc.
*
* Author: Felix Fietkau <nbd@nbd.name>
* Lorenzo Bianconi <lorenzo@kernel.org>
* Sean Wang <sean.wang@mediatek.com>
*/
#include <linux/kernel.h>
#include <linux/mmc/sdio_func.h>
#include <linux/module.h>
#include <linux/iopoll.h>
#include "mt7615.h"
#include "mac.h"
#include "mcu.h"
#include "regs.h"
#include "sdio.h"
static int mt7663s_mcu_init_sched(struct mt7615_dev *dev)
{
struct mt76_sdio *sdio = &dev->mt76.sdio;
u32 pse0, ple, pse1, txdwcnt;
pse0 = mt76_get_field(dev, MT_PSE_PG_HIF0_GROUP, MT_HIF0_MIN_QUOTA);
pse1 = mt76_get_field(dev, MT_PSE_PG_HIF1_GROUP, MT_HIF1_MIN_QUOTA);
ple = mt76_get_field(dev, MT_PLE_PG_HIF0_GROUP, MT_HIF0_MIN_QUOTA);
txdwcnt = mt76_get_field(dev, MT_PP_TXDWCNT,
MT_PP_TXDWCNT_TX1_ADD_DW_CNT);
mutex_lock(&sdio->sched.lock);
sdio->sched.pse_data_quota = pse0;
sdio->sched.ple_data_quota = ple;
sdio->sched.pse_mcu_quota = pse1;
sdio->sched.deficit = txdwcnt << 2;
mutex_unlock(&sdio->sched.lock);
return 0;
}
static int
mt7663s_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
int cmd, bool wait_resp)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
int ret, seq;
mutex_lock(&mdev->mcu.mutex);
mt7615_mcu_fill_msg(dev, skb, cmd, &seq);
ret = mt76_tx_queue_skb_raw(dev, MT_TXQ_MCU, skb, 0);
if (ret)
goto out;
mt76_queue_kick(dev, mdev->q_tx[MT_TXQ_MCU].q);
if (wait_resp)
ret = mt7615_mcu_wait_response(dev, cmd, seq);
out:
mutex_unlock(&mdev->mcu.mutex);
return ret;
}
int mt7663s_driver_own(struct mt7615_dev *dev)
{
struct sdio_func *func = dev->mt76.sdio.func;
struct mt76_phy *mphy = &dev->mt76.phy;
u32 status;
int ret;
if (!test_and_clear_bit(MT76_STATE_PM, &mphy->state))
goto out;
sdio_claim_host(func);
sdio_writel(func, WHLPCR_FW_OWN_REQ_CLR, MCR_WHLPCR, 0);
ret = readx_poll_timeout(mt7663s_read_pcr, dev, status,
status & WHLPCR_IS_DRIVER_OWN, 2000, 1000000);
if (ret < 0) {
dev_err(dev->mt76.dev, "Cannot get ownership from device");
set_bit(MT76_STATE_PM, &mphy->state);
sdio_release_host(func);
return ret;
}
sdio_release_host(func);
out:
dev->pm.last_activity = jiffies;
return 0;
}
int mt7663s_firmware_own(struct mt7615_dev *dev)
{
struct sdio_func *func = dev->mt76.sdio.func;
struct mt76_phy *mphy = &dev->mt76.phy;
u32 status;
int ret;
if (test_and_set_bit(MT76_STATE_PM, &mphy->state))
return 0;
sdio_claim_host(func);
sdio_writel(func, WHLPCR_FW_OWN_REQ_SET, MCR_WHLPCR, 0);
ret = readx_poll_timeout(mt7663s_read_pcr, dev, status,
!(status & WHLPCR_IS_DRIVER_OWN), 2000, 1000000);
if (ret < 0) {
dev_err(dev->mt76.dev, "Cannot set ownership to device");
clear_bit(MT76_STATE_PM, &mphy->state);
}
sdio_release_host(func);
return ret;
}
int mt7663s_mcu_init(struct mt7615_dev *dev)
{
static const struct mt76_mcu_ops mt7663s_mcu_ops = {
.headroom = sizeof(struct mt7615_mcu_txd),
.tailroom = MT_USB_TAIL_SIZE,
.mcu_skb_send_msg = mt7663s_mcu_send_message,
.mcu_send_msg = mt7615_mcu_msg_send,
.mcu_restart = mt7615_mcu_restart,
.mcu_rr = mt7615_mcu_reg_rr,
.mcu_wr = mt7615_mcu_reg_wr,
};
int ret;
ret = mt7663s_driver_own(dev);
if (ret)
return ret;
dev->mt76.mcu_ops = &mt7663s_mcu_ops,
ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY);
if (ret) {
mt7615_mcu_restart(&dev->mt76);
if (!mt76_poll_msec(dev, MT_CONN_ON_MISC,
MT_TOP_MISC2_FW_N9_RDY, 0, 500))
return -EIO;
}
ret = __mt7663_load_firmware(dev);
if (ret)
return ret;
ret = mt7663s_mcu_init_sched(dev);
if (ret)
return ret;
set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
return 0;
}
// SPDX-License-Identifier: ISC
/* Copyright (C) 2020 MediaTek Inc.
*
* Author: Felix Fietkau <nbd@nbd.name>
* Lorenzo Bianconi <lorenzo@kernel.org>
* Sean Wang <sean.wang@mediatek.com>
*/
#include <linux/kernel.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio_func.h>
#include "../trace.h"
#include "mt7615.h"
#include "sdio.h"
#include "mac.h"
static void mt7663s_refill_sched_quota(struct mt7615_dev *dev, u32 *data)
{
struct mt76_sdio *sdio = &dev->mt76.sdio;
mutex_lock(&sdio->sched.lock);
sdio->sched.pse_data_quota += FIELD_GET(TXQ_CNT_L, data[0]) + /* BK */
FIELD_GET(TXQ_CNT_H, data[0]) + /* BE */
FIELD_GET(TXQ_CNT_L, data[1]) + /* VI */
FIELD_GET(TXQ_CNT_H, data[1]); /* VO */
sdio->sched.ple_data_quota += FIELD_GET(TXQ_CNT_H, data[2]) + /* BK */
FIELD_GET(TXQ_CNT_L, data[3]) + /* BE */
FIELD_GET(TXQ_CNT_H, data[3]) + /* VI */
FIELD_GET(TXQ_CNT_L, data[4]); /* VO */
sdio->sched.pse_mcu_quota += FIELD_GET(TXQ_CNT_L, data[2]);
mutex_unlock(&sdio->sched.lock);
}
static struct sk_buff *mt7663s_build_rx_skb(void *data, int data_len,
int buf_len)
{
int len = min_t(int, data_len, MT_SKB_HEAD_LEN);
struct sk_buff *skb;
skb = alloc_skb(len, GFP_KERNEL);
if (!skb)
return NULL;
skb_put_data(skb, data, len);
if (data_len > len) {
struct page *page;
data += len;
page = virt_to_head_page(data);
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
page, data - page_address(page),
data_len - len, buf_len);
get_page(page);
}
return skb;
}
static int mt7663s_rx_run_queue(struct mt7615_dev *dev, enum mt76_rxq_id qid,
struct mt76s_intr *intr)
{
struct mt76_queue *q = &dev->mt76.q_rx[qid];
struct mt76_sdio *sdio = &dev->mt76.sdio;
int len = 0, err, i, order;
struct page *page;
u8 *buf;
for (i = 0; i < intr->rx.num[qid]; i++)
len += round_up(intr->rx.len[qid][i] + 4, 4);
if (!len)
return 0;
if (len > sdio->func->cur_blksize)
len = roundup(len, sdio->func->cur_blksize);
order = get_order(len);
page = __dev_alloc_pages(GFP_KERNEL, order);
if (!page)
return -ENOMEM;
buf = page_address(page);
err = sdio_readsb(sdio->func, buf, MCR_WRDR(qid), len);
if (err < 0) {
dev_err(dev->mt76.dev, "sdio read data failed:%d\n", err);
__free_pages(page, order);
return err;
}
for (i = 0; i < intr->rx.num[qid]; i++) {
int index = (q->tail + i) % q->ndesc;
struct mt76_queue_entry *e = &q->entry[index];
len = intr->rx.len[qid][i];
e->skb = mt7663s_build_rx_skb(buf, len, round_up(len + 4, 4));
if (!e->skb)
break;
buf += round_up(len + 4, 4);
if (q->queued + i + 1 == q->ndesc)
break;
}
__free_pages(page, order);
spin_lock_bh(&q->lock);
q->tail = (q->tail + i) % q->ndesc;
q->queued += i;
spin_unlock_bh(&q->lock);
return err;
}
static int mt7663s_tx_update_sched(struct mt7615_dev *dev,
struct mt76_queue_entry *e,
bool mcu)
{
struct mt76_sdio *sdio = &dev->mt76.sdio;
struct mt76_phy *mphy = &dev->mt76.phy;
struct ieee80211_hdr *hdr;
int size, ret = -EBUSY;
size = DIV_ROUND_UP(e->buf_sz + sdio->sched.deficit, MT_PSE_PAGE_SZ);
if (mcu) {
if (!test_bit(MT76_STATE_MCU_RUNNING, &mphy->state))
return 0;
mutex_lock(&sdio->sched.lock);
if (sdio->sched.pse_mcu_quota > size) {
sdio->sched.pse_mcu_quota -= size;
ret = 0;
}
mutex_unlock(&sdio->sched.lock);
return ret;
}
hdr = (struct ieee80211_hdr *)(e->skb->data + MT_USB_TXD_SIZE);
if (ieee80211_is_ctl(hdr->frame_control))
return 0;
mutex_lock(&sdio->sched.lock);
if (sdio->sched.pse_data_quota > size &&
sdio->sched.ple_data_quota > 0) {
sdio->sched.pse_data_quota -= size;
sdio->sched.ple_data_quota--;
ret = 0;
}
mutex_unlock(&sdio->sched.lock);
return ret;
}
static int mt7663s_tx_run_queue(struct mt7615_dev *dev, struct mt76_queue *q)
{
bool mcu = q == dev->mt76.q_tx[MT_TXQ_MCU].q;
struct mt76_sdio *sdio = &dev->mt76.sdio;
int nframes = 0;
while (q->first != q->tail) {
struct mt76_queue_entry *e = &q->entry[q->first];
int err, len = e->skb->len;
if (mt7663s_tx_update_sched(dev, e, mcu))
break;
if (len > sdio->func->cur_blksize)
len = roundup(len, sdio->func->cur_blksize);
/* TODO: skb_walk_frags and then write to SDIO port */
err = sdio_writesb(sdio->func, MCR_WTDR1, e->skb->data, len);
if (err) {
dev_err(dev->mt76.dev, "sdio write failed: %d\n", err);
return -EIO;
}
e->done = true;
q->first = (q->first + 1) % q->ndesc;
nframes++;
}
return nframes;
}
static int mt7663s_tx_run_queues(struct mt7615_dev *dev)
{
int i, nframes = 0;
for (i = 0; i < MT_TXQ_MCU_WA; i++) {
int ret;
ret = mt7663s_tx_run_queue(dev, dev->mt76.q_tx[i].q);
if (ret < 0)
return ret;
nframes += ret;
}
return nframes;
}
int mt7663s_kthread_run(void *data)
{
struct mt7615_dev *dev = data;
struct mt76_phy *mphy = &dev->mt76.phy;
while (!kthread_should_stop()) {
int ret;
cond_resched();
sdio_claim_host(dev->mt76.sdio.func);
ret = mt7663s_tx_run_queues(dev);
sdio_release_host(dev->mt76.sdio.func);
if (ret <= 0 || !test_bit(MT76_STATE_RUNNING, &mphy->state)) {
set_current_state(TASK_INTERRUPTIBLE);
schedule();
} else {
wake_up_process(dev->mt76.sdio.kthread);
}
}
return 0;
}
void mt7663s_sdio_irq(struct sdio_func *func)
{
struct mt7615_dev *dev = sdio_get_drvdata(func);
struct mt76_sdio *sdio = &dev->mt76.sdio;
struct mt76s_intr intr;
/* disable interrupt */
sdio_writel(func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, 0);
do {
sdio_readsb(func, &intr, MCR_WHISR, sizeof(struct mt76s_intr));
trace_dev_irq(&dev->mt76, intr.isr, 0);
if (!test_bit(MT76_STATE_INITIALIZED, &dev->mt76.phy.state))
goto out;
if (intr.isr & WHIER_RX0_DONE_INT_EN) {
mt7663s_rx_run_queue(dev, 0, &intr);
wake_up_process(sdio->kthread);
}
if (intr.isr & WHIER_RX1_DONE_INT_EN) {
mt7663s_rx_run_queue(dev, 1, &intr);
wake_up_process(sdio->kthread);
}
if (intr.isr & WHIER_TX_DONE_INT_EN) {
mt7663s_refill_sched_quota(dev, intr.tx.wtqcr);
mt7663s_tx_run_queues(dev);
wake_up_process(sdio->kthread);
}
} while (intr.isr);
out:
/* enable interrupt */
sdio_writel(func, WHLPCR_INT_EN_SET, MCR_WHLPCR, 0);
}
// SPDX-License-Identifier: ISC
/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
#include "mt7615.h"
#include "eeprom.h"
#include "mcu.h"
enum {
TM_CHANGED_TXPOWER_CTRL,
TM_CHANGED_TXPOWER,
TM_CHANGED_FREQ_OFFSET,
/* must be last */
NUM_TM_CHANGED
};
static const u8 tm_change_map[] = {
[TM_CHANGED_TXPOWER_CTRL] = MT76_TM_ATTR_TX_POWER_CONTROL,
[TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER,
[TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET,
};
static const u32 reg_backup_list[] = {
MT_WF_PHY_RFINTF3_0(0),
MT_WF_PHY_RFINTF3_0(1),
MT_WF_PHY_RFINTF3_0(2),
MT_WF_PHY_RFINTF3_0(3),
MT_ANT_SWITCH_CON(2),
MT_ANT_SWITCH_CON(3),
MT_ANT_SWITCH_CON(4),
MT_ANT_SWITCH_CON(6),
MT_ANT_SWITCH_CON(7),
MT_ANT_SWITCH_CON(8),
};
static const struct {
u16 wf;
u16 reg;
} rf_backup_list[] = {
{ 0, 0x48 },
{ 1, 0x48 },
{ 2, 0x48 },
{ 3, 0x48 },
};
static int
mt7615_tm_set_tx_power(struct mt7615_phy *phy)
{
struct mt7615_dev *dev = phy->dev;
struct mt76_phy *mphy = phy->mt76;
int i, ret, n_chains = hweight8(mphy->antenna_mask);
struct cfg80211_chan_def *chandef = &mphy->chandef;
int freq = chandef->center_freq1, len, target_chains;
u8 *data, *eep = (u8 *)dev->mt76.eeprom.data;
enum nl80211_band band = chandef->chan->band;
struct sk_buff *skb;
struct {
u8 center_chan;
u8 dbdc_idx;
u8 band;
u8 rsv;
} __packed req_hdr = {
.center_chan = ieee80211_frequency_to_channel(freq),
.band = band,
.dbdc_idx = phy != &dev->phy,
};
u8 *tx_power = NULL;
if (dev->mt76.test.state != MT76_TM_STATE_OFF)
tx_power = dev->mt76.test.tx_power;
len = sizeof(req_hdr) + MT7615_EE_MAX - MT_EE_NIC_CONF_0;
skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(req_hdr) + len);
if (!skb)
return -ENOMEM;
skb_put_data(skb, &req_hdr, sizeof(req_hdr));
data = skb_put_data(skb, eep + MT_EE_NIC_CONF_0, len);
target_chains = mt7615_ext_pa_enabled(dev, band) ? 1 : n_chains;
for (i = 0; i < target_chains; i++) {
int index;
ret = mt7615_eeprom_get_target_power_index(dev, chandef->chan, i);
if (ret < 0)
return -EINVAL;
index = ret - MT_EE_NIC_CONF_0;
if (tx_power && tx_power[i])
data[ret - MT_EE_NIC_CONF_0] = tx_power[i];
}
return __mt76_mcu_skb_send_msg(&dev->mt76, skb,
MCU_EXT_CMD_SET_TX_POWER_CTRL, false);
}
static void
mt7615_tm_reg_backup_restore(struct mt7615_dev *dev)
{
u32 *b = dev->test.reg_backup;
int n_regs = ARRAY_SIZE(reg_backup_list);
int n_rf_regs = ARRAY_SIZE(rf_backup_list);
int i;
if (dev->mt76.test.state == MT76_TM_STATE_OFF) {
for (i = 0; i < n_regs; i++)
mt76_wr(dev, reg_backup_list[i], b[i]);
for (i = 0; i < n_rf_regs; i++)
mt7615_rf_wr(dev, rf_backup_list[i].wf,
rf_backup_list[i].reg, b[n_regs + i]);
return;
}
if (b)
return;
b = devm_kzalloc(dev->mt76.dev, 4 * (n_regs + n_rf_regs),
GFP_KERNEL);
if (!b)
return;
dev->test.reg_backup = b;
for (i = 0; i < n_regs; i++)
b[i] = mt76_rr(dev, reg_backup_list[i]);
for (i = 0; i < n_rf_regs; i++)
b[n_regs + i] = mt7615_rf_rr(dev, rf_backup_list[i].wf,
rf_backup_list[i].reg);
}
static void
mt7615_tm_init_phy(struct mt7615_dev *dev, struct mt7615_phy *phy)
{
unsigned int total_flags = ~0;
if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
return;
mutex_unlock(&dev->mt76.mutex);
mt7615_set_channel(phy);
mt7615_ops.configure_filter(phy->mt76->hw, 0, &total_flags, 0);
mutex_lock(&dev->mt76.mutex);
mt7615_tm_reg_backup_restore(dev);
}
static void
mt7615_tm_init(struct mt7615_dev *dev)
{
mt7615_tm_init_phy(dev, &dev->phy);
if (dev->mt76.phy2)
mt7615_tm_init_phy(dev, dev->mt76.phy2->priv);
}
static void
mt7615_tm_set_rx_enable(struct mt7615_dev *dev, bool en)
{
u32 rqcr_mask = (MT_ARB_RQCR_RX_START |
MT_ARB_RQCR_RXV_START |
MT_ARB_RQCR_RXV_R_EN |
MT_ARB_RQCR_RXV_T_EN) *
(BIT(0) | BIT(MT_ARB_RQCR_BAND_SHIFT));
if (en) {
mt76_clear(dev, MT_ARB_SCR,
MT_ARB_SCR_RX0_DISABLE | MT_ARB_SCR_RX1_DISABLE);
mt76_set(dev, MT_ARB_RQCR, rqcr_mask);
} else {
mt76_set(dev, MT_ARB_SCR,
MT_ARB_SCR_RX0_DISABLE | MT_ARB_SCR_RX1_DISABLE);
mt76_clear(dev, MT_ARB_RQCR, rqcr_mask);
}
}
static void
mt7615_tm_set_tx_antenna(struct mt7615_dev *dev, bool en)
{
struct mt76_testmode_data *td = &dev->mt76.test;
u8 mask = td->tx_antenna_mask;
int i;
if (!mask)
return;
if (!en)
mask = dev->phy.chainmask;
for (i = 0; i < 4; i++) {
mt76_rmw_field(dev, MT_WF_PHY_RFINTF3_0(i),
MT_WF_PHY_RFINTF3_0_ANT,
td->tx_antenna_mask & BIT(i) ? 0 : 0xa);
}
/* 2.4 GHz band */
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(3), MT_ANT_SWITCH_CON_MODE(0),
(td->tx_antenna_mask & BIT(0)) ? 0x8 : 0x1b);
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(4), MT_ANT_SWITCH_CON_MODE(2),
(td->tx_antenna_mask & BIT(1)) ? 0xe : 0x1b);
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(6), MT_ANT_SWITCH_CON_MODE1(0),
(td->tx_antenna_mask & BIT(2)) ? 0x0 : 0xf);
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(7), MT_ANT_SWITCH_CON_MODE1(2),
(td->tx_antenna_mask & BIT(3)) ? 0x6 : 0xf);
/* 5 GHz band */
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(4), MT_ANT_SWITCH_CON_MODE(1),
(td->tx_antenna_mask & BIT(0)) ? 0xd : 0x1b);
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(2), MT_ANT_SWITCH_CON_MODE(3),
(td->tx_antenna_mask & BIT(1)) ? 0x13 : 0x1b);
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(7), MT_ANT_SWITCH_CON_MODE1(1),
(td->tx_antenna_mask & BIT(2)) ? 0x5 : 0xf);
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(8), MT_ANT_SWITCH_CON_MODE1(3),
(td->tx_antenna_mask & BIT(3)) ? 0xb : 0xf);
for (i = 0; i < 4; i++) {
u32 val;
val = mt7615_rf_rr(dev, i, 0x48);
val &= ~(0x3ff << 20);
if (td->tx_antenna_mask & BIT(i))
val |= 3 << 20;
else
val |= (2 << 28) | (2 << 26) | (8 << 20);
mt7615_rf_wr(dev, i, 0x48, val);
}
}
static void
mt7615_tm_set_tx_frames(struct mt7615_dev *dev, bool en)
{
struct ieee80211_tx_info *info;
struct sk_buff *skb = dev->mt76.test.tx_skb;
mt7615_mcu_set_chan_info(&dev->phy, MCU_EXT_CMD_SET_RX_PATH);
mt7615_tm_set_tx_antenna(dev, en);
mt7615_tm_set_rx_enable(dev, !en);
if (!en || !skb)
return;
info = IEEE80211_SKB_CB(skb);
info->control.vif = dev->phy.monitor_vif;
}
static void
mt7615_tm_update_params(struct mt7615_dev *dev, u32 changed)
{
struct mt76_testmode_data *td = &dev->mt76.test;
bool en = dev->mt76.test.state != MT76_TM_STATE_OFF;
if (changed & BIT(TM_CHANGED_TXPOWER_CTRL))
mt7615_mcu_set_test_param(dev, MCU_ATE_SET_TX_POWER_CONTROL,
en, en && td->tx_power_control);
if (changed & BIT(TM_CHANGED_FREQ_OFFSET))
mt7615_mcu_set_test_param(dev, MCU_ATE_SET_FREQ_OFFSET,
en, en ? td->freq_offset : 0);
if (changed & BIT(TM_CHANGED_TXPOWER))
mt7615_tm_set_tx_power(&dev->phy);
}
static int
mt7615_tm_set_state(struct mt76_dev *mdev, enum mt76_testmode_state state)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
struct mt76_testmode_data *td = &mdev->test;
enum mt76_testmode_state prev_state = td->state;
mdev->test.state = state;
if (prev_state == MT76_TM_STATE_TX_FRAMES)
mt7615_tm_set_tx_frames(dev, false);
else if (state == MT76_TM_STATE_TX_FRAMES)
mt7615_tm_set_tx_frames(dev, true);
if (state <= MT76_TM_STATE_IDLE)
mt7615_tm_init(dev);
if ((state == MT76_TM_STATE_IDLE &&
prev_state == MT76_TM_STATE_OFF) ||
(state == MT76_TM_STATE_OFF &&
prev_state == MT76_TM_STATE_IDLE)) {
u32 changed = 0;
int i;
for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
u16 cur = tm_change_map[i];
if (td->param_set[cur / 32] & BIT(cur % 32))
changed |= BIT(i);
}
mt7615_tm_update_params(dev, changed);
}
return 0;
}
static int
mt7615_tm_set_params(struct mt76_dev *mdev, struct nlattr **tb,
enum mt76_testmode_state new_state)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
struct mt76_testmode_data *td = &dev->mt76.test;
u32 changed = 0;
int i;
BUILD_BUG_ON(NUM_TM_CHANGED >= 32);
if (new_state == MT76_TM_STATE_OFF ||
td->state == MT76_TM_STATE_OFF)
return 0;
if (td->tx_antenna_mask & ~dev->phy.chainmask)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
if (tb[tm_change_map[i]])
changed |= BIT(i);
}
mt7615_tm_update_params(dev, changed);
return 0;
}
static int
mt7615_tm_dump_stats(struct mt76_dev *mdev, struct sk_buff *msg)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
void *rx, *rssi;
int i;
rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX);
if (!rx)
return -ENOMEM;
if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, dev->test.last_freq_offset) ||
nla_put_s32(msg, MT76_TM_RX_ATTR_IB_RSSI, dev->test.last_ib_rssi) ||
nla_put_s32(msg, MT76_TM_RX_ATTR_WB_RSSI, dev->test.last_wb_rssi))
return -ENOMEM;
rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI);
if (!rssi)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(dev->test.last_rcpi); i++)
if (nla_put_u8(msg, i, dev->test.last_rcpi[i]))
return -ENOMEM;
nla_nest_end(msg, rssi);
nla_nest_end(msg, rx);
return 0;
}
const struct mt76_testmode_ops mt7615_testmode_ops = {
.set_state = mt7615_tm_set_state,
.set_params = mt7615_tm_set_params,
.dump_stats = mt7615_tm_dump_stats,
};
......@@ -15,31 +15,6 @@
#include "mcu.h"
#include "regs.h"
static const u32 mt7663u_reg_map[] = {
[MT_TOP_CFG_BASE] = 0x80020000,
[MT_HW_BASE] = 0x80000000,
[MT_DMA_SHDL_BASE] = 0x5000a000,
[MT_HIF_BASE] = 0x50000000,
[MT_CSR_BASE] = 0x40000000,
[MT_EFUSE_ADDR_BASE] = 0x78011000,
[MT_TOP_MISC_BASE] = 0x81020000,
[MT_PLE_BASE] = 0x82060000,
[MT_PSE_BASE] = 0x82068000,
[MT_PHY_BASE] = 0x82070000,
[MT_WTBL_BASE_ADDR] = 0x820e0000,
[MT_CFG_BASE] = 0x820f0000,
[MT_AGG_BASE] = 0x820f2000,
[MT_ARB_BASE] = 0x820f3000,
[MT_TMAC_BASE] = 0x820f4000,
[MT_RMAC_BASE] = 0x820f5000,
[MT_DMA_BASE] = 0x820f7000,
[MT_PF_BASE] = 0x820f8000,
[MT_WTBL_BASE_ON] = 0x820f9000,
[MT_WTBL_BASE_OFF] = 0x820f9800,
[MT_LPON_BASE] = 0x820fb000,
[MT_MIB_BASE] = 0x820fd000,
};
static const struct usb_device_id mt7615_device_table[] = {
{ USB_DEVICE_AND_INTERFACE_INFO(0x0e8d, 0x7663, 0xff, 0xff, 0xff) },
{ },
......@@ -64,205 +39,19 @@ static void mt7663u_cleanup(struct mt7615_dev *dev)
mt76u_queues_deinit(&dev->mt76);
}
static void
mt7663u_mac_write_txwi(struct mt7615_dev *dev, struct mt76_wcid *wcid,
enum mt76_txq_id qid, struct ieee80211_sta *sta,
struct sk_buff *skb)
{
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct ieee80211_key_conf *key = info->control.hw_key;
__le32 *txwi;
int pid;
if (!wcid)
wcid = &dev->mt76.global_wcid;
pid = mt76_tx_status_skb_add(&dev->mt76, wcid, skb);
txwi = (__le32 *)(skb->data - MT_USB_TXD_SIZE);
memset(txwi, 0, MT_USB_TXD_SIZE);
mt7615_mac_write_txwi(dev, txwi, skb, wcid, sta, pid, key, false);
skb_push(skb, MT_USB_TXD_SIZE);
}
static int
__mt7663u_mac_set_rates(struct mt7615_dev *dev,
struct mt7615_wtbl_desc *wd)
{
struct mt7615_rate_desc *rate = &wd->rate;
struct mt7615_sta *sta = wd->sta;
u32 w5, w27, addr, val;
lockdep_assert_held(&dev->mt76.mutex);
if (!sta)
return -EINVAL;
if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
return -ETIMEDOUT;
addr = mt7615_mac_wtbl_addr(dev, sta->wcid.idx);
w27 = mt76_rr(dev, addr + 27 * 4);
w27 &= ~MT_WTBL_W27_CC_BW_SEL;
w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rate->bw);
w5 = mt76_rr(dev, addr + 5 * 4);
w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
MT_WTBL_W5_MPDU_OK_COUNT |
MT_WTBL_W5_MPDU_FAIL_COUNT |
MT_WTBL_W5_RATE_IDX);
w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rate->bw) |
FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
rate->bw_idx ? rate->bw_idx - 1 : 7);
mt76_wr(dev, MT_WTBL_RIUCR0, w5);
mt76_wr(dev, MT_WTBL_RIUCR1,
FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rate->probe_val) |
FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rate->val[0]) |
FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rate->val[1]));
mt76_wr(dev, MT_WTBL_RIUCR2,
FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rate->val[1] >> 8) |
FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rate->val[1]) |
FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rate->val[2]) |
FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rate->val[2]));
mt76_wr(dev, MT_WTBL_RIUCR3,
FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rate->val[2] >> 4) |
FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rate->val[3]) |
FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rate->val[3]));
mt76_wr(dev, MT_WTBL_UPDATE,
FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, sta->wcid.idx) |
MT_WTBL_UPDATE_RATE_UPDATE |
MT_WTBL_UPDATE_TX_COUNT_CLEAR);
mt76_wr(dev, addr + 27 * 4, w27);
mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
val = mt76_rr(dev, MT_LPON_UTTR0);
sta->rate_set_tsf = (val & ~BIT(0)) | rate->rateset;
if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
sta->rate_count = 2 * MT7615_RATE_RETRY * sta->n_rates;
sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
return 0;
}
static int
__mt7663u_mac_set_key(struct mt7615_dev *dev,
struct mt7615_wtbl_desc *wd)
{
struct mt7615_key_desc *key = &wd->key;
struct mt7615_sta *sta = wd->sta;
enum mt7615_cipher_type cipher;
struct mt76_wcid *wcid;
int err;
lockdep_assert_held(&dev->mt76.mutex);
if (!sta)
return -EINVAL;
cipher = mt7615_mac_get_cipher(key->cipher);
if (cipher == MT_CIPHER_NONE)
return -EOPNOTSUPP;
wcid = &wd->sta->wcid;
mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, key->cmd);
err = mt7615_mac_wtbl_update_key(dev, wcid, key->key, key->keylen,
cipher, key->cmd);
if (err < 0)
return err;
err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, key->keyidx,
key->cmd);
if (err < 0)
return err;
if (key->cmd == SET_KEY)
wcid->cipher |= BIT(cipher);
else
wcid->cipher &= ~BIT(cipher);
return 0;
}
void mt7663u_wtbl_work(struct work_struct *work)
static void mt7663u_init_work(struct work_struct *work)
{
struct mt7615_wtbl_desc *wd, *wd_next;
struct mt7615_dev *dev;
dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
wtbl_work);
list_for_each_entry_safe(wd, wd_next, &dev->wd_head, node) {
spin_lock_bh(&dev->mt76.lock);
list_del(&wd->node);
spin_unlock_bh(&dev->mt76.lock);
mutex_lock(&dev->mt76.mutex);
switch (wd->type) {
case MT7615_WTBL_RATE_DESC:
__mt7663u_mac_set_rates(dev, wd);
break;
case MT7615_WTBL_KEY_DESC:
__mt7663u_mac_set_key(dev, wd);
break;
}
mutex_unlock(&dev->mt76.mutex);
kfree(wd);
}
}
static void
mt7663u_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
struct mt76_queue_entry *e)
{
skb_pull(e->skb, MT_USB_HDR_SIZE + MT_USB_TXD_SIZE);
mt76_tx_complete_skb(mdev, e->skb);
}
static int
mt7663u_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
enum mt76_txq_id qid, struct mt76_wcid *wcid,
struct ieee80211_sta *sta,
struct mt76_tx_info *tx_info)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
struct mt7615_sta *msta;
msta = container_of(wcid, struct mt7615_sta, wcid);
spin_lock_bh(&dev->mt76.lock);
mt7615_mac_set_rates(&dev->phy, msta, &info->control.rates[0],
msta->rates);
msta->rate_probe = true;
spin_unlock_bh(&dev->mt76.lock);
}
mt7663u_mac_write_txwi(dev, wcid, qid, sta, tx_info->skb);
return mt76u_skb_dma_info(tx_info->skb, tx_info->skb->len);
}
static bool mt7663u_tx_status_data(struct mt76_dev *mdev, u8 *update)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
mutex_lock(&dev->mt76.mutex);
mt7615_mac_sta_poll(dev);
mutex_unlock(&dev->mt76.mutex);
dev = container_of(work, struct mt7615_dev, mcu_work);
if (mt7663u_mcu_init(dev))
return;
return 0;
mt7615_mcu_set_eeprom(dev);
mt7615_mac_init(dev);
mt7615_phy_init(dev);
mt7615_mcu_del_wtbl_all(dev);
mt7615_check_offload_capability(dev);
}
static int mt7663u_probe(struct usb_interface *usb_intf,
......@@ -270,10 +59,10 @@ static int mt7663u_probe(struct usb_interface *usb_intf,
{
static const struct mt76_driver_ops drv_ops = {
.txwi_size = MT_USB_TXD_SIZE,
.drv_flags = MT_DRV_RX_DMA_HDR,
.tx_prepare_skb = mt7663u_tx_prepare_skb,
.tx_complete_skb = mt7663u_tx_complete_skb,
.tx_status_data = mt7663u_tx_status_data,
.drv_flags = MT_DRV_RX_DMA_HDR | MT_DRV_HW_MGMT_TXQ,
.tx_prepare_skb = mt7663_usb_sdio_tx_prepare_skb,
.tx_complete_skb = mt7663_usb_sdio_tx_complete_skb,
.tx_status_data = mt7663_usb_sdio_tx_status_data,
.rx_skb = mt7615_queue_rx_skb,
.sta_ps = mt7615_sta_ps,
.sta_add = mt7615_mac_sta_add,
......@@ -303,7 +92,8 @@ static int mt7663u_probe(struct usb_interface *usb_intf,
usb_set_intfdata(usb_intf, dev);
dev->reg_map = mt7663u_reg_map;
INIT_WORK(&dev->mcu_work, mt7663u_init_work);
dev->reg_map = mt7663_usb_sdio_reg_map;
dev->ops = ops;
ret = mt76u_init(mdev, usb_intf, true);
if (ret < 0)
......@@ -341,7 +131,7 @@ static int mt7663u_probe(struct usb_interface *usb_intf,
if (ret)
goto error;
ret = mt7663u_register_device(dev);
ret = mt7663_usb_sdio_register_device(dev);
if (ret)
goto error_freeq;
......@@ -350,11 +140,10 @@ static int mt7663u_probe(struct usb_interface *usb_intf,
error_freeq:
mt76u_queues_deinit(&dev->mt76);
error:
mt76u_deinit(&dev->mt76);
usb_set_intfdata(usb_intf, NULL);
usb_put_dev(interface_to_usbdev(usb_intf));
ieee80211_free_hw(mdev->hw);
mt76_free_device(&dev->mt76);
return ret;
}
......@@ -372,8 +161,7 @@ static void mt7663u_disconnect(struct usb_interface *usb_intf)
usb_set_intfdata(usb_intf, NULL);
usb_put_dev(interface_to_usbdev(usb_intf));
mt76u_deinit(&dev->mt76);
ieee80211_free_hw(dev->mt76.hw);
mt76_free_device(&dev->mt76);
}
#ifdef CONFIG_PM
......
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2019 MediaTek Inc.
*
* Author: Felix Fietkau <nbd@nbd.name>
* Lorenzo Bianconi <lorenzo@kernel.org>
* Sean Wang <sean.wang@mediatek.com>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include "mt7615.h"
#include "mac.h"
#include "regs.h"
static int mt7663u_dma_sched_init(struct mt7615_dev *dev)
{
int i;
mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
/* disable refill group 5 - group 15 and raise group 2
* and 3 as high priority.
*/
mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffe00006);
mt76_clear(dev, MT_DMA_SHDL(MT_DMASHDL_PAGE), BIT(16));
for (i = 0; i < 5; i++)
mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),
FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x3) |
FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x1ff));
mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);
mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);
mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x4444);
/* group pririority from high to low:
* 15 (cmd groups) > 4 > 3 > 2 > 1 > 0.
*/
mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6501234f);
mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);
mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x7004801c);
mt76_wr(dev, MT_UDMA_WLCFG_1,
FIELD_PREP(MT_WL_TX_TMOUT_LMT, 80000) |
FIELD_PREP(MT_WL_RX_AGG_PKT_LMT, 1));
/* setup UDMA Rx Flush */
mt76_clear(dev, MT_UDMA_WLCFG_0, MT_WL_RX_FLUSH);
/* hif reset */
mt76_set(dev, MT_HIF_RST, MT_HIF_LOGIC_RST_N);
mt76_set(dev, MT_UDMA_WLCFG_0,
MT_WL_RX_AGG_EN | MT_WL_RX_EN | MT_WL_TX_EN |
MT_WL_RX_MPSZ_PAD0 | MT_TICK_1US_EN |
MT_WL_TX_TMOUT_FUNC_EN);
mt76_rmw(dev, MT_UDMA_WLCFG_0, MT_WL_RX_AGG_LMT | MT_WL_RX_AGG_TO,
FIELD_PREP(MT_WL_RX_AGG_LMT, 32) |
FIELD_PREP(MT_WL_RX_AGG_TO, 100));
return 0;
}
static int mt7663u_init_hardware(struct mt7615_dev *dev)
{
int ret, idx;
ret = mt7615_eeprom_init(dev, MT_EFUSE_BASE);
if (ret < 0)
return ret;
ret = mt7663u_dma_sched_init(dev);
if (ret)
return ret;
set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
/* Beacon and mgmt frames should occupy wcid 0 */
idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7615_WTBL_STA - 1);
if (idx)
return -ENOSPC;
dev->mt76.global_wcid.idx = idx;
dev->mt76.global_wcid.hw_key_idx = -1;
rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
return 0;
}
static void mt7663u_init_work(struct work_struct *work)
{
struct mt7615_dev *dev;
dev = container_of(work, struct mt7615_dev, mcu_work);
if (mt7663u_mcu_init(dev))
return;
mt7615_mcu_set_eeprom(dev);
mt7615_mac_init(dev);
mt7615_phy_init(dev);
mt7615_mcu_del_wtbl_all(dev);
mt7615_check_offload_capability(dev);
}
int mt7663u_register_device(struct mt7615_dev *dev)
{
struct ieee80211_hw *hw = mt76_hw(dev);
int err;
INIT_WORK(&dev->wtbl_work, mt7663u_wtbl_work);
INIT_WORK(&dev->mcu_work, mt7663u_init_work);
INIT_LIST_HEAD(&dev->wd_head);
mt7615_init_device(dev);
err = mt7663u_init_hardware(dev);
if (err)
return err;
hw->extra_tx_headroom += MT_USB_HDR_SIZE + MT_USB_TXD_SIZE;
/* check hw sg support in order to enable AMSDU */
hw->max_tx_fragments = dev->mt76.usb.sg_en ? MT_HW_TXP_MAX_BUF_NUM : 1;
err = mt76_register_device(&dev->mt76, true, mt7615_rates,
ARRAY_SIZE(mt7615_rates));
if (err < 0)
return err;
if (!dev->mt76.usb.sg_en) {
struct ieee80211_sta_vht_cap *vht_cap;
/* decrease max A-MSDU size if SG is not supported */
vht_cap = &dev->mphy.sband_5g.sband.vht_cap;
vht_cap->cap &= ~IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
}
ieee80211_queue_work(hw, &dev->mcu_work);
mt7615_init_txpower(dev, &dev->mphy.sband_2g.sband);
mt7615_init_txpower(dev, &dev->mphy.sband_5g.sband);
return mt7615_init_debugfs(dev);
}
......@@ -28,13 +28,13 @@ mt7663u_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
else
ep = MT_EP_OUT_AC_BE;
ret = mt76u_skb_dma_info(skb, skb->len);
put_unaligned_le32(skb->len, skb_push(skb, sizeof(skb->len)));
ret = mt76_skb_adjust_pad(skb);
if (ret < 0)
goto out;
ret = mt76u_bulk_msg(&dev->mt76, skb->data, skb->len, NULL,
1000, ep);
dev_kfree_skb(skb);
if (ret < 0)
goto out;
......@@ -43,6 +43,7 @@ mt7663u_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
out:
mutex_unlock(&mdev->mcu.mutex);
dev_kfree_skb(skb);
return ret;
}
......@@ -60,6 +61,8 @@ int mt7663u_mcu_init(struct mt7615_dev *dev)
dev->mt76.mcu_ops = &mt7663u_mcu_ops,
/* usb does not support runtime-pm */
clear_bit(MT76_STATE_PM, &dev->mphy.state);
mt76_set(dev, MT_UDMA_TX_QSEL, MT_FW_DL_EN);
if (test_and_clear_bit(MT76_STATE_POWER_OFF, &dev->mphy.state)) {
......
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......@@ -80,7 +80,6 @@ struct mt76x02_dev {
struct mutex phy_mutex;
u16 vif_mask;
u16 chainmask;
u8 txdone_seq;
......
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