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Commit 99355a23 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'ti-k3-dt-for-v6.6' of... 

Merge tag 'ti-k3-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt

TI K3 device tree updates for v6.6

New Boards:
 - TQ group's TQMaX4XxL AM64 SOM and MBaX4XxL carrier board
 - TI's AM62P5 Starter Kit (SK)

New features:
AM625:
 - Support for Display (parallel only) - hdmi+audio support for
   AM625-SK/BeaglePlay, TC358778 DPI to MIPI-DSI bridge support
   for verdin.
 - MCU MCAN support and enable of Toradex Verdin
 - Toradex Verdin Dahlia audio support
AM62A7:
 - MCU MCAN support
 - Enable USB Dual Role Device(DRD) support for AM62A7
   Starter Kit(SK).
AM64:
 - TQ group's tqma64xxl: Overlays for SD-card and wlan.
J721E:
 - Main domain CPSW9G and correponding gateway/ethernet
   switch expansion - GESI board.
J721S2/AM68:
 - New CAN instances, ehrpwm, Display (DSS) and am68-sk HDMI support
 - Main domain CPSW2G and correponding gateway/ethernet
   switch expansion - GESI board.
J784S4/AM69:
 - Boot phase tag marking in device tree
 - UFS support

Cleanups and non-urgent fixes:
 - Cosmetic style fixups around "=" and "{" whitespace usage.
 - Fixups across multiple SoCs/boards for pwm-tbclk to matchup with
   bindings
 - Serdes header file include/dt-bindings/mux/ti-serdes.h is now
   deprecated, use k3-serdes.h in soc dtsi folder.
 - All SoCs: Enable GPIO/SDHCI/OSPI/TSADC/C6/C7 DSP nodes at the
   board level.
 - Fixups for AM62: Crypto powerdomains are conditional to better
   represent control of the crypto engines by security controller.
 - Fixups for j721e: Duplicate wakeup_i2c node dropped for SoM board.
 - Fixups for j721s2/am68: pimux offsets for OSPI.
 - Fixups for j784s4/am69: Fixups for pinmux for ospi/adc interrupt
   ranges for wkup/main gpios

* tag 'ti-k3-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (68 commits)
  arm64: dts: ti: verdin-am62: Add DSI display support
  arm64: dts: ti: Add support for the AM62P5 Starter Kit
  arm64: dts: ti: Introduce AM62P5 family of SoCs
  dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
  arm64: dts: ti: k3-am69-sk: Add phase tags marking
  arm64: dts: ti: k3-j784s4-evm: Add phase tags marking
  arm64: dts: ti: k3-j784s4: Add phase tags marking
  arm64: dts: ti: k3-am625-beagleplay: Add HDMI support
  arm64: dts: ti: am62x-sk: Add overlay for HDMI audio
  arm64: dts: ti: k3-am62x-sk-common: Add HDMI support
  arm64: dts: ti: k3-am62-main: Add node for DSS
  arm64: dts: ti: k3-am62x-sk-common: Update main-i2c1 frequency
  arm64: dts: ti: k3-j721e: Enable C6x DSP nodes at the board level
  arm64: dts: ti: k3-j784s4: Enable C7x DSP nodes at the board level
  arm64: dts: ti: k3-j721e: Enable C7x DSP nodes at the board level
  arm64: dts: ti: k3-*: fix fss node dtbs check warnings
  arm64: dts: ti: k3-am64: Enable TSCADC nodes at the board level
  arm64: dts: ti: k3-am65: Enable TSCADC nodes at the board level
  arm64: dts: ti: k3-j721e: Enable TSCADC nodes at the board level
  arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level
  ...

Link: https://lore.kernel.org/r/20230814160651.frxohyshd2evp2k4@expensesSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f0df584f 9e772003
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Showing with 3575 additions and 381 deletions
Documentation/devicetree/bindings/arm/ti/k3.yaml
View file @ 99355a23
......@@ -25,6 +25,12 @@ properties:
- ti,am62a7-sk
- const: ti,am62a7
- description: K3 AM62P5 SoC and Boards
items:
- enum:
- ti,am62p5-sk
- const: ti,am62p5
- description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
items:
- const: phytec,am625-phyboard-lyra-rdk
......@@ -72,6 +78,13 @@ properties:
- const: phytec,am64-phycore-som
- const: ti,am642
- description: K3 AM642 SoC on TQ-Systems TQMaX4XxL SoM
items:
- enum:
- tq,am642-tqma6442l-mbax4xxl # MBaX4XxL base board
- const: tq,am642-tqma6442l
- const: ti,am642
- description: K3 AM654 SoC
items:
- enum:
......
Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml
View file @ 99355a23
......@@ -66,10 +66,22 @@ patternProperties:
required:
- compatible
- reg
- power-domains
- dmas
- dma-names
allOf:
- if:
properties:
compatible:
contains:
const: ti,am62-sa3ul
then:
properties:
power-domains: false
else:
required:
- power-domains
additionalProperties: false
examples:
......
Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml
View file @ 99355a23
......@@ -34,18 +34,22 @@ properties:
- const: ti,am654-navss-ringacc
reg:
minItems: 4
items:
- description: real time registers regions
- description: fifos registers regions
- description: proxy gcfg registers regions
- description: proxy target registers regions
- description: configuration registers region
reg-names:
minItems: 4
items:
- const: rt
- const: fifos
- const: proxy_gcfg
- const: proxy_target
- const: cfg
msi-parent: true
......@@ -80,8 +84,9 @@ examples:
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
<0x0 0x33000000 0x0 0x40000>,
<0x0 0x31080000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <818>;
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
ti,sci = <&dmsc>;
......
arch/arm64/boot/dts/ti/Makefile
View file @ 99355a23
......@@ -19,14 +19,27 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo
# Boards with AM62Ax SoC
dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
# Boards with AM62Px SoC
dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
# Boards with AM64x SoC
dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \
k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
# Boards with AM65x SoC
k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
......@@ -46,15 +59,21 @@ dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb
k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
# Boards with J721s2 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am625-sk += -@
DTC_FLAGS_k3-am62-lp-sk += -@
DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
DTC_FLAGS_k3-j721e-common-proc-board += -@
DTC_FLAGS_k3-j721s2-common-proc-board += -@
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
View file @ 99355a23
......@@ -55,11 +55,29 @@ phy_gmii_sel: phy@4044 {
#phy-cells = <1>;
};
epwm_tbclk: clock@4130 {
compatible = "ti,am62-epwm-tbclk", "syscon";
epwm_tbclk: clock-controller@4130 {
compatible = "ti,am62-epwm-tbclk";
reg = <0x4130 0x4>;
#clock-cells = <1>;
};
audio_refclk0: clock-controller@82e0 {
compatible = "ti,am62-audio-refclk";
reg = <0x82e0 0x4>;
clocks = <&k3_clks 157 0>;
assigned-clocks = <&k3_clks 157 0>;
assigned-clock-parents = <&k3_clks 157 8>;
#clock-cells = <0>;
};
audio_refclk1: clock-controller@82e4 {
compatible = "ti,am62-audio-refclk";
reg = <0x82e4 0x4>;
clocks = <&k3_clks 157 10>;
assigned-clocks = <&k3_clks 157 10>;
assigned-clock-parents = <&k3_clks 157 18>;
#clock-cells = <0>;
};
};
dmss: bus@48000000 {
......@@ -174,7 +192,6 @@ k3_reset: reset-controller {
crypto: crypto@40900000 {
compatible = "ti,am62-sa3ul";
reg = <0x00 0x40900000 0x00 0x1200>;
power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
......@@ -590,7 +607,7 @@ usbss0: dwc3-usb@f900000 {
usb0: usb@31000000 {
compatible = "snps,dwc3";
reg =<0x00 0x31000000 0x00 0x50000>;
reg = <0x00 0x31000000 0x00 0x50000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
......@@ -613,7 +630,7 @@ usbss1: dwc3-usb@f910000 {
usb1: usb@31100000 {
compatible = "snps,dwc3";
reg =<0x00 0x31100000 0x00 0x50000>;
reg = <0x00 0x31100000 0x00 0x50000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
......@@ -718,6 +735,31 @@ cpts@3d000 {
};
};
dss: dss@30200000 {
compatible = "ti,am625-dss";
reg = <0x00 0x30200000 0x00 0x1000>, /* common */
<0x00 0x30202000 0x00 0x1000>, /* vidl1 */
<0x00 0x30206000 0x00 0x1000>, /* vid */
<0x00 0x30207000 0x00 0x1000>, /* ovr1 */
<0x00 0x30208000 0x00 0x1000>, /* ovr2 */
<0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
<0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 6>,
<&dss_vp1_clk>,
<&k3_clks 186 2>;
clock-names = "fck", "vp1", "vp2";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
dss_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
hwspinlock: spinlock@2a000000 {
compatible = "ti,am64-hwspinlock";
reg = <0x00 0x2a000000 0x00 0x1000>;
......
arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
View file @ 99355a23
......@@ -147,4 +147,28 @@ mcu_rti0: watchdog@4880000 {
/* Tightly coupled to M4F */
status = "reserved";
};
mcu_mcan0: can@4e08000 {
compatible = "bosch,m_can";
reg = <0x00 0x4e08000 0x00 0x200>,
<0x00 0x4e00000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
mcu_mcan1: can@4e18000 {
compatible = "bosch,m_can";
reg = <0x00 0x4e18000 0x00 0x200>,
<0x00 0x4e10000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
};
arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi
View file @ 99355a23
......@@ -8,6 +8,43 @@
* https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
*/
/ {
reg_1v8_sw: regulator-1v8-sw {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "On-carrier +V1.8_SW";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,name = "verdin-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Headphone Jack", "MICBIAS",
"IN1L", "Headphone Jack";
simple-audio-card,widgets =
"Microphone", "Headphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
clocks = <&audio_refclk1>;
sound-dai = <&wm8904_1a>;
};
simple-audio-card,cpu {
sound-dai = <&mcasp0>;
};
};
};
/* Verdin ETHs */
&cpsw3g {
status = "okay";
......@@ -46,6 +83,22 @@ &main_gpio0 {
&main_i2c1 {
status = "okay";
/* Audio Codec */
wm8904_1a: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s1_mclk>;
#sound-dai-cells = <0>;
clocks = <&audio_refclk1>;
clock-names = "mclk";
AVDD-supply = <&reg_1v8_sw>;
CPVDD-supply = <&reg_1v8_sw>;
DBVDD-supply = <&reg_1v8_sw>;
DCVDD-supply = <&reg_1v8_sw>;
MICVDD-supply = <&reg_1v8_sw>;
};
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina219";
......@@ -115,6 +168,11 @@ &mcu_i2c0 {
status = "okay";
};
/* Verdin CAN_2 */
&mcu_mcan0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
......
arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
View file @ 99355a23
......@@ -8,6 +8,42 @@
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/ {
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
"Speaker", "LSPK",
"Speaker", "RSPK",
"Line Out", "AUXOUT1",
"Line Out", "AUXOUT2",
"LAUX", "Line In",
"RAUX", "Line In",
"LMICP", "Mic In",
"RMICP", "Mic In";
simple-audio-card,widgets =
"Headphones", "Headphones",
"Line Out", "Line Out",
"Speaker", "Speaker",
"Microphone", "Mic In",
"Line", "Line In";
codec_dai: simple-audio-card,codec {
clocks = <&audio_refclk1>;
sound-dai = <&nau8822_1a>;
};
simple-audio-card,cpu {
sound-dai = <&mcasp0>;
};
};
};
/* Verdin ETHs */
&cpsw3g {
pinctrl-names = "default";
......@@ -65,6 +101,15 @@ &main_gpio0 {
&main_i2c1 {
status = "okay";
/* Audio Codec */
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s1_mclk>;
#sound-dai-cells = <0>;
};
/* IO Expander */
gpio_expander_21: gpio@21 {
compatible = "nxp,pcal6416";
......@@ -144,6 +189,11 @@ &mcu_i2c0 {
status = "okay";
};
/* Verdin CAN_2 */
&mcu_mcan0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
......
arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi
View file @ 99355a23
......@@ -167,6 +167,11 @@ &mcu_i2c0 {
status = "okay";
};
/* Verdin CAN_2 */
&mcu_mcan0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
......
arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
View file @ 99355a23
......@@ -19,6 +19,8 @@ chosen {
};
aliases {
can0 = &main_mcan0;
can1 = &mcu_mcan0;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
i2c0 = &main_i2c0;
......@@ -732,6 +734,14 @@ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */
>;
};
/* Verdin CAN_2 */
pinctrl_mcu_mcan0: mcu-mcan0-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ /* SODIMM 26 */
AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ /* SODIMM 24 */
>;
};
/* Verdin UART_4 - Reserved to Cortex-M4 */
pinctrl_mcu_uart0: mcu-uart0-default-pins {
pinctrl-single,pins = <
......@@ -758,6 +768,11 @@ AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIM
};
};
/* VERDIN I2S_1_MCLK */
&audio_refclk1 {
assigned-clock-rates = <25000000>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1>;
......@@ -800,6 +815,26 @@ cpsw3g_phy0: ethernet-phy@0 {
};
};
&dss {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_parallel_rgb>;
status = "disabled";
};
&dss_ports {
#address-cells = <1>;
#size-cells = <0>;
/* VP2: DPI Output */
port@1 {
reg = <1>;
dpi_out: endpoint {
remote-endpoint = <&rgb_in>;
};
};
};
/* Verdin PWM_1, PWM_2 */
&epwm0 {
pinctrl-names = "default";
......@@ -1036,6 +1071,7 @@ port@0 {
rgb_in: endpoint {
data-lines = <18>;
remote-endpoint = <&dpi_out>;
};
};
......@@ -1238,8 +1274,6 @@ &main_mcan0 {
status = "disabled";
};
/* Verdin CAN_2 - Reserved to Cortex-M4 */
/* Verdin SPI_1 */
&main_spi1 {
pinctrl-names = "default";
......@@ -1333,6 +1367,13 @@ &mcu_gpio0 {
"";
};
/* Verdin CAN_2 */
&mcu_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mcu_mcan0>;
status = "disabled";
};
/* Verdin UART_4 - Cortex-M4 UART */
&mcu_uart0 {
pinctrl-names = "default";
......
arch/arm64/boot/dts/ti/k3-am62.dtsi
View file @ 99355a23
......@@ -102,6 +102,14 @@ cbass_wakeup: bus@b00000 {
};
};
dss_vp1_clk: clock-divider-oldi {
compatible = "fixed-factor-clock";
clocks = <&k3_clks 186 0>;
#clock-cells = <0>;
clock-div = <7>;
clock-mult = <1>;
};
#include "k3-am62-thermal.dtsi"
};
......
arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
View file @ 99355a23
......@@ -14,7 +14,7 @@
#include "k3-am625.dtsi"
/ {
compatible = "beagle,am625-beagleplay", "ti,am625";
compatible = "beagle,am625-beagleplay", "ti,am625";
model = "BeagleBoard.org BeaglePlay";
aliases {
......@@ -192,6 +192,34 @@ usr: button-usr {
};
hdmi0: connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&it66121_out>;
};
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "it66121 HDMI";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&hdmi_dailink_master>;
simple-audio-card,frame-master = <&hdmi_dailink_master>;
hdmi_dailink_master: simple-audio-card,cpu {
sound-dai = <&mcasp1>;
system-clock-direction-out;
};
simple-audio-card,codec {
sound-dai = <&it66121>;
};
};
/* Workaround for errata i2329 - just use mdio bitbang */
mdio0: mdio {
compatible = "virtual,mdio-gpio";
......@@ -422,6 +450,57 @@ pmic_irq_pins_default: pmic-irq-default-pins {
AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */
>;
};
hdmi_gpio_pins_default: hdmi-gpio-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */
AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */
>;
};
mcasp_hdmi_pins_default: mcasp-hdmi-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */
AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */
AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */
AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */
AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */
>;
};
dss0_pins_default: dss0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
>;
};
};
&mcu_pmx0 {
......@@ -432,7 +511,7 @@ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */
>;
};
gbe_pmx_obsclk: gbe-pmx-clk-default {
gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */
>;
......@@ -670,6 +749,42 @@ &main_i2c2 {
pinctrl-0 = <&i2c2_1v8_pins_default>;
clock-frequency = <100000>;
status = "okay";
it66121: bridge-hdmi@4c {
compatible = "ite,it66121";
reg = <0x4c>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_gpio_pins_default>;
vcn33-supply = <&vdd_3v3>;
vcn18-supply = <&buck2_reg>;
vrf12-supply = <&buck3_reg>;
reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>;
interrupt-parent = <&main_gpio0>;
interrupts = <36 IRQ_TYPE_EDGE_FALLING>;
#sound-dai-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
it66121_in: endpoint {
bus-width = <24>;
remote-endpoint = <&dpi1_out>;
};
};
port@1 {
reg = <1>;
it66121_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&main_i2c3 {
......@@ -756,3 +871,38 @@ &main_uart6 {
pinctrl-0 = <&wifi_debug_uart_pins_default>;
status = "okay";
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss0_pins_default>;
};
&dss_ports {
/* VP2: DPI Output */
port@1 {
reg = <1>;
dpi1_out: endpoint {
remote-endpoint = <&it66121_in>;
};
};
};
&mcasp1 {
status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcasp_hdmi_pins_default>;
auxclk-fs-ratio = <2177>;
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
arch/arm64/boot/dts/ti/k3-am625-sk.dts
View file @ 99355a23
......@@ -212,7 +212,7 @@ &ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0{
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
......
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
View file @ 99355a23
......@@ -56,7 +56,7 @@ phy_gmii_sel: phy@4044 {
};
epwm_tbclk: clock-controller@4130 {
compatible = "ti,am62-epwm-tbclk", "syscon";
compatible = "ti,am62-epwm-tbclk";
reg = <0x4130 0x4>;
#clock-cells = <1>;
};
......@@ -150,8 +150,8 @@ dmsc: system-controller@44043000 {
reg-names = "debug_messages";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
mboxes = <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
......@@ -527,7 +527,7 @@ usbss0: dwc3-usb@f900000 {
usb0: usb@31000000 {
compatible = "snps,dwc3";
reg =<0x00 0x31000000 0x00 0x50000>;
reg = <0x00 0x31000000 0x00 0x50000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
......@@ -550,7 +550,7 @@ usbss1: dwc3-usb@f910000 {
usb1: usb@31100000 {
compatible = "snps,dwc3";
reg =<0x00 0x31100000 0x00 0x50000>;
reg = <0x00 0x31100000 0x00 0x50000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
interrupt-names = "host", "peripheral";
......
arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
View file @ 99355a23
......@@ -143,4 +143,28 @@ mcu_rti0: watchdog@4880000 {
/* Tightly coupled to M4F */
status = "reserved";
};
mcu_mcan0: can@4e08000 {
compatible = "bosch,m_can";
reg = <0x00 0x4e08000 0x00 0x200>,
<0x00 0x4e00000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
mcu_mcan1: can@4e18000 {
compatible = "bosch,m_can";
reg = <0x00 0x4e18000 0x00 0x200>,
<0x00 0x4e10000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
};
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
View file @ 99355a23
......@@ -13,7 +13,7 @@
#include "k3-am62a7.dtsi"
/ {
compatible = "ti,am62a7-sk", "ti,am62a7";
compatible = "ti,am62a7-sk", "ti,am62a7";
model = "Texas Instruments AM62A7 SK";
aliases {
......@@ -226,6 +226,24 @@ &main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
typec_pd0: usb-power-controller@3f {
compatible = "ti,tps6598x";
reg = <0x3f>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
self-powered;
data-role = "dual";
power-role = "sink";
port {
usb_con_hs: endpoint {
remote-endpoint = <&usb0_hs_ep>;
};
};
};
};
};
&main_i2c1 {
......@@ -290,6 +308,21 @@ &main_uart1 {
status = "reserved";
};
&usbss0 {
status = "okay";
ti,vbus-divider;
};
&usb0 {
usb-role-switch;
port {
usb0_hs_ep: endpoint {
remote-endpoint = <&usb_con_hs>;
};
};
};
&usbss1 {
status = "okay";
};
......
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for the AM62P main domain peripherals
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x00 0x70000000 0x00 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x70000000 0x10000>;
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
dmss: bus@48000000 {
bootph-all;
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x4d000000 0x00 0x80000>,
<0x00 0x4a600000 0x00 0x80000>,
<0x00 0x4a400000 0x00 0x80000>;
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
};
dmsc: system-controller@44043000 {
bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes = <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
main_pmx0: pinctrl@f4000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_timer0: timer@2400000 {
bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 36 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 36 2>;
assigned-clock-parents = <&k3_clks 36 3>;
power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
status = "disabled";
};
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
status = "disabled";
};
};
arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for the AM62P MCU domain peripherals
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
};
arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for the AM62P wakeup domain peripherals
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
wkup_conf: bus@43000000 {
bootph-all;
compatible = "simple-bus";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
bootph-all;
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
wkup_uart0: serial@2b300000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x2b300000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fclk";
status = "disabled";
};
};
arch/arm64/boot/dts/ti/k3-am62p.dtsi 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM62P SoC Family
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 AM62P5 SoC";
compatible = "ti,am62p5";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a53_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@f0000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
/* MCU Domain Range */
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
/* Wakeup Domain Range */
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
cbass_mcu: bus@4000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
};
cbass_wakeup: bus@b00000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
};
/* Now include peripherals for each bus segment */
#include "k3-am62p-main.dtsi"
#include "k3-am62p-mcu.dtsi"
#include "k3-am62p-wakeup.dtsi"
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for the AM62P5-SK
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*
* Schematics: https://www.ti.com/lit/zip/sprr487
*/
/dts-v1/;
#include "k3-am62p5.dtsi"
/ {
compatible = "ti,am62p5-sk", "ti,am62p5";
model = "Texas Instruments AM62P5 SK";
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
};
chosen {
stdout-path = &main_uart0;
};
memory@80000000 {
/* 8G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000001 0x80000000>;
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
no-map;
};
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
no-map;
};
wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9c900000 0x00 0x01e00000>;
no-map;
};
};
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */
AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */
AM62PX_IOPAD(0x198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2 */
AM62PX_IOPAD(0x1ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR */
AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR */
>;
};
};
&main_uart0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
/* Main UART1 is used by TIFS firmware */
status = "reserved";
};
&cbass_mcu {
bootph-all;
};
&mcu_pmx0 {
bootph-all;
wkup_uart0_pins_default: wkup-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */
AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */
AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */
AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */
>;
};
};
&wkup_uart0 {
/* WKUP UART0 is used by DM firmware */
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "reserved";
};
arch/arm64/boot/dts/ti/k3-am62p5.dtsi 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for the AM62P5 SoC family (quad core)
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*
* TRM: https://www.ti.com/lit/pdf/spruj83
*/
/dts-v1/;
#include "k3-am62p.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
clocks = <&k3_clks 135 0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
clocks = <&k3_clks 136 0>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x002>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
clocks = <&k3_clks 137 0>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x003>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
clocks = <&k3_clks 138 0>;
};
};
l2_0: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};
arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
View file @ 99355a23
......@@ -114,6 +114,17 @@ sound_master: simple-audio-card,codec {
clocks = <&tlv320_mclk>;
};
};
hdmi0: connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&sii9022_out>;
};
};
};
};
&main_pmx0 {
......@@ -226,6 +237,39 @@ AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */
AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
>;
};
main_dss0_pins_default: main-dss0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
>;
};
};
&mcu_pmx0 {
......@@ -300,7 +344,7 @@ &main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
clock-frequency = <100000>;
tlv320aic3106: audio-codec@1b {
#sound-dai-cells = <0>;
......@@ -313,6 +357,36 @@ tlv320aic3106: audio-codec@1b {
IOVDD-supply = <&vcc_3v3_sys>;
DRVDD-supply = <&vcc_3v3_sys>;
};
sii9022: bridge-hdmi@3b {
compatible = "sil,sii9022";
reg = <0x3b>;
interrupt-parent = <&exp1>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = < 0 >;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in: endpoint {
remote-endpoint = <&dpi1_out>;
};
};
port@1 {
reg = <1>;
sii9022_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&sdhci0 {
......@@ -410,3 +484,20 @@ &mcasp1 {
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_dss0_pins_default>;
};
&dss_ports {
/* VP2: DPI Output */
port@1 {
reg = <1>;
dpi1_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
};
arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/**
* Audio playback via HDMI for AM625-SK and AM62-LP SK.
*
* Links:
* AM625 SK: https://www.ti.com/tool/SK-AM62
* AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP
*
* Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
/plugin/;
&{/} {
hdmi_audio: sound-sii9022 {
compatible = "simple-audio-card";
simple-audio-card,name = "AM62x-Sil9022-HDMI";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&hdmi_dailink_master>;
simple-audio-card,frame-master = <&hdmi_dailink_master>;
hdmi_dailink_master: simple-audio-card,cpu {
sound-dai = <&mcasp1>;
system-clock-direction-out;
};
simple-audio-card,codec {
sound-dai = <&sii9022>;
};
};
};
&mcasp1 {
auxclk-fs-ratio = <2177>;
};
&codec_audio {
status = "disabled";
};
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
View file @ 99355a23
......@@ -44,11 +44,28 @@ main_conf: syscon@43000000 {
#size-cells = <1>;
ranges = <0x0 0x0 0x43000000 0x20000>;
chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x00000014 0x4>;
};
serdes_ln_ctrl: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
};
phy_gmii_sel: phy@4044 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4044 0x8>;
#phy-cells = <1>;
};
epwm_tbclk: clock-controller@4140 {
compatible = "ti,am64-epwm-tbclk";
reg = <0x4130 0x4>;
#clock-cells = <1>;
};
};
gic500: interrupt-controller@1800000 {
......@@ -203,31 +220,6 @@ main_pmx0: pinctrl@f4000 {
pinctrl-single,function-mask = <0xffffffff>;
};
main_conf: syscon@43000000 {
compatible = "syscon", "simple-mfd";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x43000000 0x20000>;
chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x00000014 0x4>;
};
phy_gmii_sel: phy@4044 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4044 0x8>;
#phy-cells = <1>;
};
epwm_tbclk: clock@4140 {
compatible = "ti,am64-epwm-tbclk", "syscon";
reg = <0x4130 0x4>;
#clock-cells = <1>;
};
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
......@@ -733,7 +725,7 @@ timesync_router: pinctrl@a40000 {
pinctrl-single,function-mask = <0x000107ff>;
};
usbss0: cdns-usb@f900000{
usbss0: cdns-usb@f900000 {
compatible = "ti,am64-usb";
reg = <0x00 0xf900000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
......@@ -744,7 +736,7 @@ usbss0: cdns-usb@f900000{
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb0: usb@f400000{
usb0: usb@f400000 {
compatible = "cdns,usb3";
reg = <0x00 0xf400000 0x00 0x10000>,
<0x00 0xf410000 0x00 0x10000>,
......@@ -773,6 +765,7 @@ tscadc0: tscadc@28001000 {
assigned-clock-parents = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
clock-names = "fck";
status = "disabled";
adc {
#io-channel-cells = <1>;
......@@ -802,6 +795,7 @@ ospi0: spi@fc40000 {
assigned-clock-parents = <&k3_clks 75 7>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
};
......
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
View file @ 99355a23
......@@ -181,6 +181,7 @@ i2c_som_rtc: rtc@52 {
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
......
arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
*/
/dts-v1/;
/plugin/;
&sdhci1 {
vmmc-supply = <&reg_sd>;
no-sdio;
status = "okay";
};
&main_gpio0 {
line43-hog {
gpio-hog;
gpios = <43 0>;
line-name = "MMC1_CTRL";
output-low;
};
};
arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
*/
/dts-v1/;
/plugin/;
&sdhci1 {
mmc-pwrseq = <&wifi_pwrseq>;
no-sd;
status = "okay";
};
&main_gpio0 {
line43-hog {
gpio-hog;
gpios = <43 0>;
line-name = "MMC1_CTRL";
output-high;
};
};
arch/arm64/boot/dts/ti/k3-am642-evm.dts
View file @ 99355a23
......@@ -6,12 +6,13 @@
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
#include "k3-serdes.h"
/ {
compatible = "ti,am642-evm", "ti,am642";
model = "Texas Instruments AM642 EVM";
......@@ -519,6 +520,7 @@ &tscadc0 {
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
......
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
View file @ 99355a23
......@@ -16,11 +16,12 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include "k3-am642.dtsi"
#include "k3-am64-phycore-som.dtsi"
#include "k3-serdes.h"
/ {
compatible = "phytec,am642-phyboard-electra-rdk",
"phytec,am64-phycore-som", "ti,am642";
......
arch/arm64/boot/dts/ti/k3-am642-sk.dts
View file @ 99355a23
......@@ -5,13 +5,14 @@
/dts-v1/;
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/leds/common.h>
#include "k3-am642.dtsi"
#include "k3-serdes.h"
/ {
compatible = "ti,am642-sk", "ti,am642";
model = "Texas Instruments AM642 SK";
......@@ -512,11 +513,8 @@ cpsw3g_phy1: ethernet-phy@1 {
};
};
&tscadc0 {
status = "disabled";
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
......
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts 0 → 100644
View file @ 99355a23
This diff is collapsed.
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
*/
#include "k3-am642.dtsi"
/ {
aliases {
i2c0 = &main_i2c0;
mmc0 = &sdhci0;
spi0 = &ospi0;
};
memory@80000000 {
device_type = "memory";
/* 1G RAM - default variant */
reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins>;
clock-frequency = <400000>;
status = "okay";
tmp1075: temperature-sensor@4a {
compatible = "ti,tmp1075";
reg = <0x4a>;
};
eeprom0: eeprom@50 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
read-only;
};
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <12500>;
};
eeprom1: eeprom@54 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
};
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster6 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <84000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Filled by bootloader */
};
};
};
&sdhci0 {
non-removable;
disable-wp;
no-sdio;
no-sd;
ti,driver-strength-ohm = <50>;
};
&main_pmx0 {
main_i2c0_pins: main-i2c0-pins {
pinctrl-single,pins = <
/* (A18) I2C0_SCL */
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0)
/* (B18) I2C0_SDA */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0)
>;
};
ospi0_pins: ospi0-pins {
pinctrl-single,pins = <
/* (N20) OSPI0_CLK */
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0)
/* (L19) OSPI0_CSn0 */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0)
/* (M19) OSPI0_D0 */
AM64X_IOPAD(0x000c, PIN_INPUT, 0)
/* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0)
/* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0)
/* (M21) OSPI0_D3 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0)
/* (P21) OSPI0_D4 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0)
/* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0)
/* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0)
/* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0)
/* (N19) OSPI0_DQS */
AM64X_IOPAD(0x0008, PIN_INPUT, 0)
>;
};
};
arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi
View file @ 99355a23
......@@ -10,7 +10,7 @@
*/
&main_pmx0 {
cp2102n_reset_pin_default: cp2102n-reset-pin-default {
cp2102n_reset_pin_default: cp2102n-reset-default-pins {
pinctrl-single,pins = <
/* (AF12) GPIO1_24, used as cp2102 reset */
AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
......
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
View file @ 99355a23
......@@ -582,17 +582,15 @@ &mcu_spi0 {
ti,pindir-d0-out-d1-in;
};
&tscadc0 {
status = "disabled";
};
&tscadc1 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5>;
};
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
......
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
View file @ 99355a23
......@@ -502,8 +502,8 @@ dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
reg = <0x000041e0 0x14>;
};
ehrpwm_tbclk: clock@4140 {
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
ehrpwm_tbclk: clock-controller@4140 {
compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
......@@ -773,11 +773,12 @@ mailbox0_cluster11: mailbox@31f8b000 {
ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>,
<0x0 0x31080000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <818>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
......@@ -787,9 +788,9 @@ ringacc: ringacc@3c000000 {
main_udmap: dma-controller@31150000 {
compatible = "ti,am654-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>;
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
......@@ -1006,13 +1007,13 @@ csi2_0: port@0 {
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
......
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
View file @ 99355a23
......@@ -112,6 +112,7 @@ tscadc0: tscadc@40200000 {
dmas = <&mcu_udmap 0x7100>,
<&mcu_udmap 0x7101 >;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
......@@ -130,6 +131,7 @@ tscadc1: tscadc@40210000 {
dmas = <&mcu_udmap 0x7102>,
<&mcu_udmap 0x7103>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
......@@ -194,11 +196,13 @@ mcu_navss: bus@28380000 {
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg",
"proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
......@@ -208,9 +212,9 @@ mcu_ringacc: ringacc@2b800000 {
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,am654-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
......@@ -274,7 +278,7 @@ m_can1: can@40568000 {
status = "disabled";
};
fss: fss@47000000 {
fss: bus@47000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
......@@ -295,6 +299,7 @@ ospi0: spi@47040000 {
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ospi1: spi@47050000 {
......@@ -309,6 +314,7 @@ ospi1: spi@47050000 {
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
......
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
View file @ 99355a23
......@@ -192,7 +192,7 @@ AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
>;
};
wkup_pca554_default: wkup-pca554-default {
wkup_pca554_default: wkup-pca554-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
>;
......@@ -478,12 +478,14 @@ &usb0_phy {
};
&tscadc0 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
......@@ -530,6 +532,7 @@ &mcu_r5fss0_core1 {
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
......
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
View file @ 99355a23
......@@ -33,7 +33,7 @@ AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
};
main_bkey_pcie_reset: main-bkey-pcie-reset {
main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
>;
......@@ -46,7 +46,7 @@ AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
>;
};
main_m2_pcie_mux_control: main-m2-pcie-mux-control {
main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
......
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
View file @ 99355a23
......@@ -11,7 +11,8 @@
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include "k3-serdes.h"
/ {
compatible = "ti,am68-sk", "ti,j721s2";
......@@ -121,6 +122,52 @@ transceiver4: can-phy3 {
#phy-cells = <0>;
max-bitrate = <5000000>;
};
connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_hpd_pins_default>;
ddc-i2c-bus = <&mcu_i2c1>;
/* HDMI_HPD */
hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
bridge-dvi {
compatible = "ti,tfp410";
/* HDMI_PDn */
powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>;
ti,deskew = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&dpi_out0>;
pclk-sample = <1>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&main_pmx0 {
......@@ -201,6 +248,45 @@ J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
>;
};
dss_vout0_pins_default: dss-vout0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */
J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */
J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */
J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */
J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */
J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */
J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */
J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */
J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */
J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */
J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */
J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */
J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */
J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */
J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */
J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */
J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */
J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */
J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */
J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */
J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */
J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */
J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */
J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */
J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */
J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */
J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */
J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */
>;
};
hdmi_hpd_pins_default: hdmi-hpd-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */
>;
};
};
&wkup_pmx2 {
......@@ -272,7 +358,7 @@ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default {
mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
......@@ -288,7 +374,7 @@ J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
};
&wkup_pmx3 {
mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default {
mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
>;
......@@ -296,31 +382,17 @@ J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
};
&main_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
&main_gpio2 {
status = "disabled";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
};
&wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
};
&wkup_gpio1 {
status = "disabled";
};
&wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
......@@ -372,13 +444,26 @@ &mcu_i2c0 {
clock-frequency = <400000>;
};
&main_sdhci0 {
/* Unused */
status = "disabled";
&mcu_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c1_pins_default>;
/* i2c1 is used for DVI DDC, so we need to use 100kHz */
clock-frequency = <100000>;
exp2: gpio@20 {
compatible = "ti,tca6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "HDMI_PDn","HDMI_LS_OE",
"DP0_3V3_EN","eDP_ENABLE";
};
};
&main_sdhci1 {
/* SD card */
status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
disable-wp;
......@@ -432,3 +517,39 @@ &main_mcan7 {
pinctrl-0 = <&main_mcan7_pins_default>;
phys = <&transceiver4>;
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_vout0_pins_default>;
/*
* These clock assignments are chosen to enable the following outputs:
*
* VP0 - DisplayPort SST
* VP1 - DPI0
* VP2 - DSI
* VP3 - DPI1
*/
assigned-clocks = <&k3_clks 158 2>,
<&k3_clks 158 5>,
<&k3_clks 158 14>,
<&k3_clks 158 18>;
assigned-clock-parents = <&k3_clks 158 3>,
<&k3_clks 158 7>,
<&k3_clks 158 16>,
<&k3_clks 158 22>;
};
&dss_ports {
#address-cells = <1>;
#size-cells = <0>;
/* HDMI */
port@1 {
reg = <1>;
dpi_out0: endpoint {
remote-endpoint = <&tfp410_in>;
};
};
};
arch/arm64/boot/dts/ti/k3-am69-sk.dts
View file @ 99355a23
......@@ -110,7 +110,9 @@ vdd_sd_dv: regulator-tlv71033 {
};
&main_pmx0 {
bootph-all;
main_uart8_pins_default: main-uart8-default-pins {
bootph-all;
pinctrl-single,pins = <
J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
......@@ -125,6 +127,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
};
main_mmc1_pins_default: main-mmc1-default-pins {
bootph-all;
pinctrl-single,pins = <
J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
......@@ -164,7 +167,9 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
};
&wkup_pmx2 {
bootph-all;
wkup_uart0_pins_default: wkup-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
......@@ -174,6 +179,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
bootph-all;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
......@@ -181,6 +187,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
......@@ -249,6 +256,7 @@ &wkup_uart0 {
};
&wkup_i2c0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
......@@ -268,6 +276,7 @@ &wkup_gpio0 {
};
&mcu_uart0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
......@@ -281,6 +290,7 @@ &mcu_i2c0 {
};
&main_uart8 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
......@@ -307,6 +317,7 @@ exp1: gpio@21 {
};
&main_sdhci0 {
bootph-all;
/* eMMC */
status = "okay";
non-removable;
......@@ -315,6 +326,7 @@ &main_sdhci0 {
};
&main_sdhci1 {
bootph-all;
/* SD card */
status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
......
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View file @ 99355a23
......@@ -8,9 +8,10 @@
#include "k3-j7200-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include "k3-serdes.h"
/ {
compatible = "ti,j7200-evm", "ti,j7200";
model = "Texas Instruments J7200 EVM";
......@@ -239,27 +240,16 @@ &main_uart3 {
pinctrl-0 = <&main_uart3_pins_default>;
};
&main_gpio2 {
status = "disabled";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
&main_gpio0 {
status = "okay";
};
&wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&wkup_gpio1 {
status = "disabled";
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
......@@ -325,6 +315,7 @@ exp3: gpio@20 {
&main_sdhci0 {
/* eMMC */
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
......@@ -332,6 +323,7 @@ &main_sdhci0 {
&main_sdhci1 {
/* SD card */
status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
vmmc-supply = <&vdd_mmc1>;
......
arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
View file @ 99355a23
......@@ -10,9 +10,9 @@
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mux/ti-serdes.h>
#include "k3-pinctrl.h"
#include "k3-serdes.h"
&{/} {
aliases {
......
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
View file @ 99355a23
......@@ -264,11 +264,12 @@ mailbox0_cluster11: mailbox@31f8b000 {
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x3c000000 0x00 0x400000>,
<0x00 0x38000000 0x00 0x400000>,
<0x00 0x31120000 0x00 0x100>,
<0x00 0x33000000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
reg = <0x00 0x3c000000 0x00 0x400000>,
<0x00 0x38000000 0x00 0x400000>,
<0x00 0x31120000 0x00 0x100>,
<0x00 0x33000000 0x00 0x40000>,
<0x00 0x31080000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
......@@ -278,9 +279,9 @@ main_ringacc: ringacc@3c000000 {
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
reg = <0x00 0x31150000 0x00 0x100>,
<0x00 0x34000000 0x00 0x100000>,
<0x00 0x35000000 0x00 0x100000>;
reg = <0x00 0x31150000 0x00 0x100>,
<0x00 0x34000000 0x00 0x100000>,
<0x00 0x35000000 0x00 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
......@@ -654,6 +655,7 @@ main_sdhci0: mmc@4f80000 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
status = "disabled";
};
main_sdhci1: mmc@4fb0000 {
......@@ -677,6 +679,7 @@ main_sdhci1: mmc@4fb0000 {
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
status = "disabled";
};
serdes_wiz0: wiz@5060000 {
......@@ -830,6 +833,7 @@ main_gpio0: gpio@600000 {
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio2: gpio@610000 {
......@@ -847,6 +851,7 @@ main_gpio2: gpio@610000 {
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio4: gpio@620000 {
......@@ -864,6 +869,7 @@ main_gpio4: gpio@620000 {
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 109 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio6: gpio@630000 {
......@@ -881,6 +887,7 @@ main_gpio6: gpio@630000 {
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
status = "disabled";
};
main_spi0: spi@2100000 {
......
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
View file @ 99355a23
......@@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 {
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
status = "disabled";
};
wkup_gpio1: gpio@42100000 {
......@@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 {
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
status = "disabled";
};
mcu_navss: bus@28380000 {
......@@ -326,11 +328,13 @@ mcu_navss: bus@28380000 {
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x2b800000 0x00 0x400000>,
<0x00 0x2b000000 0x00 0x400000>,
<0x00 0x28590000 0x00 0x100>,
<0x00 0x2a500000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
reg = <0x00 0x2b800000 0x00 0x400000>,
<0x00 0x2b000000 0x00 0x400000>,
<0x00 0x28590000 0x00 0x100>,
<0x00 0x2a500000 0x00 0x40000>,
<0x00 0x28440000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg",
"proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
......@@ -340,9 +344,9 @@ mcu_ringacc: ringacc@2b800000 {
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
<0x00 0x2aa00000 0x00 0x40000>;
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
<0x00 0x2aa00000 0x00 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
......@@ -544,6 +548,7 @@ ospi0: spi@47040000 {
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
......
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
View file @ 99355a23
......@@ -267,6 +267,7 @@ eeprom@50 {
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
......
arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
View file @ 99355a23
......@@ -563,6 +563,7 @@ &main_uart0 {
&main_sdhci0 {
/* eMMC */
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
......@@ -570,6 +571,7 @@ &main_sdhci0 {
&main_sdhci1 {
/* SD Card */
status = "okay";
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
......@@ -578,21 +580,6 @@ &main_sdhci1 {
disable-wp;
};
&main_sdhci2 {
/* Unused */
status = "disabled";
};
&ospi0 {
/* Unused */
status = "disabled";
};
&ospi1 {
/* Unused */
status = "disabled";
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
......@@ -660,52 +647,23 @@ eeprom@50 {
};
};
&main_gpio2 {
/* Unused */
status = "disabled";
};
&main_gpio3 {
/* Unused */
status = "disabled";
};
&main_gpio4 {
/* Unused */
status = "disabled";
};
&main_gpio5 {
/* Unused */
status = "disabled";
};
&main_gpio6 {
/* Unused */
status = "disabled";
};
&main_gpio7 {
/* Unused */
status = "disabled";
};
&wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
<&mikro_bus_pins_default>;
};
&wkup_gpio1 {
/* Unused */
status = "disabled";
};
&main_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>;
};
&main_gpio1 {
status = "okay";
};
&usb_serdes_mux {
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
};
......@@ -789,6 +747,7 @@ &usb1 {
};
&tscadc0 {
status = "okay";
/* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
adc {
ti,adc-channels = <0 1 2 3 4 5 6>;
......@@ -796,6 +755,7 @@ adc {
};
&tscadc1 {
status = "okay";
/* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
adc {
ti,adc-channels = <0>;
......@@ -1012,18 +972,21 @@ &main_r5fss1_core1 {
};
&c66_0 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
......
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
View file @ 99355a23
......@@ -469,41 +469,23 @@ &main_uart4 {
pinctrl-0 = <&main_uart4_pins_default>;
};
&main_gpio2 {
status = "disabled";
};
&main_gpio3 {
status = "disabled";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio5 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
};
&main_gpio7 {
status = "disabled";
};
&wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&wkup_gpio1 {
status = "disabled";
&main_gpio0 {
status = "okay";
};
&main_gpio1 {
status = "okay";
};
&main_sdhci0 {
/* eMMC */
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
......@@ -511,6 +493,7 @@ &main_sdhci0 {
&main_sdhci1 {
/* SD/MMC */
status = "okay";
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
......@@ -519,11 +502,6 @@ &main_sdhci1 {
disable-wp;
};
&main_sdhci2 {
/* Unused */
status = "disabled";
};
&usb_serdes_mux {
idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
};
......@@ -641,12 +619,14 @@ partition@3fe0000 {
};
&tscadc0 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
......
arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/**
* DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with
* J721E board.
*
* GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-pinctrl.h"
&{/} {
aliases {
ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
};
};
&cpsw0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_default_pins
&rgmii2_default_pins
&rgmii3_default_pins
&rgmii4_default_pins>;
};
&cpsw0_port1 {
status = "okay";
phy-handle = <&cpsw9g_phy12>;
phy-mode = "rgmii-rxid";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 1>;
};
&cpsw0_port2 {
status = "okay";
phy-handle = <&cpsw9g_phy15>;
phy-mode = "rgmii-rxid";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 2>;
};
&cpsw0_port3 {
status = "okay";
phy-handle = <&cpsw9g_phy0>;
phy-mode = "rgmii-rxid";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 3>;
};
&cpsw0_port4 {
status = "okay";
phy-handle = <&cpsw9g_phy3>;
phy-mode = "rgmii-rxid";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 4>;
};
&cpsw9g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_default_pins>;
bus_freq = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
cpsw9g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
cpsw9g_phy3: ethernet-phy@3 {
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
cpsw9g_phy12: ethernet-phy@12 {
reg = <12>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
cpsw9g_phy15: ethernet-phy@15 {
reg = <15>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&exp1 {
p15-hog {
/* P15 - EXP_MUX2 */
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "EXP_MUX2";
};
p16-hog {
/* P16 - EXP_MUX3 */
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "EXP_MUX3";
};
};
&main_pmx0 {
mdio0_default_pins: mdio0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
>;
};
rgmii1_default_pins: rgmii1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */
J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */
J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */
J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */
J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */
J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */
J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */
J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */
J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */
J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */
J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */
J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */
>;
};
rgmii2_default_pins: rgmii2-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x58, PIN_INPUT, 4) /* (AE22) PRG1_PRU1_GPO0.RGMII2_RD0 */
J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (AG23) PRG1_PRU1_GPO1.RGMII2_RD1 */
J721E_IOPAD(0x60, PIN_INPUT, 4) /* (AF23) PRG1_PRU1_GPO2.RGMII2_RD2 */
J721E_IOPAD(0x64, PIN_INPUT, 4) /* (AD23) PRG1_PRU1_GPO3.RGMII2_RD3 */
J721E_IOPAD(0x70, PIN_INPUT, 4) /* (AE23) PRG1_PRU1_GPO6.RGMII2_RXC */
J721E_IOPAD(0x68, PIN_INPUT, 4) /* (AH24) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
J721E_IOPAD(0x84, PIN_OUTPUT, 4) /* (AJ25) PRG1_PRU1_GPO11.RGMII2_TD0 */
J721E_IOPAD(0x88, PIN_OUTPUT, 4) /* (AH25) PRG1_PRU1_GPO12.RGMII2_TD1 */
J721E_IOPAD(0x8c, PIN_OUTPUT, 4) /* (AG25) PRG1_PRU1_GPO13.RGMII2_TD2 */
J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (AH26) PRG1_PRU1_GPO14.RGMII2_TD3 */
J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (AJ26) PRG1_PRU1_GPO16.RGMII2_TXC */
J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (AJ27) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
rgmii3_default_pins: rgmii3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xb0, PIN_INPUT, 4) /* (AF28) PRG0_PRU0_GPO0.RGMII3_RD0 */
J721E_IOPAD(0xb4, PIN_INPUT, 4) /* (AE28) PRG0_PRU0_GPO1.RGMII3_RD1 */
J721E_IOPAD(0xb8, PIN_INPUT, 4) /* (AE27) PRG0_PRU0_GPO2.RGMII3_RD2 */
J721E_IOPAD(0xbc, PIN_INPUT, 4) /* (AD26) PRG0_PRU0_GPO3.RGMII3_RD3 */
J721E_IOPAD(0xc8, PIN_INPUT, 4) /* (AE26) PRG0_PRU0_GPO6.RGMII3_RXC */
J721E_IOPAD(0xc0, PIN_INPUT, 4) /* (AD25) PRG0_PRU0_GPO4.RGMII3_RX_CTL */
J721E_IOPAD(0xdc, PIN_OUTPUT, 4) /* (AJ28) PRG0_PRU0_GPO11.RGMII3_TD0 */
J721E_IOPAD(0xe0, PIN_OUTPUT, 4) /* (AH27) PRG0_PRU0_GPO12.RGMII3_TD1 */
J721E_IOPAD(0xe4, PIN_OUTPUT, 4) /* (AH29) PRG0_PRU0_GPO13.RGMII3_TD2 */
J721E_IOPAD(0xe8, PIN_OUTPUT, 4) /* (AG28) PRG0_PRU0_GPO14.RGMII3_TD3 */
J721E_IOPAD(0xf0, PIN_OUTPUT, 4) /* (AH28) PRG0_PRU0_GPO16.RGMII3_TXC */
J721E_IOPAD(0xec, PIN_OUTPUT, 4) /* (AG27) PRG0_PRU0_GPO15.RGMII3_TX_CTL */
>;
};
rgmii4_default_pins: rgmii4-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x100, PIN_INPUT, 4) /* (AE29) PRG0_PRU1_GPO0.RGMII4_RD0 */
J721E_IOPAD(0x104, PIN_INPUT, 4) /* (AD28) PRG0_PRU1_GPO1.RGMII4_RD1 */
J721E_IOPAD(0x108, PIN_INPUT, 4) /* (AD27) PRG0_PRU1_GPO2.RGMII4_RD2 */
J721E_IOPAD(0x10c, PIN_INPUT, 4) /* (AC25) PRG0_PRU1_GPO3.RGMII4_RD3 */
J721E_IOPAD(0x118, PIN_INPUT, 4) /* (AC26) PRG0_PRU1_GPO6.RGMII4_RXC */
J721E_IOPAD(0x110, PIN_INPUT, 4) /* (AD29) PRG0_PRU1_GPO4.RGMII4_RX_CTL */
J721E_IOPAD(0x12c, PIN_OUTPUT, 4) /* (AG26) PRG0_PRU1_GPO11.RGMII4_TD0 */
J721E_IOPAD(0x130, PIN_OUTPUT, 4) /* (AF27) PRG0_PRU1_GPO12.RGMII4_TD1 */
J721E_IOPAD(0x134, PIN_OUTPUT, 4) /* (AF26) PRG0_PRU1_GPO13.RGMII4_TD2 */
J721E_IOPAD(0x138, PIN_OUTPUT, 4) /* (AE25) PRG0_PRU1_GPO14.RGMII4_TD3 */
J721E_IOPAD(0x140, PIN_OUTPUT, 4) /* (AG29) PRG0_PRU1_GPO16.RGMII4_TXC */
J721E_IOPAD(0x13c, PIN_OUTPUT, 4) /* (AF29) PRG0_PRU1_GPO15.RGMII4_TX_CTL */
>;
};
};
arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
View file @ 99355a23
......@@ -10,11 +10,11 @@
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-cadence.h>
#include "k3-pinctrl.h"
#include "k3-serdes.h"
&{/} {
aliases {
......
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View file @ 99355a23
......@@ -7,7 +7,8 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-ti.h>
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
#include "k3-serdes.h"
/ {
cmn_refclk: clock-cmnrefclk {
......@@ -76,7 +77,7 @@ usb_serdes_mux: mux-controller@4000 {
};
ehrpwm_tbclk: clock-controller@4140 {
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
......@@ -364,11 +365,12 @@ mailbox0_cluster11: mailbox@31f8b000 {
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>,
<0x0 0x31080000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
......@@ -378,9 +380,9 @@ main_ringacc: ringacc@3c000000 {
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>;
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
......@@ -660,7 +662,7 @@ wiz1_refclk_dig: refclk-dig {
assigned-clock-parents = <&k3_clks 293 13>;
};
wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
clocks = <&wiz1_refclk_dig>;
#clock-cells = <0>;
};
......@@ -1338,6 +1340,7 @@ main_gpio0: gpio@600000 {
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio1: gpio@601000 {
......@@ -1354,6 +1357,7 @@ main_gpio1: gpio@601000 {
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio2: gpio@610000 {
......@@ -1371,6 +1375,7 @@ main_gpio2: gpio@610000 {
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio3: gpio@611000 {
......@@ -1387,6 +1392,7 @@ main_gpio3: gpio@611000 {
power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 108 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio4: gpio@620000 {
......@@ -1404,6 +1410,7 @@ main_gpio4: gpio@620000 {
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 109 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio5: gpio@621000 {
......@@ -1420,6 +1427,7 @@ main_gpio5: gpio@621000 {
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 110 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio6: gpio@630000 {
......@@ -1437,6 +1445,7 @@ main_gpio6: gpio@630000 {
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio7: gpio@631000 {
......@@ -1453,6 +1462,7 @@ main_gpio7: gpio@631000 {
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
status = "disabled";
};
main_sdhci0: mmc@4f80000 {
......@@ -1477,6 +1487,7 @@ main_sdhci0: mmc@4f80000 {
ti,itap-del-sel-ddr52 = <0x3>;
ti,trm-icp = <0x8>;
dma-coherent;
status = "disabled";
};
main_sdhci1: mmc@4fb0000 {
......@@ -1504,6 +1515,7 @@ main_sdhci1: mmc@4fb0000 {
ti,clkbuf-sel = <0x7>;
dma-coherent;
sdhci-caps-mask = <0x2 0x0>;
status = "disabled";
};
main_sdhci2: mmc@4f98000 {
......@@ -1531,6 +1543,7 @@ main_sdhci2: mmc@4f98000 {
ti,clkbuf-sel = <0x7>;
dma-coherent;
sdhci-caps-mask = <0x2 0x0>;
status = "disabled";
};
usbss0: cdns-usb@4104000 {
......@@ -1761,11 +1774,11 @@ dss: dss@4a00000 {
"vp1", "vp2", "vp3", "vp4",
"wb";
clocks = <&k3_clks 152 0>,
<&k3_clks 152 1>,
<&k3_clks 152 4>,
<&k3_clks 152 9>,
<&k3_clks 152 13>;
clocks = <&k3_clks 152 0>,
<&k3_clks 152 1>,
<&k3_clks 152 4>,
<&k3_clks 152 9>,
<&k3_clks 152 13>;
clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
......@@ -2108,6 +2121,7 @@ c66_0: dsp@4d80800000 {
ti,sci-proc-ids = <0x03 0xff>;
resets = <&k3_reset 142 1>;
firmware-name = "j7-c66_0-fw";
status = "disabled";
};
c66_1: dsp@4d81800000 {
......@@ -2121,6 +2135,7 @@ c66_1: dsp@4d81800000 {
ti,sci-proc-ids = <0x04 0xff>;
resets = <&k3_reset 143 1>;
firmware-name = "j7-c66_1-fw";
status = "disabled";
};
c71_0: dsp@64800000 {
......@@ -2133,6 +2148,7 @@ c71_0: dsp@64800000 {
ti,sci-proc-ids = <0x30 0xff>;
resets = <&k3_reset 15 1>;
firmware-name = "j7-c71_0-fw";
status = "disabled";
};
icssg0: icssg@b000000 {
......
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
View file @ 99355a23
......@@ -281,6 +281,7 @@ wkup_gpio0: gpio@42110000 {
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
status = "disabled";
};
wkup_gpio1: gpio@42100000 {
......@@ -297,6 +298,7 @@ wkup_gpio1: gpio@42100000 {
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
status = "disabled";
};
mcu_i2c0: i2c@40b00000 {
......@@ -335,7 +337,7 @@ wkup_i2c0: i2c@42120000 {
status = "disabled";
};
fss: fss@47000000 {
fss: bus@47000000 {
compatible = "simple-bus";
reg = <0x0 0x47000000 0x0 0x100>;
#address-cells = <2>;
......@@ -378,6 +380,7 @@ ospi0: spi@47040000 {
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ospi1: spi@47050000 {
......@@ -392,6 +395,7 @@ ospi1: spi@47050000 {
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
......@@ -407,6 +411,7 @@ tscadc0: tscadc@40200000 {
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
......@@ -426,6 +431,7 @@ tscadc1: tscadc@40210000 {
dmas = <&main_udmap 0x7402>,
<&main_udmap 0x7403>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
......@@ -445,11 +451,12 @@ mcu_navss: bus@28380000 {
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
......@@ -459,9 +466,9 @@ mcu_ringacc: ringacc@2b800000 {
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
......
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
View file @ 99355a23
......@@ -582,13 +582,9 @@ &main_uart1 {
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_sdhci0 {
/* Unused */
status = "disabled";
};
&main_sdhci1 {
/* SD Card */
status = "okay";
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
......@@ -597,12 +593,8 @@ &main_sdhci1 {
disable-wp;
};
&main_sdhci2 {
/* Unused */
status = "disabled";
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
......@@ -666,11 +658,6 @@ partition@3fc0000 {
};
};
&ospi1 {
/* Unused */
status = "disabled";
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
......@@ -744,41 +731,19 @@ &main_i2c5 {
};
&main_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
&main_gpio1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rpi_header_gpio1_pins_default>;
};
&main_gpio2 {
status = "disabled";
};
&main_gpio3 {
status = "disabled";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio5 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
};
&main_gpio7 {
status = "disabled";
};
&wkup_gpio1 {
status = "disabled";
&wkup_gpio0 {
status = "okay";
};
&usb_serdes_mux {
......@@ -863,16 +828,6 @@ &usb1 {
phy-names = "cdns3,usb3-phy";
};
&tscadc0 {
/* Unused */
status = "disabled";
};
&tscadc1 {
/* Unused */
status = "disabled";
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
......@@ -1098,18 +1053,21 @@ &main_r5fss1_core1 {
};
&c66_0 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
......
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
View file @ 99355a23
......@@ -201,20 +201,8 @@ eeprom@50 {
};
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* CAV24C256WE-GT3 */
compatible = "atmel,24c256";
reg = <0x50>;
};
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
......@@ -437,18 +425,21 @@ &main_r5fss1_core1 {
};
&c66_0 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
status = "okay";
mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
......
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
View file @ 99355a23
......@@ -11,7 +11,8 @@
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include "k3-serdes.h"
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
......@@ -29,6 +30,8 @@ aliases {
can0 = &main_mcan16;
can1 = &mcu_mcan0;
can2 = &mcu_mcan1;
can3 = &main_mcan3;
can4 = &main_mcan5;
};
evm_12v0: fixedregulator-evm12v0 {
......@@ -109,6 +112,22 @@ transceiver2: can-phy2 {
standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
};
transceiver3: can-phy3 {
compatible = "ti,tcan1043";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
mux-states = <&mux0 1>;
};
transceiver4: can-phy4 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
mux-states = <&mux1 1>;
};
};
&main_pmx0 {
......@@ -152,6 +171,20 @@ main_usbss0_pins_default: main-usbss0-default-pins {
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
};
main_mcan3_pins_default: main-mcan3-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */
J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */
>;
};
main_mcan5_pins_default: main-mcan5-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */
J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */
>;
};
};
&wkup_pmx2 {
......@@ -249,36 +282,29 @@ J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */
J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */
>;
};
};
&wkup_pmx1 {
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
};
};
&main_gpio2 {
status = "disabled";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
&main_gpio0 {
status = "okay";
};
&wkup_gpio1 {
status = "disabled";
&wkup_gpio0 {
status = "okay";
};
&wkup_uart0 {
......@@ -332,6 +358,7 @@ exp2: gpio@22 {
&main_sdhci0 {
/* eMMC */
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
......@@ -339,6 +366,7 @@ &main_sdhci0 {
&main_sdhci1 {
/* SD card */
status = "okay";
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
disable-wp;
......@@ -407,7 +435,7 @@ &ospi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
flash@0{
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
......@@ -460,3 +488,17 @@ adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&main_mcan3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan3_pins_default>;
phys = <&transceiver3>;
};
&main_mcan5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan5_pins_default>;
phys = <&transceiver4>;
};
arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso 0 → 100644
View file @ 99355a23
// SPDX-License-Identifier: GPL-2.0
/**
* DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board.
*
* GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-pinctrl.h"
&{/} {
aliases {
ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
};
};
&main_pmx0 {
main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
>;
};
rgmii1_default_pins: rgmii1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
>;
};
};
&exp1 {
p15 {
/* P15 - EXP_MUX2 */
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "EXP_MUX2";
};
};
&main_cpsw {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_default_pins>;
};
&main_cpsw_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_cpsw_mdio_default_pins>;
#address-cells = <1>;
#size-cells = <0>;
main_cpsw_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&main_cpsw_port1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-handle = <&main_cpsw_phy0>;
};
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
View file @ 99355a23
......@@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 {
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
phy_gmii_sel_cpsw: phy@34 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x34 0x4>;
#phy-cells = <1>;
};
serdes_ln_ctrl: mux-controller@80 {
compatible = "mmio-mux";
reg = <0x80 0x10>;
......@@ -58,6 +64,72 @@ serdes_ln_ctrl: mux-controller@80 {
mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
<0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
};
ehrpwm_tbclk: clock-controller@140 {
compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x140 0x18>;
#clock-cells = <1>;
};
};
main_ehrpwm0: pwm@3000000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3000000 0x00 0x100>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
main_ehrpwm1: pwm@3010000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3010000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
main_ehrpwm2: pwm@3020000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3020000 0x00 0x100>;
power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
main_ehrpwm3: pwm@3030000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3030000 0x00 0x100>;
power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
main_ehrpwm4: pwm@3040000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3040000 0x00 0x100>;
power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
main_ehrpwm5: pwm@3050000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3050000 0x00 0x100>;
power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
clock-names = "tbclk", "fck";
status = "disabled";
};
gic500: interrupt-controller@1800000 {
......@@ -507,6 +579,7 @@ main_gpio0: gpio@600000 {
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio2: gpio@610000 {
......@@ -523,6 +596,7 @@ main_gpio2: gpio@610000 {
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio4: gpio@620000 {
......@@ -539,6 +613,7 @@ main_gpio4: gpio@620000 {
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio6: gpio@630000 {
......@@ -555,6 +630,7 @@ main_gpio6: gpio@630000 {
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
status = "disabled";
};
main_i2c0: i2c@2000000 {
......@@ -665,6 +741,7 @@ main_sdhci0: mmc@4f80000 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
status = "disabled";
};
main_sdhci1: mmc@4fb0000 {
......@@ -694,6 +771,7 @@ main_sdhci1: mmc@4fb0000 {
dma-coherent;
/* Masking support for SDR104 capability */
sdhci-caps-mask = <0x00000003 0x00000000>;
status = "disabled";
};
main_navss: bus@30000000 {
......@@ -993,8 +1071,9 @@ main_ringacc: ringacc@3c000000 {
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
<0x0 0x33000000 0x0 0x40000>,
<0x0 0x31080000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
......@@ -1039,6 +1118,69 @@ cpts@310d0000 {
};
};
main_cpsw: ethernet@c200000 {
compatible = "ti,j721e-cpsw-nuss";
reg = <0x00 0xc200000 0x00 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
dma-coherent;
clocks = <&k3_clks 28 28>;
clock-names = "fck";
power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
dmas = <&main_udmap 0xc640>,
<&main_udmap 0xc641>,
<&main_udmap 0xc642>,
<&main_udmap 0xc643>,
<&main_udmap 0xc644>,
<&main_udmap 0xc645>,
<&main_udmap 0xc646>,
<&main_udmap 0xc647>,
<&main_udmap 0x4640>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
status = "disabled";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
main_cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel_cpsw 1>;
status = "disabled";
};
};
main_cpsw_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x00 0xf00 0x00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 28 28>;
clock-names = "fck";
bus_freq = <1000000>;
status = "disabled";
};
cpts@3d000 {
compatible = "ti,am65-cpts";
reg = <0x00 0x3d000 0x00 0x400>;
clocks = <&k3_clks 28 3>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x04104000 0x00 0x100>;
......@@ -1507,4 +1649,50 @@ main_spi7: spi@2170000 {
clocks = <&k3_clks 346 1>;
status = "disabled";
};
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
<0x00 0x04a60000 0x00 0x10000>, /* vid2 */
<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
<0x00 0x04af0000 0x00 0x10000>; /* wb */
reg-names = "common_m", "common_s0",
"common_s1", "common_s2",
"vidl1", "vidl2","vid1","vid2",
"ovr1", "ovr2", "ovr3", "ovr4",
"vp1", "vp2", "vp3", "vp4",
"wb";
clocks = <&k3_clks 158 0>,
<&k3_clks 158 2>,
<&k3_clks 158 5>,
<&k3_clks 158 14>,
<&k3_clks 158 18>;
clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common_m",
"common_s0",
"common_s1",
"common_s2";
status = "disabled";
dss_ports: ports {
};
};
};
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
View file @ 99355a23
......@@ -323,6 +323,7 @@ wkup_gpio0: gpio@42110000 {
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 115 0>;
clock-names = "gpio";
status = "disabled";
};
wkup_gpio1: gpio@42100000 {
......@@ -339,6 +340,7 @@ wkup_gpio1: gpio@42100000 {
power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 116 0>;
clock-names = "gpio";
status = "disabled";
};
wkup_i2c0: i2c@42120000 {
......@@ -440,7 +442,7 @@ mcu_spi2: spi@40320000 {
status = "disabled";
};
mcu_navss: bus@28380000{
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
......@@ -455,8 +457,9 @@ mcu_ringacc: ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
......
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
View file @ 99355a23
......@@ -31,6 +31,18 @@ secure_ddr: optee@9e800000 {
};
};
mux0: mux-controller {
compatible = "gpio-mux";
#mux-state-cells = <1>;
mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
};
mux1: mux-controller {
compatible = "gpio-mux";
#mux-state-cells = <1>;
mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
};
transceiver0: can-phy0 {
/* standby pin has been grounded by default */
compatible = "ti,tcan1042";
......@@ -44,9 +56,6 @@ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
......
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
View file @ 99355a23
This diff is collapsed.
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
View file @ 99355a23
......@@ -60,7 +60,7 @@ main_gpio_intr: interrupt-controller@a00000 {
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <10>;
ti,interrupt-ranges = <8 360 56>;
ti,interrupt-ranges = <8 392 56>;
};
main_pmx0: pinctrl@11c000 {
......@@ -618,7 +618,7 @@ main_sdhci0: mmc@4f80000 {
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 140 1>, <&k3_clks 140 2>;
clock-names = "clk_ahb", "clk_xin";
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 140 2>;
assigned-clock-parents = <&k3_clks 140 3>;
bus-width = <8>;
......@@ -646,7 +646,7 @@ main_sdhci1: mmc@4fb0000 {
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 141 3>, <&k3_clks 141 4>;
clock-names = "clk_ahb", "clk_xin";
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 141 4>;
assigned-clock-parents = <&k3_clks 141 5>;
bus-width = <4>;
......@@ -670,6 +670,7 @@ main_sdhci1: mmc@4fb0000 {
};
main_navss: bus@30000000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
......@@ -705,6 +706,7 @@ main_udmass_inta: msi-controller@33d00000 {
};
secure_proxy_main: mailbox@32c00000 {
bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
......@@ -966,8 +968,9 @@ main_ringacc: ringacc@3c000000 {
reg = <0x00 0x3c000000 0x00 0x400000>,
<0x00 0x38000000 0x00 0x400000>,
<0x00 0x31120000 0x00 0x100>,
<0x00 0x33000000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
<0x00 0x33000000 0x00 0x40000>,
<0x00 0x31080000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
......@@ -1370,6 +1373,30 @@ main_spi7: spi@2170000 {
status = "disabled";
};
ufs_wrapper: ufs-wrapper@4e80000 {
compatible = "ti,j721e-ufs";
reg = <0x00 0x4e80000 0x00 0x100>;
power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 387 3>;
assigned-clocks = <&k3_clks 387 3>;
assigned-clock-parents = <&k3_clks 387 6>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
ufs@4e84000 {
compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
reg = <0x00 0x4e84000 0x00 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
freq-table-hz = <250000000 250000000>, <19200000 19200000>,
<19200000 19200000>;
clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>;
clock-names = "core_clk", "phy_clk", "ref_clk";
dma-coherent;
};
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
......@@ -1500,6 +1527,7 @@ c71_0: dsp@64800000 {
ti,sci-proc-ids = <0x30 0xff>;
resets = <&k3_reset 30 1>;
firmware-name = "j784s4-c71_0-fw";
status = "disabled";
};
c71_1: dsp@65800000 {
......@@ -1512,6 +1540,7 @@ c71_1: dsp@65800000 {
ti,sci-proc-ids = <0x31 0xff>;
resets = <&k3_reset 33 1>;
firmware-name = "j784s4-c71_1-fw";
status = "disabled";
};
c71_2: dsp@66800000 {
......@@ -1524,6 +1553,7 @@ c71_2: dsp@66800000 {
ti,sci-proc-ids = <0x32 0xff>;
resets = <&k3_reset 37 1>;
firmware-name = "j784s4-c71_2-fw";
status = "disabled";
};
c71_3: dsp@67800000 {
......@@ -1536,5 +1566,6 @@ c71_3: dsp@67800000 {
ti,sci-proc-ids = <0x33 0xff>;
resets = <&k3_reset 40 1>;
firmware-name = "j784s4-c71_3-fw";
status = "disabled";
};
};
arch/arm64/boot/dts/ti/k3-j784s4.dtsi
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arch/arm64/boot/dts/ti/k3-pinctrl.h
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arch/arm64/boot/dts/ti/k3-serdes.h 0 → 100644
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include/dt-bindings/mux/ti-serdes.h
View file @ 99355a23
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