PPC32: Modify the OpenPIC code to allow for all combinations of sense

and polarity of IRQs.  Update the machines in CONFIG_ALL_PPC for this change.

arch/ppc/kernel/open_pic.c

@@ -34,6 +34,11 @@
 
 void* OpenPIC_Addr;
 static volatile struct OpenPIC *OpenPIC = NULL;
+/*
+ * We define OpenPIC_InitSenses table thusly:
+ * bit 0x1: sense, 0 for edge and 1 for level.
+ * bit 0x2: polarity, 0 for negative, 1 for positive.
+ */
 u_int OpenPIC_NumInitSenses __initdata = 0;
 u_char *OpenPIC_InitSenses __initdata = NULL;
 extern int use_of_interrupt_tree;
@@ -380,14 +385,8 @@ void __init openpic_init(int main_pic, int offset, unsigned char *chrp_ack,
 
 	openpic_set_priority(0xf);
 
-	/* SIOint (8259 cascade) is special */
-	if (offset) {
-		openpic_initirq(0, 8, offset, 1, 1);
-		openpic_mapirq(0, 1<<0, 0);
-	}
-
-	/* Init all external sources */
-	for (i = 1; i < NumSources; i++) {
+	/* Init all external sources, including possibly the cascade. */
+	for (i = 0; i < NumSources; i++) {
 		int pri, sense;
 
 		if (ISR[i] == 0)
@@ -397,12 +396,18 @@ void __init openpic_init(int main_pic, int offset, unsigned char *chrp_ack,
 		openpic_disable_irq(i+offset);
 
 		pri = (i == programmer_switch_irq)? 9: 8;
+		/*
+		 * We find the vale from either the InitSenses table
+		 * or assume a negative polarity level interrupt.
+		 */
 		sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: 1;
-		if (sense)
+
+		if ((sense & IRQ_SENSE_MASK) == 1)
 			irq_desc[i+offset].status = IRQ_LEVEL;
 
 		/* Enabled, Priority 8 or 9 */
-		openpic_initirq(i, pri, i+offset, !sense, sense);
+		openpic_initirq(i, pri, i+offset, (sense & IRQ_POLARITY_MASK),
+				(sense & IRQ_SENSE_MASK));
 		/* Processor 0 */
 		openpic_mapirq(i, 1<<0, 0);
 	}

arch/ppc/kernel/prom.c

@@ -773,7 +773,12 @@ prom_get_irq_senses(unsigned char *senses, int off, int max)
 		for (j = 0; j < np->n_intrs; j++) {
 			i = np->intrs[j].line;
 			if (i >= off && i < max)
-				senses[i-off] = np->intrs[j].sense;
+				if (np->intrs[j].sense == 1)
+					senses[i-off] = (IRQ_SENSE_LEVEL
+						| IRQ_POLARITY_NEGATIVE);
+				else
+					senses[i-off] = (IRQ_SENSE_EDGE 
+						| IRQ_POLARITY_POSITIVE);
 		}
 	}
 }

arch/ppc/platforms/prep_pci.c

@@ -666,21 +666,21 @@ static struct pci_ops prep_pci_ops =
 #define	MOT_PROC2_BIT		0x800
 
 static u_char mvme2600_openpic_initsenses[] __initdata = {
-    1,	/* MVME2600_INT_SIO */
-    0,	/* MVME2600_INT_FALCN_ECC_ERR */
-    1,	/* MVME2600_INT_PCI_ETHERNET */
-    1,	/* MVME2600_INT_PCI_SCSI */
-    1,	/* MVME2600_INT_PCI_GRAPHICS */
-    1,	/* MVME2600_INT_PCI_VME0 */
-    1,	/* MVME2600_INT_PCI_VME1 */
-    1,	/* MVME2600_INT_PCI_VME2 */
-    1,	/* MVME2600_INT_PCI_VME3 */
-    1,	/* MVME2600_INT_PCI_INTA */
-    1,	/* MVME2600_INT_PCI_INTB */
-    1,	/* MVME2600_INT_PCI_INTC */
-    1,	/* MVME2600_INT_PCI_INTD */
-    1,	/* MVME2600_INT_LM_SIG0 */
-    1,	/* MVME2600_INT_LM_SIG1 */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_SIO */
+    (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_FALCN_ECC_ERR */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_ETHERNET */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_GRAPHICS */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
+    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
 };
 
 #define MOT_RAVEN_PRESENT	0x1

include/asm-ppc/open_pic.h

@@ -28,6 +28,19 @@
 #define OPENPIC_VEC_IPI		72	/* and up */
 #define OPENPIC_VEC_SPURIOUS	127
 
+/*
+ * For the OpenPIC_InitSenses table, we include both the sense
+ * and polarity in one number and mask out the value we want
+ * later on. -- Tom
+ */
+#define IRQ_SENSE_MASK		0x1
+#define IRQ_SENSE_LEVEL		0x1
+#define IRQ_SENSE_EDGE		0x0
+
+#define IRQ_POLARITY_MASK	0x2
+#define IRQ_POLARITY_POSITIVE	0x2
+#define IRQ_POLARITY_NEGATIVE	0x0
+
 /* OpenPIC IRQ controller structure */
 extern struct hw_interrupt_type open_pic;