Merge tag 'samsung-dt-2' of...

Merge tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt

Samsung 2nd DT updates for v4.4

- use exynos5420-dw-mshc instead of exynos5250 for exynos3250
- add DISP1 clocks and the DISP1 power domain of two closk
  on exynos5250 (clock commit got Stephen's ack)
- add vbus regulators on exynos3250, exynos4210 and exynos4412 boards
- fix typo in regulator enable GPIO property on s5pv20-aquila and goni
- document: correct the example of exynos power domain clocks
- document: consolidate exynos SoC dt-bindings and non-Samsung
  boards related compatibles (FriendlyARM, Google, Hardkernel
  and Insignal)
- update MAINTAINER entries accordingly (documentation)

* tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  MAINTAINERS: Add documentation and dt-bindings for exynos stuff
  dt-bindings: EXYNOS: Document compatibles from other vendors
  dt-bindings: Consolidate Exynos SoC bindings
  ARM: dts: Add clocks to DISP1 domain in exynos5250
  dt-bindings: Correct the example for Exynos power domain clocks
  ARM: dts: Fix typo in regulator enable GPIO property in s5pv210-goni
  ARM: dts: Fix typo in regulator enable GPIO property in s5pv210-aquila
  ARM: dts: Add vbus regulator to USB2 phy nodes on exynos3250, exynos4210 and exynos4412 boards
  clk: samsung: exynos5250: Add DISP1 clocks
  ARM: dts: use exynos5420-dw-mshc compatible for exynos3250
Signed-off-by: Olof Johansson <olof@lixom.net>

Documentation/devicetree/bindings/arm/samsung-boards.txt → Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt

@@ -16,7 +16,49 @@ Required root node properties:
 	- "samsung,sd5v1"	- for Exynos5440-based Samsung board.
 	- "samsung,ssdk5440"	- for Exynos5440-based Samsung board.
 
-Optional:
+* Other companies Exynos SoC based
+  * FriendlyARM
+	- "friendlyarm,tiny4412"  - for Exynos4412-based FriendlyARM
+				    TINY4412 board.
+
+  * Google
+	- "google,pi"		- for Exynos5800-based Google Peach Pi
+				  Rev 10+ board,
+	  also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14",
+		"google,pi-rev13", "google,pi-rev12", "google,pi-rev11",
+		"google,pi-rev10", "google,peach".
+
+	- "google,pit"		- for Exynos5420-based Google Peach Pit
+				  Rev 6+ (Exynos5420),
+	  also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14",
+		"google,pit-rev13", "google,pit-rev12", "google,pit-rev11",
+		"google,pit-rev10", "google,pit-rev9", "google,pit-rev8",
+		"google,pit-rev7", "google,pit-rev6", "google,peach".
+
+	- "google,snow-rev4"	- for Exynos5250-based Google Snow board,
+	  also: "google,snow"
+	- "google,snow-rev5"	- for Exynos5250-based Google Snow
+				  Rev 5+ board.
+	- "google,spring"	- for Exynos5250-based Google Spring board.
+
+  * Hardkernel
+	- "hardkernel,odroid-u3"  - for Exynos4412-based Hardkernel Odroid U3.
+	- "hardkernel,odroid-x"   - for Exynos4412-based Hardkernel Odroid X.
+	- "hardkernel,odroid-x2"  - for Exynos4412-based Hardkernel Odroid X2.
+	- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
+	- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
+					 Odroid XU3 Lite board.
+	- "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
+
+  * Insignal
+	- "insignal,arndale"      - for Exynos5250-based Insignal Arndale board.
+	- "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale
+				    Octa board.
+	- "insignal,origen"       - for Exynos4210-based Insignal Origen board.
+	- "insignal,origen4412    - for Exynos4412-based Insignal Origen board.
+
+
+Optional nodes:
     - firmware node, specifying presence and type of secure firmware:
         - compatible: only "samsung,secure-firmware" is currently supported
         - reg: address of non-secure SYSRAM used for communication with firmware

Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt

@@ -47,7 +47,7 @@ Required properties:
 - clocks: Required if the System MMU is needed to gate its clock.
 - power-domains: Required if the System MMU is needed to gate its power.
 	  Please refer to the following document:
-	  Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+	  Documentation/devicetree/bindings/power/pd-samsung.txt
 
 Examples:
 	gsc_0: gsc@13e00000 {

Documentation/devicetree/bindings/arm/exynos/power_domain.txt → Documentation/devicetree/bindings/power/pd-samsung.txt

@@ -43,9 +43,8 @@ Example:
 	mfc_pd: power-domain@10044060 {
 		compatible = "samsung,exynos4210-pd";
 		reg = <0x10044060 0x20>;
-		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
-			<&clock CLK_MOUT_USER_ACLK333>;
-		clock-names = "oscclk", "pclk0", "clk0";
+		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
+		clock-names = "oscclk", "clk0";
 		#power-domain-cells = <0>;
 	};
 

MAINTAINERS

@@ -1450,6 +1450,10 @@ F:	drivers/*/*s3c2410*
 F:	drivers/*/*/*s3c2410*
 F:	drivers/spi/spi-s3c*
 F:	sound/soc/samsung/*
+F:	Documentation/arm/Samsung/
+F:	Documentation/devicetree/bindings/arm/samsung/
+F:	Documentation/devicetree/bindings/sram/samsung-sram.txt
+F:	Documentation/devicetree/bindings/power/pd-samsung.txt
 N:	exynos
 
 ARM/SAMSUNG MOBILE MACHINE SUPPORT

arch/arm/boot/dts/exynos3250-monk.dts

@@ -161,6 +161,7 @@ &cpu0 {
 };
 
 &exynos_usbphy {
+	vbus-supply = <&safeout_reg>;
 	status = "okay";
 };
 

arch/arm/boot/dts/exynos3250-rinato.dts

@@ -153,6 +153,7 @@ &cpu0 {
 
 &exynos_usbphy {
 	status = "okay";
+	vbus-supply = <&safeout_reg>;
 };
 
 &hsotg {

arch/arm/boot/dts/exynos3250.dtsi

@@ -333,7 +333,7 @@ hsotg: hsotg@12480000 {
 		};
 
 		mshc_0: mshc@12510000 {
-			compatible = "samsung,exynos5250-dw-mshc";
+			compatible = "samsung,exynos5420-dw-mshc";
 			reg = <0x12510000 0x1000>;
 			interrupts = <0 142 0>;
 			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
@@ -345,7 +345,7 @@ mshc_0: mshc@12510000 {
 		};
 
 		mshc_1: mshc@12520000 {
-			compatible = "samsung,exynos5250-dw-mshc";
+			compatible = "samsung,exynos5420-dw-mshc";
 			reg = <0x12520000 0x1000>;
 			interrupts = <0 143 0>;
 			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;

arch/arm/boot/dts/exynos4210-trats.dts

@@ -252,6 +252,7 @@ dsi_in: endpoint {
 
 &exynos_usbphy {
 	status = "okay";
+	vbus-supply = <&safe1_sreg>;
 };
 
 &fimd {
@@ -449,7 +450,6 @@ vccsub_breg: BUCK7 {
 
 			safe1_sreg: ESAFEOUT1 {
 			     regulator-name = "SAFEOUT1";
-			     regulator-always-on;
 			};
 
 			safe2_sreg: ESAFEOUT2 {

arch/arm/boot/dts/exynos4210-universal_c210.dts

@@ -249,6 +249,7 @@ port@0 {
 
 &exynos_usbphy {
 	status = "okay";
+	vbus-supply = <&safeout1_reg>;
 };
 
 &fimd {
@@ -488,7 +489,6 @@ vichg_reg: ENVICHG {
 
 			safeout1_reg: ESAFEOUT1 {
 				regulator-name = "SAFEOUT1";
-				regulator-always-on;
 			};
 
 			safeout2_reg: ESAFEOUT2 {

arch/arm/boot/dts/exynos4412-trats2.dts

@@ -391,6 +391,7 @@ dsi_in: endpoint {
 };
 
 &exynos_usbphy {
+	vbus-supply = <&esafeout1_reg>;
 	status = "okay";
 };
 

arch/arm/boot/dts/exynos5250.dtsi

@@ -130,6 +130,10 @@ pd_disp1: disp1-power-domain@100440A0 {
 		compatible = "samsung,exynos4210-pd";
 		reg = <0x100440A0 0x20>;
 		#power-domain-cells = <0>;
+		clocks = <&clock CLK_FIN_PLL>,
+			 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
+			 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
+		clock-names = "oscclk", "clk0", "clk1";
 	};
 
 	clock: clock-controller@10010000 {

arch/arm/boot/dts/s5pv210-aquila.dts

@@ -46,7 +46,7 @@ vtf_reg: fixed-regulator@0 {
 			regulator-name = "V_TF_2.8V";
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
-			gpios = <&mp05 4 0>;
+			gpio = <&mp05 4 0>;
 			enable-active-high;
 		};
 

arch/arm/boot/dts/s5pv210-goni.dts

@@ -47,7 +47,7 @@ vtf_reg: fixed-regulator@0 {
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			reg = <0>;
-			gpios = <&mp05 4 0>;
+			gpio = <&mp05 4 0>;
 			enable-active-high;
 		};
 
@@ -73,7 +73,7 @@ tsp_reg: fixed-regulator@3 {
 			regulator-min-microvolt = <2800000>;
 			regulator-max-microvolt = <2800000>;
 			reg = <3>;
-			gpios = <&gpj1 3 0>;
+			gpio = <&gpj1 3 0>;
 			enable-active-high;
 		};
 	};

drivers/clk/samsung/clk-exynos5250.c

@@ -222,9 +222,13 @@ PNAME(mout_mpll_user_p)	= { "fin_pll", "mout_mpll" };
 PNAME(mout_bpll_user_p)	= { "fin_pll", "mout_bpll" };
 PNAME(mout_aclk166_p)	= { "mout_cpll", "mout_mpll_user" };
 PNAME(mout_aclk200_p)	= { "mout_mpll_user", "mout_bpll_user" };
+PNAME(mout_aclk300_p)	= { "mout_aclk300_disp1_mid",
+			    "mout_aclk300_disp1_mid1" };
 PNAME(mout_aclk400_p)	= { "mout_aclk400_g3d_mid", "mout_gpll" };
 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
+PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
+PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
 PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
 PNAME(mout_hdmi_p)	= { "div_hdmi_pixel", "sclk_hdmiphy" };
@@ -303,9 +307,13 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	 */
 	MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
 	MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+	MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
+	MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
 	MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
 	MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
 
+	MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
+		8, 1),
 	MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
 	MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
 
@@ -316,7 +324,10 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
 	MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
 
-	MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
+	MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
+		mout_aclk200_sub_p, SRC_TOP3, 4, 1),
+	MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
+		mout_aclk300_sub_p, SRC_TOP3, 6, 1),
 	MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
 	MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
 	MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
@@ -392,6 +403,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
 	DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
 	DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
 							24, 3),
+	DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
 
 	DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
 	DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),

include/dt-bindings/clock/exynos5250.h

@@ -173,8 +173,10 @@
 /* mux clocks */
 #define CLK_MOUT_HDMI		1024
 #define CLK_MOUT_GPLL		1025
+#define CLK_MOUT_ACLK200_DISP1_SUB	1026
+#define CLK_MOUT_ACLK300_DISP1_SUB	1027
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		1026
+#define CLK_NR_CLKS		1028
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */