ibmvnic: Ensure that device queue memory is cache-line aligned
PCI bus slowdowns were observed on IBM VNIC devices as a result of partial cache line writes and non-cache aligned full cache line writes. Ensure that packet data buffers are cache-line aligned to avoid these slowdowns. Signed-off-by: Dwip N. Banerjee <dnbanerg@us.ibm.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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