Commit 9c5d8933 authored by Thaissa Falbo's avatar Thaissa Falbo Committed by Greg Kroah-Hartman

staging:media:davinci_vpfe: Fixed block comments according to kernel coding style

Fixed block comments by following the checkpatch warnings

WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on separate line
Signed-off-by: default avatarThaissa Falbo <thaissa.falbo@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 72a5f6a8
......@@ -538,8 +538,8 @@ struct vpfe_isif_raw_config {
};
/**********************************************************************
IPIPE API Structures
**********************************************************************/
* IPIPE API Structures
**********************************************************************/
/* IPIPE module configurations */
......
......@@ -682,8 +682,10 @@ ipipe_set_rgb2rgb_regs(void __iomem *base_addr, unsigned int id,
ipipe_clock_enable(base_addr);
if (id == IPIPE_RGB2RGB_2) {
/* For second RGB module, gain integer is 3 bits instead
of 4, offset has 11 bits insread of 13 */
/*
* For second RGB module, gain integer is 3 bits instead
* of 4, offset has 11 bits insread of 13
*/
offset = RGB2_MUL_BASE;
integ_mask = 0x7;
offset_mask = RGB2RGB_2_OFST_MASK;
......@@ -792,8 +794,10 @@ ipipe_set_3d_lut_regs(void __iomem *base_addr, void __iomem *isp5_base_addr,
/* valied table */
tbl = lut_3d->table;
for (i = 0; i < VPFE_IPIPE_MAX_SIZE_3D_LUT; i++) {
/* Each entry has 0-9 (B), 10-19 (G) and
20-29 R values */
/*
* Each entry has 0-9 (B), 10-19 (G) and
* 20-29 R values
*/
val = tbl[i].b & D3_LUT_ENTRY_MASK;
val |= (tbl[i].g & D3_LUT_ENTRY_MASK) <<
D3_LUT_ENTRY_G_SHIFT;
......
......@@ -278,9 +278,10 @@
/* Resizer Rescale Parameters */
#define RSZ_EN_A 0x58
#define RSZ_EN_B 0xe8
/* offset of the registers to be added with base register of
either RSZ0 or RSZ1
*/
/*
* offset of the registers to be added with base register of
* either RSZ0 or RSZ1
*/
#define RSZ_MODE 0x4
#define RSZ_420 0x8
#define RSZ_I_VPS 0xc
......
......@@ -442,8 +442,10 @@ static int vpfe_register_entities(struct vpfe_device *vpfe_dev)
/* create links now, starting with external(i2c) entities */
for (i = 0; i < vpfe_dev->num_ext_subdevs; i++)
/* if entity has no pads (ex: amplifier),
cant establish link */
/*
* if entity has no pads (ex: amplifier),
* cant establish link
*/
if (vpfe_dev->sd[i]->entity.num_pads) {
ret = media_create_pad_link(&vpfe_dev->sd[i]->entity,
0, &vpfe_dev->vpfe_isif.subdev.entity,
......
......@@ -178,9 +178,10 @@ static int vpfe_update_pipe_state(struct vpfe_video_device *video)
if (ret)
return ret;
/* Find out if there is any input video
if yes, it is single shot.
*/
/*
* Find out if there is any input video
* if yes, it is single shot.
*/
if (pipe->input_num == 0) {
pipe->state = VPFE_PIPELINE_STREAM_CONTINUOUS;
ret = vpfe_update_current_ext_subdev(video);
......@@ -529,10 +530,11 @@ static int vpfe_release(struct file *file)
if (fh->io_allowed) {
if (video->started) {
vpfe_stop_capture(video);
/* mark pipe state as stopped in vpfe_release(),
as app might call streamon() after streamoff()
in which case driver has to start streaming.
*/
/*
* mark pipe state as stopped in vpfe_release(),
* as app might call streamon() after streamoff()
* in which case driver has to start streaming.
*/
video->pipe.state = VPFE_PIPELINE_STREAM_STOPPED;
vb2_streamoff(&video->buffer_queue,
video->buffer_queue.type);
......@@ -672,8 +674,10 @@ static int vpfe_enum_fmt(struct file *file, void *priv,
v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_enum_fmt\n");
/* since already subdev pad format is set,
only one pixel format is available */
/*
* since already subdev pad format is set,
* only one pixel format is available
*/
if (fmt->index > 0) {
v4l2_err(&vpfe_dev->v4l2_dev, "Invalid index\n");
return -EINVAL;
......
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