Commit 9ced9f03 authored by Russell King's avatar Russell King

Merge branch 'for-rmk' of...

Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable

Conflicts:
	arch/arm/mm/Kconfig
parents 9b963f32 b0b6ff0b
...@@ -715,7 +715,8 @@ config ARCH_S5P64X0 ...@@ -715,7 +715,8 @@ config ARCH_S5P64X0
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C2410_WATCHDOG if WATCHDOG
select ARCH_USES_GETTIMEOFFSET select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C_RTC if RTC_CLASS
help help
...@@ -753,15 +754,16 @@ config ARCH_S5PV210 ...@@ -753,15 +754,16 @@ config ARCH_S5PV210
select HAVE_CLK select HAVE_CLK
select ARM_L1_CACHE_SHIFT_6 select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select ARCH_USES_GETTIMEOFFSET select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C2410_WATCHDOG if WATCHDOG
help help
Samsung S5PV210/S5PC110 series based systems Samsung S5PV210/S5PC110 series based systems
config ARCH_S5PV310 config ARCH_EXYNOS4
bool "Samsung S5PV310/S5PC210" bool "Samsung EXYNOS4"
select CPU_V7 select CPU_V7
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO select GENERIC_GPIO
...@@ -772,7 +774,7 @@ config ARCH_S5PV310 ...@@ -772,7 +774,7 @@ config ARCH_S5PV310
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C2410_WATCHDOG if WATCHDOG
help help
Samsung S5PV310 series based systems Samsung EXYNOS4 series based systems
config ARCH_SHARK config ARCH_SHARK
bool "Shark" bool "Shark"
...@@ -991,7 +993,7 @@ source "arch/arm/mach-s5pc100/Kconfig" ...@@ -991,7 +993,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig" source "arch/arm/mach-s5pv210/Kconfig"
source "arch/arm/mach-s5pv310/Kconfig" source "arch/arm/mach-exynos4/Kconfig"
source "arch/arm/mach-shmobile/Kconfig" source "arch/arm/mach-shmobile/Kconfig"
...@@ -1278,7 +1280,7 @@ config SMP ...@@ -1278,7 +1280,7 @@ config SMP
depends on GENERIC_CLOCKEVENTS depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
select USE_GENERIC_SMP_HELPERS select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
...@@ -1366,7 +1368,7 @@ config LOCAL_TIMERS ...@@ -1366,7 +1368,7 @@ config LOCAL_TIMERS
bool "Use local timer interrupts" bool "Use local timer interrupts"
depends on SMP depends on SMP
default y default y
select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
help help
Enable support for local timers on SMP platforms, rather then the Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system legacy IPI broadcast method. Local timers allows the system
...@@ -1378,7 +1380,7 @@ source kernel/Kconfig.preempt ...@@ -1378,7 +1380,7 @@ source kernel/Kconfig.preempt
config HZ config HZ
int int
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91 default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
......
...@@ -178,7 +178,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0 ...@@ -178,7 +178,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5P6442) := s5p6442 machine-$(CONFIG_ARCH_S5P6442) := s5p6442
machine-$(CONFIG_ARCH_S5PC100) := s5pc100 machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210 machine-$(CONFIG_ARCH_S5PV210) := s5pv210
machine-$(CONFIG_ARCH_S5PV310) := s5pv310 machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
......
CONFIG_EXPERIMENTAL=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_EXYNOS4=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDKC210=y
CONFIG_MACH_SMDKV310=y
CONFIG_MACH_UNIVERSAL_C210=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_HOTPLUG_CPU=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_DEBUG_S3C_UART=1
CONFIG_CRC_CCITT=y
...@@ -10,6 +10,8 @@ CONFIG_S3C_BOOT_ERROR_RESET=y ...@@ -10,6 +10,8 @@ CONFIG_S3C_BOOT_ERROR_RESET=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1 CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDK6440=y CONFIG_MACH_SMDK6440=y
CONFIG_MACH_SMDK6450=y CONFIG_MACH_SMDK6450=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CPU_32v6K=y CONFIG_CPU_32v6K=y
CONFIG_AEABI=y CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
......
...@@ -13,6 +13,8 @@ CONFIG_MACH_AQUILA=y ...@@ -13,6 +13,8 @@ CONFIG_MACH_AQUILA=y
CONFIG_MACH_GONI=y CONFIG_MACH_GONI=y
CONFIG_MACH_SMDKC110=y CONFIG_MACH_SMDKC110=y
CONFIG_MACH_SMDKV210=y CONFIG_MACH_SMDKV210=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_VMSPLIT_2G=y CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
CONFIG_AEABI=y CONFIG_AEABI=y
......
# arch/arm/mach-s5pv310/Kconfig # arch/arm/mach-exynos4/Kconfig
# #
# Copyright (c) 2010 Samsung Electronics Co., Ltd. # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/ # http://www.samsung.com/
# #
# Licensed under GPLv2 # Licensed under GPLv2
# Configuration options for the S5PV310 # Configuration options for the EXYNOS4
if ARCH_S5PV310 if ARCH_EXYNOS4
config CPU_S5PV310 config CPU_EXYNOS4210
bool bool
select S3C_PL330_DMA select S3C_PL330_DMA
help help
Enable S5PV310 CPU support Enable EXYNOS4210 CPU support
config S5PV310_DEV_PD config EXYNOS4_MCT
bool "Kernel timer support by MCT"
help
Use MCT (Multi Core Timer) as kernel timers
config EXYNOS4_DEV_PD
bool bool
help help
Compile in platform device definitions for Power Domain Compile in platform device definitions for Power Domain
config S5PV310_SETUP_I2C1 config EXYNOS4_DEV_SYSMMU
bool
help
Common setup code for SYSTEM MMU in EXYNOS4
config EXYNOS4_SETUP_I2C1
bool bool
help help
Common setup code for i2c bus 1. Common setup code for i2c bus 1.
config S5PV310_SETUP_I2C2 config EXYNOS4_SETUP_I2C2
bool bool
help help
Common setup code for i2c bus 2. Common setup code for i2c bus 2.
config S5PV310_SETUP_I2C3 config EXYNOS4_SETUP_I2C3
bool bool
help help
Common setup code for i2c bus 3. Common setup code for i2c bus 3.
config S5PV310_SETUP_I2C4 config EXYNOS4_SETUP_I2C4
bool bool
help help
Common setup code for i2c bus 4. Common setup code for i2c bus 4.
config S5PV310_SETUP_I2C5 config EXYNOS4_SETUP_I2C5
bool bool
help help
Common setup code for i2c bus 5. Common setup code for i2c bus 5.
config S5PV310_SETUP_I2C6 config EXYNOS4_SETUP_I2C6
bool bool
help help
Common setup code for i2c bus 6. Common setup code for i2c bus 6.
config S5PV310_SETUP_I2C7 config EXYNOS4_SETUP_I2C7
bool bool
help help
Common setup code for i2c bus 7. Common setup code for i2c bus 7.
config S5PV310_SETUP_SDHCI config EXYNOS4_SETUP_KEYPAD
bool bool
select S5PV310_SETUP_SDHCI_GPIO
help help
Internal helper functions for S5PV310 based SDHCI systems. Common setup code for keypad.
config S5PV310_SETUP_SDHCI_GPIO config EXYNOS4_SETUP_SDHCI
bool
select EXYNOS4_SETUP_SDHCI_GPIO
help
Internal helper functions for EXYNOS4 based SDHCI systems.
config EXYNOS4_SETUP_SDHCI_GPIO
bool bool
help help
Common setup code for SDHCI gpio. Common setup code for SDHCI gpio.
config S5PV310_DEV_SYSMMU config EXYNOS4_SETUP_FIMC
bool bool
help help
Common setup code for SYSTEM MMU in S5PV310 Common setup code for the camera interfaces.
# machine support # machine support
menu "S5PC210 Machines" menu "EXYNOS4 Machines"
config MACH_SMDKC210 config MACH_SMDKC210
bool "SMDKC210" bool "SMDKC210"
select CPU_S5PV310 select CPU_EXYNOS4210
select S3C_DEV_RTC select S3C_DEV_RTC
select S3C_DEV_WDT select S3C_DEV_WDT
select S3C_DEV_I2C1 select S3C_DEV_I2C1
...@@ -85,48 +100,77 @@ config MACH_SMDKC210 ...@@ -85,48 +100,77 @@ config MACH_SMDKC210
select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3 select S3C_DEV_HSMMC3
select S5PV310_DEV_PD select EXYNOS4_DEV_PD
select S5PV310_SETUP_I2C1 select EXYNOS4_DEV_SYSMMU
select S5PV310_SETUP_SDHCI select EXYNOS4_SETUP_I2C1
select S5PV310_DEV_SYSMMU select EXYNOS4_SETUP_SDHCI
help help
Machine support for Samsung SMDKC210 Machine support for Samsung SMDKC210
S5PC210(MCP) is one of package option of S5PV310
config MACH_SMDKV310
bool "SMDKV310"
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select SAMSUNG_DEV_KEYPAD
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung SMDKV310
config MACH_ARMLEX4210
bool "ARMLEX4210"
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_SDHCI
select SATA_AHCI_PLATFORM
help
Machine support for Samsung ARMLEX4210 based on EXYNOS4210
config MACH_UNIVERSAL_C210 config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board" bool "Mobile UNIVERSAL_C210 Board"
select CPU_S5PV310 select CPU_EXYNOS4210
select S5P_DEV_ONENAND
select S3C_DEV_HSMMC select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3 select S3C_DEV_HSMMC3
select S5PV310_SETUP_SDHCI
select S3C_DEV_I2C1 select S3C_DEV_I2C1
select S5PV310_SETUP_I2C1 select S3C_DEV_I2C5
select S5P_DEV_ONENAND
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
help help
Machine support for Samsung Mobile Universal S5PC210 Reference Machine support for Samsung Mobile Universal S5PC210 Reference
Board. S5PC210(MCP) is one of package option of S5PV310 Board.
endmenu config MACH_NURI
bool "Mobile NURI Board"
menu "S5PV310 Machines" select CPU_EXYNOS4210
config MACH_SMDKV310
bool "SMDKV310"
select CPU_S5PV310
select S3C_DEV_RTC
select S3C_DEV_WDT select S3C_DEV_WDT
select S3C_DEV_I2C1
select S3C_DEV_HSMMC select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3 select S3C_DEV_HSMMC3
select S5PV310_DEV_PD select S3C_DEV_I2C1
select S5PV310_DEV_SYSMMU select S3C_DEV_I2C5
select S5PV310_SETUP_I2C1 select EXYNOS4_SETUP_I2C1
select S5PV310_SETUP_SDHCI select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select SAMSUNG_DEV_PWM
help help
Machine support for Samsung SMDKV310 Machine support for Samsung Mobile NURI Board.
endmenu endmenu
...@@ -134,13 +178,13 @@ comment "Configuration for HSMMC bus width" ...@@ -134,13 +178,13 @@ comment "Configuration for HSMMC bus width"
menu "Use 8-bit bus width" menu "Use 8-bit bus width"
config S5PV310_SDHCI_CH0_8BIT config EXYNOS4_SDHCI_CH0_8BIT
bool "Channel 0 with 8-bit bus" bool "Channel 0 with 8-bit bus"
help help
Support HSMMC Channel 0 8-bit bus. Support HSMMC Channel 0 8-bit bus.
If selected, Channel 1 is disabled. If selected, Channel 1 is disabled.
config S5PV310_SDHCI_CH2_8BIT config EXYNOS4_SDHCI_CH2_8BIT
bool "Channel 2 with 8-bit bus" bool "Channel 2 with 8-bit bus"
help help
Support HSMMC Channel 2 8-bit bus. Support HSMMC Channel 2 8-bit bus.
......
# arch/arm/mach-exynos4/Makefile
#
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
ifeq ($(CONFIG_EXYNOS4_MCT),y)
obj-y += mct.o
else
obj-y += time.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
endif
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
# machine support
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
# device support
obj-y += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o
/* linux/arch/arm/mach-s5pv310/cpu.c /* linux/arch/arm/mach-exynos4/cpu.c
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -19,8 +19,10 @@ ...@@ -19,8 +19,10 @@
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/clock.h> #include <plat/clock.h>
#include <plat/s5pv310.h> #include <plat/exynos4.h>
#include <plat/sdhci.h> #include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/fimc-core.h>
#include <mach/regs-irq.h> #include <mach/regs-irq.h>
...@@ -29,55 +31,60 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base, ...@@ -29,55 +31,60 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
/* Initial IO mappings */ /* Initial IO mappings */
static struct map_desc s5pv310_iodesc[] __initdata = { static struct map_desc exynos4_iodesc[] __initdata = {
{ {
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSRAM, .virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM), .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_CMU, .virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(S5PV310_PA_CMU), .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K, .length = SZ_128K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_PMU, .virtual = (unsigned long)S5P_VA_PMU,
.pfn = __phys_to_pfn(S5PV310_PA_PMU), .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
.length = SZ_64K, .length = SZ_64K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE, .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COMBINER), .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_COREPERI_BASE, .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COREPERI), .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
.length = SZ_8K, .length = SZ_8K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_L2CC, .virtual = (unsigned long)S5P_VA_L2CC,
.pfn = __phys_to_pfn(S5PV310_PA_L2CC), .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_GPIO1, .virtual = (unsigned long)S5P_VA_GPIO1,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO1), .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_GPIO2, .virtual = (unsigned long)S5P_VA_GPIO2,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO2), .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_GPIO3, .virtual = (unsigned long)S5P_VA_GPIO3,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO3), .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
.length = SZ_256, .length = SZ_256,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_DMC0, .virtual = (unsigned long)S5P_VA_DMC0,
.pfn = __phys_to_pfn(S5PV310_PA_DMC0), .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
...@@ -87,13 +94,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = { ...@@ -87,13 +94,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_SROMC, .virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(S5PV310_PA_SROMC), .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, },
}; };
static void s5pv310_idle(void) static void exynos4_idle(void)
{ {
if (!need_resched()) if (!need_resched())
cpu_do_idle(); cpu_do_idle();
...@@ -101,32 +108,38 @@ static void s5pv310_idle(void) ...@@ -101,32 +108,38 @@ static void s5pv310_idle(void)
local_irq_enable(); local_irq_enable();
} }
/* s5pv310_map_io /*
* exynos4_map_io
* *
* register the standard cpu IO areas * register the standard cpu IO areas
*/ */
void __init s5pv310_map_io(void) void __init exynos4_map_io(void)
{ {
iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc)); iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
/* initialize device information early */ /* initialize device information early */
s5pv310_default_sdhci0(); exynos4_default_sdhci0();
s5pv310_default_sdhci1(); exynos4_default_sdhci1();
s5pv310_default_sdhci2(); exynos4_default_sdhci2();
s5pv310_default_sdhci3(); exynos4_default_sdhci3();
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
} }
void __init s5pv310_init_clocks(int xtal) void __init exynos4_init_clocks(int xtal)
{ {
printk(KERN_DEBUG "%s: initializing clocks\n", __func__); printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal); s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal); s5p_register_clocks(xtal);
s5pv310_register_clocks(); exynos4_register_clocks();
s5pv310_setup_clocks(); exynos4_setup_clocks();
} }
void __init s5pv310_init_irq(void) void __init exynos4_init_irq(void)
{ {
int irq; int irq;
...@@ -148,29 +161,29 @@ void __init s5pv310_init_irq(void) ...@@ -148,29 +161,29 @@ void __init s5pv310_init_irq(void)
} }
/* The parameters of s5p_init_irq() are for VIC init. /* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because S5PV310 * Theses parameters should be NULL and 0 because EXYNOS4
* uses GIC instead of VIC. * uses GIC instead of VIC.
*/ */
s5p_init_irq(NULL, 0); s5p_init_irq(NULL, 0);
} }
struct sysdev_class s5pv310_sysclass = { struct sysdev_class exynos4_sysclass = {
.name = "s5pv310-core", .name = "exynos4-core",
}; };
static struct sys_device s5pv310_sysdev = { static struct sys_device exynos4_sysdev = {
.cls = &s5pv310_sysclass, .cls = &exynos4_sysclass,
}; };
static int __init s5pv310_core_init(void) static int __init exynos4_core_init(void)
{ {
return sysdev_class_register(&s5pv310_sysclass); return sysdev_class_register(&exynos4_sysclass);
} }
core_initcall(s5pv310_core_init); core_initcall(exynos4_core_init);
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
static int __init s5pv310_l2x0_cache_init(void) static int __init exynos4_l2x0_cache_init(void)
{ {
/* TAG, Data Latency Control: 2cycle */ /* TAG, Data Latency Control: 2cycle */
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
...@@ -188,15 +201,15 @@ static int __init s5pv310_l2x0_cache_init(void) ...@@ -188,15 +201,15 @@ static int __init s5pv310_l2x0_cache_init(void)
return 0; return 0;
} }
early_initcall(s5pv310_l2x0_cache_init); early_initcall(exynos4_l2x0_cache_init);
#endif #endif
int __init s5pv310_init(void) int __init exynos4_init(void)
{ {
printk(KERN_INFO "S5PV310: Initializing architecture\n"); printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
/* set idle function */ /* set idle function */
pm_idle = s5pv310_idle; pm_idle = exynos4_idle;
return sysdev_register(&s5pv310_sysdev); return sysdev_register(&exynos4_sysdev);
} }
/* linux/arch/arm/mach-s5pv310/cpufreq.c /* linux/arch/arm/mach-exynos4/cpufreq.c
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* S5PV310 - CPU frequency scaling support * EXYNOS4 - CPU frequency scaling support
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -31,15 +31,13 @@ static struct clk *moutcore; ...@@ -31,15 +31,13 @@ static struct clk *moutcore;
static struct clk *mout_mpll; static struct clk *mout_mpll;
static struct clk *mout_apll; static struct clk *mout_apll;
#ifdef CONFIG_REGULATOR
static struct regulator *arm_regulator; static struct regulator *arm_regulator;
static struct regulator *int_regulator; static struct regulator *int_regulator;
#endif
static struct cpufreq_freqs freqs; static struct cpufreq_freqs freqs;
static unsigned int memtype; static unsigned int memtype;
enum s5pv310_memory_type { enum exynos4_memory_type {
DDR2 = 4, DDR2 = 4,
LPDDR2, LPDDR2,
DDR3, DDR3,
...@@ -49,7 +47,7 @@ enum cpufreq_level_index { ...@@ -49,7 +47,7 @@ enum cpufreq_level_index {
L0, L1, L2, L3, CPUFREQ_LEVEL_END, L0, L1, L2, L3, CPUFREQ_LEVEL_END,
}; };
static struct cpufreq_frequency_table s5pv310_freq_table[] = { static struct cpufreq_frequency_table exynos4_freq_table[] = {
{L0, 1000*1000}, {L0, 1000*1000},
{L1, 800*1000}, {L1, 800*1000},
{L2, 400*1000}, {L2, 400*1000},
...@@ -160,7 +158,7 @@ struct cpufreq_voltage_table { ...@@ -160,7 +158,7 @@ struct cpufreq_voltage_table {
unsigned int int_volt; unsigned int int_volt;
}; };
static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = { static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
{ {
.index = L0, .index = L0,
.arm_volt = 1200000, .arm_volt = 1200000,
...@@ -180,7 +178,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = { ...@@ -180,7 +178,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
}, },
}; };
static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = { static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
/* APLL FOUT L0: 1000MHz */ /* APLL FOUT L0: 1000MHz */
((250 << 16) | (6 << 8) | 1), ((250 << 16) | (6 << 8) | 1),
...@@ -194,17 +192,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = { ...@@ -194,17 +192,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
((200 << 16) | (6 << 8) | 4), ((200 << 16) | (6 << 8) | 4),
}; };
int s5pv310_verify_speed(struct cpufreq_policy *policy) int exynos4_verify_speed(struct cpufreq_policy *policy)
{ {
return cpufreq_frequency_table_verify(policy, s5pv310_freq_table); return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
} }
unsigned int s5pv310_getspeed(unsigned int cpu) unsigned int exynos4_getspeed(unsigned int cpu)
{ {
return clk_get_rate(cpu_clk) / 1000; return clk_get_rate(cpu_clk) / 1000;
} }
void s5pv310_set_clkdiv(unsigned int div_index) void exynos4_set_clkdiv(unsigned int div_index)
{ {
unsigned int tmp; unsigned int tmp;
...@@ -321,7 +319,7 @@ void s5pv310_set_clkdiv(unsigned int div_index) ...@@ -321,7 +319,7 @@ void s5pv310_set_clkdiv(unsigned int div_index)
} while (tmp & 0x11); } while (tmp & 0x11);
} }
static void s5pv310_set_apll(unsigned int index) static void exynos4_set_apll(unsigned int index)
{ {
unsigned int tmp; unsigned int tmp;
...@@ -340,7 +338,7 @@ static void s5pv310_set_apll(unsigned int index) ...@@ -340,7 +338,7 @@ static void s5pv310_set_apll(unsigned int index)
/* 3. Change PLL PMS values */ /* 3. Change PLL PMS values */
tmp = __raw_readl(S5P_APLL_CON0); tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
tmp |= s5pv310_apll_pms_table[index]; tmp |= exynos4_apll_pms_table[index];
__raw_writel(tmp, S5P_APLL_CON0); __raw_writel(tmp, S5P_APLL_CON0);
/* 4. wait_lock_time */ /* 4. wait_lock_time */
...@@ -357,99 +355,95 @@ static void s5pv310_set_apll(unsigned int index) ...@@ -357,99 +355,95 @@ static void s5pv310_set_apll(unsigned int index)
} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
} }
static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index) static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
{ {
unsigned int tmp; unsigned int tmp;
if (old_index > new_index) { if (old_index > new_index) {
/* The frequency changing to L0 needs to change apll */ /* The frequency changing to L0 needs to change apll */
if (freqs.new == s5pv310_freq_table[L0].frequency) { if (freqs.new == exynos4_freq_table[L0].frequency) {
/* 1. Change the system clock divider values */ /* 1. Change the system clock divider values */
s5pv310_set_clkdiv(new_index); exynos4_set_clkdiv(new_index);
/* 2. Change the apll m,p,s value */ /* 2. Change the apll m,p,s value */
s5pv310_set_apll(new_index); exynos4_set_apll(new_index);
} else { } else {
/* 1. Change the system clock divider values */ /* 1. Change the system clock divider values */
s5pv310_set_clkdiv(new_index); exynos4_set_clkdiv(new_index);
/* 2. Change just s value in apll m,p,s value */ /* 2. Change just s value in apll m,p,s value */
tmp = __raw_readl(S5P_APLL_CON0); tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~(0x7 << 0); tmp &= ~(0x7 << 0);
tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
__raw_writel(tmp, S5P_APLL_CON0); __raw_writel(tmp, S5P_APLL_CON0);
} }
} }
else if (old_index < new_index) { else if (old_index < new_index) {
/* The frequency changing from L0 needs to change apll */ /* The frequency changing from L0 needs to change apll */
if (freqs.old == s5pv310_freq_table[L0].frequency) { if (freqs.old == exynos4_freq_table[L0].frequency) {
/* 1. Change the apll m,p,s value */ /* 1. Change the apll m,p,s value */
s5pv310_set_apll(new_index); exynos4_set_apll(new_index);
/* 2. Change the system clock divider values */ /* 2. Change the system clock divider values */
s5pv310_set_clkdiv(new_index); exynos4_set_clkdiv(new_index);
} else { } else {
/* 1. Change just s value in apll m,p,s value */ /* 1. Change just s value in apll m,p,s value */
tmp = __raw_readl(S5P_APLL_CON0); tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~(0x7 << 0); tmp &= ~(0x7 << 0);
tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
__raw_writel(tmp, S5P_APLL_CON0); __raw_writel(tmp, S5P_APLL_CON0);
/* 2. Change the system clock divider values */ /* 2. Change the system clock divider values */
s5pv310_set_clkdiv(new_index); exynos4_set_clkdiv(new_index);
} }
} }
} }
static int s5pv310_target(struct cpufreq_policy *policy, static int exynos4_target(struct cpufreq_policy *policy,
unsigned int target_freq, unsigned int target_freq,
unsigned int relation) unsigned int relation)
{ {
unsigned int index, old_index; unsigned int index, old_index;
unsigned int arm_volt, int_volt; unsigned int arm_volt, int_volt;
freqs.old = s5pv310_getspeed(policy->cpu); freqs.old = exynos4_getspeed(policy->cpu);
if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
freqs.old, relation, &old_index)) freqs.old, relation, &old_index))
return -EINVAL; return -EINVAL;
if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
target_freq, relation, &index)) target_freq, relation, &index))
return -EINVAL; return -EINVAL;
freqs.new = s5pv310_freq_table[index].frequency; freqs.new = exynos4_freq_table[index].frequency;
freqs.cpu = policy->cpu; freqs.cpu = policy->cpu;
if (freqs.new == freqs.old) if (freqs.new == freqs.old)
return 0; return 0;
/* get the voltage value */ /* get the voltage value */
arm_volt = s5pv310_volt_table[index].arm_volt; arm_volt = exynos4_volt_table[index].arm_volt;
int_volt = s5pv310_volt_table[index].int_volt; int_volt = exynos4_volt_table[index].int_volt;
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
/* control regulator */ /* control regulator */
if (freqs.new > freqs.old) { if (freqs.new > freqs.old) {
/* Voltage up */ /* Voltage up */
#ifdef CONFIG_REGULATOR
regulator_set_voltage(arm_regulator, arm_volt, arm_volt); regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
regulator_set_voltage(int_regulator, int_volt, int_volt); regulator_set_voltage(int_regulator, int_volt, int_volt);
#endif
} }
/* Clock Configuration Procedure */ /* Clock Configuration Procedure */
s5pv310_set_frequency(old_index, index); exynos4_set_frequency(old_index, index);
/* control regulator */ /* control regulator */
if (freqs.new < freqs.old) { if (freqs.new < freqs.old) {
/* Voltage down */ /* Voltage down */
#ifdef CONFIG_REGULATOR
regulator_set_voltage(arm_regulator, arm_volt, arm_volt); regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
regulator_set_voltage(int_regulator, int_volt, int_volt); regulator_set_voltage(int_regulator, int_volt, int_volt);
#endif
} }
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
...@@ -458,52 +452,52 @@ static int s5pv310_target(struct cpufreq_policy *policy, ...@@ -458,52 +452,52 @@ static int s5pv310_target(struct cpufreq_policy *policy,
} }
#ifdef CONFIG_PM #ifdef CONFIG_PM
static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy, static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy,
pm_message_t pmsg) pm_message_t pmsg)
{ {
return 0; return 0;
} }
static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy) static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
{ {
return 0; return 0;
} }
#endif #endif
static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy) static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
{ {
policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu); policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu); cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
/* set the transition latency value */ /* set the transition latency value */
policy->cpuinfo.transition_latency = 100000; policy->cpuinfo.transition_latency = 100000;
/* /*
* S5PV310 multi-core processors has 2 cores * EXYNOS4 multi-core processors has 2 cores
* that the frequency cannot be set independently. * that the frequency cannot be set independently.
* Each cpu is bound to the same speed. * Each cpu is bound to the same speed.
* So the affected cpu is all of the cpus. * So the affected cpu is all of the cpus.
*/ */
cpumask_setall(policy->cpus); cpumask_setall(policy->cpus);
return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table); return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
} }
static struct cpufreq_driver s5pv310_driver = { static struct cpufreq_driver exynos4_driver = {
.flags = CPUFREQ_STICKY, .flags = CPUFREQ_STICKY,
.verify = s5pv310_verify_speed, .verify = exynos4_verify_speed,
.target = s5pv310_target, .target = exynos4_target,
.get = s5pv310_getspeed, .get = exynos4_getspeed,
.init = s5pv310_cpufreq_cpu_init, .init = exynos4_cpufreq_cpu_init,
.name = "s5pv310_cpufreq", .name = "exynos4_cpufreq",
#ifdef CONFIG_PM #ifdef CONFIG_PM
.suspend = s5pv310_cpufreq_suspend, .suspend = exynos4_cpufreq_suspend,
.resume = s5pv310_cpufreq_resume, .resume = exynos4_cpufreq_resume,
#endif #endif
}; };
static int __init s5pv310_cpufreq_init(void) static int __init exynos4_cpufreq_init(void)
{ {
cpu_clk = clk_get(NULL, "armclk"); cpu_clk = clk_get(NULL, "armclk");
if (IS_ERR(cpu_clk)) if (IS_ERR(cpu_clk))
...@@ -521,7 +515,6 @@ static int __init s5pv310_cpufreq_init(void) ...@@ -521,7 +515,6 @@ static int __init s5pv310_cpufreq_init(void)
if (IS_ERR(mout_apll)) if (IS_ERR(mout_apll))
goto out; goto out;
#ifdef CONFIG_REGULATOR
arm_regulator = regulator_get(NULL, "vdd_arm"); arm_regulator = regulator_get(NULL, "vdd_arm");
if (IS_ERR(arm_regulator)) { if (IS_ERR(arm_regulator)) {
printk(KERN_ERR "failed to get resource %s\n", "vdd_arm"); printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
...@@ -533,7 +526,6 @@ static int __init s5pv310_cpufreq_init(void) ...@@ -533,7 +526,6 @@ static int __init s5pv310_cpufreq_init(void)
printk(KERN_ERR "failed to get resource %s\n", "vdd_int"); printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
goto out; goto out;
} }
#endif
/* /*
* Check DRAM type. * Check DRAM type.
...@@ -550,7 +542,7 @@ static int __init s5pv310_cpufreq_init(void) ...@@ -550,7 +542,7 @@ static int __init s5pv310_cpufreq_init(void)
printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype); printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
} }
return cpufreq_register_driver(&s5pv310_driver); return cpufreq_register_driver(&exynos4_driver);
out: out:
if (!IS_ERR(cpu_clk)) if (!IS_ERR(cpu_clk))
...@@ -565,16 +557,14 @@ static int __init s5pv310_cpufreq_init(void) ...@@ -565,16 +557,14 @@ static int __init s5pv310_cpufreq_init(void)
if (!IS_ERR(mout_apll)) if (!IS_ERR(mout_apll))
clk_put(mout_apll); clk_put(mout_apll);
#ifdef CONFIG_REGULATOR
if (!IS_ERR(arm_regulator)) if (!IS_ERR(arm_regulator))
regulator_put(arm_regulator); regulator_put(arm_regulator);
if (!IS_ERR(int_regulator)) if (!IS_ERR(int_regulator))
regulator_put(int_regulator); regulator_put(int_regulator);
#endif
printk(KERN_ERR "%s: failed initialization\n", __func__); printk(KERN_ERR "%s: failed initialization\n", __func__);
return -EINVAL; return -EINVAL;
} }
late_initcall(s5pv310_cpufreq_init); late_initcall(exynos4_cpufreq_init);
/* linux/arch/arm/mach-exynos4/dev-ahci.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - AHCI support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/ahci_platform.h>
#include <plat/cpu.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <mach/regs-pmu.h>
/* PHY Control Register */
#define SATA_CTRL0 0x0
/* PHY Link Control Register */
#define SATA_CTRL1 0x4
/* PHY Status Register */
#define SATA_PHY_STATUS 0x8
#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27)
#define SATA_CTRL0_SPEED_MODE (1 << 26)
#define SATA_CTRL0_M_PHY_CAL (1 << 19)
#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10)
#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9)
#define SATA_CTRL0_PHY_POR_N (1 << 8)
#define SATA_CTRL1_RST_PMALIVE_N (1 << 8)
#define SATA_CTRL1_RST_RXOOB_N (1 << 7)
#define SATA_CTRL1_RST_RX_N (1 << 6)
#define SATA_CTRL1_RST_TX_N (1 << 5)
#define SATA_PHY_STATUS_CMU_OK (1 << 18)
#define SATA_PHY_STATUS_LANE_OK (1 << 16)
#define LANE0 0x200
#define COM_LANE 0xA00
#define HOST_PORTS_IMPL 0xC
#define SCLK_SATA_FREQ (67 * MHZ)
static void __iomem *phy_base, *phy_ctrl;
struct phy_reg {
u8 reg;
u8 val;
};
/* SATA PHY setup */
static const struct phy_reg exynos4_sataphy_cmu[] = {
{ 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
{ 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
{ 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
{ 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
{ 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
{ 0x6b, 0xc8 }, { 0x6c, 0x06 },
};
static const struct phy_reg exynos4_sataphy_lane[] = {
{ 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
{ 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
{ 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
{ 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
{ 0x51, 0x0f },
};
static const struct phy_reg exynos4_sataphy_comlane[] = {
{ 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
{ 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
{ 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
{ 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
{ 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
{ 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
{ 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
{ 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
{ 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
{ 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
{ 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
{ 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
{ 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
{ 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
};
static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
{
unsigned long timeout;
/* wait for maximum of 3 sec */
timeout = jiffies + msecs_to_jiffies(3000);
while (!(__raw_readl(reg) & bit)) {
if (time_after(jiffies, timeout))
return -1;
cpu_relax();
}
return 0;
}
static int ahci_phy_init(void __iomem *mmio)
{
int i, ctrl0;
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
__raw_writeb(exynos4_sataphy_cmu[i].val,
phy_base + (exynos4_sataphy_cmu[i].reg * 4));
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
__raw_writeb(exynos4_sataphy_lane[i].val,
phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
__raw_writeb(exynos4_sataphy_comlane[i].val,
phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
__raw_writeb(0x07, phy_base);
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
SATA_PHY_STATUS_CMU_OK) < 0) {
printk(KERN_ERR "PHY CMU not ready\n");
return -EBUSY;
}
__raw_writeb(0x03, phy_base + (COM_LANE * 4));
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
SATA_PHY_STATUS_LANE_OK) < 0) {
printk(KERN_ERR "PHY LANE not ready\n");
return -EBUSY;
}
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_M_PHY_CAL;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
return 0;
}
static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
{
struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
int val, ret;
phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
if (!phy_base) {
dev_err(dev, "failed to allocate memory for SATA PHY\n");
return -ENOMEM;
}
phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
if (!phy_ctrl) {
dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
ret = -ENOMEM;
goto err1;
}
clk_sata = clk_get(dev, "sata");
if (IS_ERR(clk_sata)) {
dev_err(dev, "failed to get sata clock\n");
ret = PTR_ERR(clk_sata);
clk_sata = NULL;
goto err2;
}
clk_enable(clk_sata);
clk_sataphy = clk_get(dev, "sataphy");
if (IS_ERR(clk_sataphy)) {
dev_err(dev, "failed to get sataphy clock\n");
ret = PTR_ERR(clk_sataphy);
clk_sataphy = NULL;
goto err3;
}
clk_enable(clk_sataphy);
clk_sclk_sata = clk_get(dev, "sclk_sata");
if (IS_ERR(clk_sclk_sata)) {
dev_err(dev, "failed to get sclk_sata\n");
ret = PTR_ERR(clk_sclk_sata);
clk_sclk_sata = NULL;
goto err4;
}
clk_enable(clk_sclk_sata);
clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
/* Enable PHY link control */
val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
__raw_writel(val, phy_ctrl + SATA_CTRL1);
/* Set communication speed as 3Gbps and enable PHY power */
val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
SATA_CTRL0_PHY_POR_N;
__raw_writel(val, phy_ctrl + SATA_CTRL0);
/* Port0 is available */
__raw_writel(0x1, mmio + HOST_PORTS_IMPL);
return ahci_phy_init(mmio);
err4:
clk_disable(clk_sataphy);
clk_put(clk_sataphy);
err3:
clk_disable(clk_sata);
clk_put(clk_sata);
err2:
iounmap(phy_ctrl);
err1:
iounmap(phy_base);
return ret;
}
static struct ahci_platform_data exynos4_ahci_pdata = {
.init = exynos4_ahci_init,
};
static struct resource exynos4_ahci_resource[] = {
[0] = {
.start = EXYNOS4_PA_SATA,
.end = EXYNOS4_PA_SATA + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SATA,
.end = IRQ_SATA,
.flags = IORESOURCE_IRQ,
},
};
static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
struct platform_device exynos4_device_ahci = {
.name = "ahci",
.id = -1,
.resource = exynos4_ahci_resource,
.num_resources = ARRAY_SIZE(exynos4_ahci_resource),
.dev = {
.platform_data = &exynos4_ahci_pdata,
.dma_mask = &exynos4_ahci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
/* linux/arch/arm/mach-s5pv310/dev-audio.c /* linux/arch/arm/mach-exynos4/dev-audio.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* *
* Copyright (c) 2010 Samsung Electronics Co. Ltd * Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com> * Jaswinder Singh <jassi.brar@samsung.com>
...@@ -24,18 +27,18 @@ static const char *rclksrc[] = { ...@@ -24,18 +27,18 @@ static const char *rclksrc[] = {
[1] = "i2sclk", [1] = "i2sclk",
}; };
static int s5pv310_cfg_i2s(struct platform_device *pdev) static int exynos4_cfg_i2s(struct platform_device *pdev)
{ {
/* configure GPIO for i2s port */ /* configure GPIO for i2s port */
switch (pdev->id) { switch (pdev->id) {
case 0: case 0:
s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2)); s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
break; break;
case 1: case 1:
s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2)); s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
break; break;
case 2: case 2:
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4)); s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
break; break;
default: default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id); printk(KERN_ERR "Invalid Device %d\n", pdev->id);
...@@ -46,7 +49,7 @@ static int s5pv310_cfg_i2s(struct platform_device *pdev) ...@@ -46,7 +49,7 @@ static int s5pv310_cfg_i2s(struct platform_device *pdev)
} }
static struct s3c_audio_pdata i2sv5_pdata = { static struct s3c_audio_pdata i2sv5_pdata = {
.cfg_gpio = s5pv310_cfg_i2s, .cfg_gpio = exynos4_cfg_i2s,
.type = { .type = {
.i2s = { .i2s = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
...@@ -56,10 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = { ...@@ -56,10 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
}, },
}; };
static struct resource s5pv310_i2s0_resource[] = { static struct resource exynos4_i2s0_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_I2S0, .start = EXYNOS4_PA_I2S0,
.end = S5PV310_PA_I2S0 + 0x100 - 1, .end = EXYNOS4_PA_I2S0 + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -79,11 +82,11 @@ static struct resource s5pv310_i2s0_resource[] = { ...@@ -79,11 +82,11 @@ static struct resource s5pv310_i2s0_resource[] = {
}, },
}; };
struct platform_device s5pv310_device_i2s0 = { struct platform_device exynos4_device_i2s0 = {
.name = "samsung-i2s", .name = "samsung-i2s",
.id = 0, .id = 0,
.num_resources = ARRAY_SIZE(s5pv310_i2s0_resource), .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
.resource = s5pv310_i2s0_resource, .resource = exynos4_i2s0_resource,
.dev = { .dev = {
.platform_data = &i2sv5_pdata, .platform_data = &i2sv5_pdata,
}, },
...@@ -95,7 +98,7 @@ static const char *rclksrc_v3[] = { ...@@ -95,7 +98,7 @@ static const char *rclksrc_v3[] = {
}; };
static struct s3c_audio_pdata i2sv3_pdata = { static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s5pv310_cfg_i2s, .cfg_gpio = exynos4_cfg_i2s,
.type = { .type = {
.i2s = { .i2s = {
.quirks = QUIRK_NO_MUXPSR, .quirks = QUIRK_NO_MUXPSR,
...@@ -104,10 +107,10 @@ static struct s3c_audio_pdata i2sv3_pdata = { ...@@ -104,10 +107,10 @@ static struct s3c_audio_pdata i2sv3_pdata = {
}, },
}; };
static struct resource s5pv310_i2s1_resource[] = { static struct resource exynos4_i2s1_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_I2S1, .start = EXYNOS4_PA_I2S1,
.end = S5PV310_PA_I2S1 + 0x100 - 1, .end = EXYNOS4_PA_I2S1 + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -122,20 +125,20 @@ static struct resource s5pv310_i2s1_resource[] = { ...@@ -122,20 +125,20 @@ static struct resource s5pv310_i2s1_resource[] = {
}, },
}; };
struct platform_device s5pv310_device_i2s1 = { struct platform_device exynos4_device_i2s1 = {
.name = "samsung-i2s", .name = "samsung-i2s",
.id = 1, .id = 1,
.num_resources = ARRAY_SIZE(s5pv310_i2s1_resource), .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
.resource = s5pv310_i2s1_resource, .resource = exynos4_i2s1_resource,
.dev = { .dev = {
.platform_data = &i2sv3_pdata, .platform_data = &i2sv3_pdata,
}, },
}; };
static struct resource s5pv310_i2s2_resource[] = { static struct resource exynos4_i2s2_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_I2S2, .start = EXYNOS4_PA_I2S2,
.end = S5PV310_PA_I2S2 + 0x100 - 1, .end = EXYNOS4_PA_I2S2 + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -150,11 +153,11 @@ static struct resource s5pv310_i2s2_resource[] = { ...@@ -150,11 +153,11 @@ static struct resource s5pv310_i2s2_resource[] = {
}, },
}; };
struct platform_device s5pv310_device_i2s2 = { struct platform_device exynos4_device_i2s2 = {
.name = "samsung-i2s", .name = "samsung-i2s",
.id = 2, .id = 2,
.num_resources = ARRAY_SIZE(s5pv310_i2s2_resource), .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
.resource = s5pv310_i2s2_resource, .resource = exynos4_i2s2_resource,
.dev = { .dev = {
.platform_data = &i2sv3_pdata, .platform_data = &i2sv3_pdata,
}, },
...@@ -162,17 +165,17 @@ struct platform_device s5pv310_device_i2s2 = { ...@@ -162,17 +165,17 @@ struct platform_device s5pv310_device_i2s2 = {
/* PCM Controller platform_devices */ /* PCM Controller platform_devices */
static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev) static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
{ {
switch (pdev->id) { switch (pdev->id) {
case 0: case 0:
s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3)); s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
break; break;
case 1: case 1:
s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3)); s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
break; break;
case 2: case 2:
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3)); s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
break; break;
default: default:
printk(KERN_DEBUG "Invalid PCM Controller number!"); printk(KERN_DEBUG "Invalid PCM Controller number!");
...@@ -183,13 +186,13 @@ static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev) ...@@ -183,13 +186,13 @@ static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
} }
static struct s3c_audio_pdata s3c_pcm_pdata = { static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5pv310_pcm_cfg_gpio, .cfg_gpio = exynos4_pcm_cfg_gpio,
}; };
static struct resource s5pv310_pcm0_resource[] = { static struct resource exynos4_pcm0_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_PCM0, .start = EXYNOS4_PA_PCM0,
.end = S5PV310_PA_PCM0 + 0x100 - 1, .end = EXYNOS4_PA_PCM0 + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -204,20 +207,20 @@ static struct resource s5pv310_pcm0_resource[] = { ...@@ -204,20 +207,20 @@ static struct resource s5pv310_pcm0_resource[] = {
}, },
}; };
struct platform_device s5pv310_device_pcm0 = { struct platform_device exynos4_device_pcm0 = {
.name = "samsung-pcm", .name = "samsung-pcm",
.id = 0, .id = 0,
.num_resources = ARRAY_SIZE(s5pv310_pcm0_resource), .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
.resource = s5pv310_pcm0_resource, .resource = exynos4_pcm0_resource,
.dev = { .dev = {
.platform_data = &s3c_pcm_pdata, .platform_data = &s3c_pcm_pdata,
}, },
}; };
static struct resource s5pv310_pcm1_resource[] = { static struct resource exynos4_pcm1_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_PCM1, .start = EXYNOS4_PA_PCM1,
.end = S5PV310_PA_PCM1 + 0x100 - 1, .end = EXYNOS4_PA_PCM1 + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -232,20 +235,20 @@ static struct resource s5pv310_pcm1_resource[] = { ...@@ -232,20 +235,20 @@ static struct resource s5pv310_pcm1_resource[] = {
}, },
}; };
struct platform_device s5pv310_device_pcm1 = { struct platform_device exynos4_device_pcm1 = {
.name = "samsung-pcm", .name = "samsung-pcm",
.id = 1, .id = 1,
.num_resources = ARRAY_SIZE(s5pv310_pcm1_resource), .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
.resource = s5pv310_pcm1_resource, .resource = exynos4_pcm1_resource,
.dev = { .dev = {
.platform_data = &s3c_pcm_pdata, .platform_data = &s3c_pcm_pdata,
}, },
}; };
static struct resource s5pv310_pcm2_resource[] = { static struct resource exynos4_pcm2_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_PCM2, .start = EXYNOS4_PA_PCM2,
.end = S5PV310_PA_PCM2 + 0x100 - 1, .end = EXYNOS4_PA_PCM2 + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -260,11 +263,11 @@ static struct resource s5pv310_pcm2_resource[] = { ...@@ -260,11 +263,11 @@ static struct resource s5pv310_pcm2_resource[] = {
}, },
}; };
struct platform_device s5pv310_device_pcm2 = { struct platform_device exynos4_device_pcm2 = {
.name = "samsung-pcm", .name = "samsung-pcm",
.id = 2, .id = 2,
.num_resources = ARRAY_SIZE(s5pv310_pcm2_resource), .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
.resource = s5pv310_pcm2_resource, .resource = exynos4_pcm2_resource,
.dev = { .dev = {
.platform_data = &s3c_pcm_pdata, .platform_data = &s3c_pcm_pdata,
}, },
...@@ -272,15 +275,15 @@ struct platform_device s5pv310_device_pcm2 = { ...@@ -272,15 +275,15 @@ struct platform_device s5pv310_device_pcm2 = {
/* AC97 Controller platform devices */ /* AC97 Controller platform devices */
static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev) static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
{ {
return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4)); return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
} }
static struct resource s5pv310_ac97_resource[] = { static struct resource exynos4_ac97_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_AC97, .start = EXYNOS4_PA_AC97,
.end = S5PV310_PA_AC97 + 0x100 - 1, .end = EXYNOS4_PA_AC97 + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -306,36 +309,36 @@ static struct resource s5pv310_ac97_resource[] = { ...@@ -306,36 +309,36 @@ static struct resource s5pv310_ac97_resource[] = {
}; };
static struct s3c_audio_pdata s3c_ac97_pdata = { static struct s3c_audio_pdata s3c_ac97_pdata = {
.cfg_gpio = s5pv310_ac97_cfg_gpio, .cfg_gpio = exynos4_ac97_cfg_gpio,
}; };
static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32); static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv310_device_ac97 = { struct platform_device exynos4_device_ac97 = {
.name = "samsung-ac97", .name = "samsung-ac97",
.id = -1, .id = -1,
.num_resources = ARRAY_SIZE(s5pv310_ac97_resource), .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
.resource = s5pv310_ac97_resource, .resource = exynos4_ac97_resource,
.dev = { .dev = {
.platform_data = &s3c_ac97_pdata, .platform_data = &s3c_ac97_pdata,
.dma_mask = &s5pv310_ac97_dmamask, .dma_mask = &exynos4_ac97_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32), .coherent_dma_mask = DMA_BIT_MASK(32),
}, },
}; };
/* S/PDIF Controller platform_device */ /* S/PDIF Controller platform_device */
static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev) static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
{ {
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3)); s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
return 0; return 0;
} }
static struct resource s5pv310_spdif_resource[] = { static struct resource exynos4_spdif_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_SPDIF, .start = EXYNOS4_PA_SPDIF,
.end = S5PV310_PA_SPDIF + 0x100 - 1, .end = EXYNOS4_PA_SPDIF + 0x100 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -346,19 +349,19 @@ static struct resource s5pv310_spdif_resource[] = { ...@@ -346,19 +349,19 @@ static struct resource s5pv310_spdif_resource[] = {
}; };
static struct s3c_audio_pdata samsung_spdif_pdata = { static struct s3c_audio_pdata samsung_spdif_pdata = {
.cfg_gpio = s5pv310_spdif_cfg_gpio, .cfg_gpio = exynos4_spdif_cfg_gpio,
}; };
static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32); static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv310_device_spdif = { struct platform_device exynos4_device_spdif = {
.name = "samsung-spdif", .name = "samsung-spdif",
.id = -1, .id = -1,
.num_resources = ARRAY_SIZE(s5pv310_spdif_resource), .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
.resource = s5pv310_spdif_resource, .resource = exynos4_spdif_resource,
.dev = { .dev = {
.platform_data = &samsung_spdif_pdata, .platform_data = &samsung_spdif_pdata,
.dma_mask = &s5pv310_spdif_dmamask, .dma_mask = &exynos4_spdif_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32), .coherent_dma_mask = DMA_BIT_MASK(32),
}, },
}; };
/* linux/arch/arm/mach-s5pv310/dev-pd.c /* linux/arch/arm/mach-exynos4/dev-pd.c
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* S5PV310 - Power Domain support * EXYNOS4 - Power Domain support
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
#include <plat/pd.h> #include <plat/pd.h>
static int s5pv310_pd_enable(struct device *dev) static int exynos4_pd_enable(struct device *dev)
{ {
struct samsung_pd_info *pdata = dev->platform_data; struct samsung_pd_info *pdata = dev->platform_data;
u32 timeout; u32 timeout;
...@@ -42,7 +42,7 @@ static int s5pv310_pd_enable(struct device *dev) ...@@ -42,7 +42,7 @@ static int s5pv310_pd_enable(struct device *dev)
return 0; return 0;
} }
static int s5pv310_pd_disable(struct device *dev) static int exynos4_pd_disable(struct device *dev)
{ {
struct samsung_pd_info *pdata = dev->platform_data; struct samsung_pd_info *pdata = dev->platform_data;
u32 timeout; u32 timeout;
...@@ -64,14 +64,14 @@ static int s5pv310_pd_disable(struct device *dev) ...@@ -64,14 +64,14 @@ static int s5pv310_pd_disable(struct device *dev)
return 0; return 0;
} }
struct platform_device s5pv310_device_pd[] = { struct platform_device exynos4_device_pd[] = {
{ {
.name = "samsung-pd", .name = "samsung-pd",
.id = 0, .id = 0,
.dev = { .dev = {
.platform_data = &(struct samsung_pd_info) { .platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable, .enable = exynos4_pd_enable,
.disable = s5pv310_pd_disable, .disable = exynos4_pd_disable,
.base = S5P_PMU_MFC_CONF, .base = S5P_PMU_MFC_CONF,
}, },
}, },
...@@ -80,8 +80,8 @@ struct platform_device s5pv310_device_pd[] = { ...@@ -80,8 +80,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 1, .id = 1,
.dev = { .dev = {
.platform_data = &(struct samsung_pd_info) { .platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable, .enable = exynos4_pd_enable,
.disable = s5pv310_pd_disable, .disable = exynos4_pd_disable,
.base = S5P_PMU_G3D_CONF, .base = S5P_PMU_G3D_CONF,
}, },
}, },
...@@ -90,8 +90,8 @@ struct platform_device s5pv310_device_pd[] = { ...@@ -90,8 +90,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 2, .id = 2,
.dev = { .dev = {
.platform_data = &(struct samsung_pd_info) { .platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable, .enable = exynos4_pd_enable,
.disable = s5pv310_pd_disable, .disable = exynos4_pd_disable,
.base = S5P_PMU_LCD0_CONF, .base = S5P_PMU_LCD0_CONF,
}, },
}, },
...@@ -100,8 +100,8 @@ struct platform_device s5pv310_device_pd[] = { ...@@ -100,8 +100,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 3, .id = 3,
.dev = { .dev = {
.platform_data = &(struct samsung_pd_info) { .platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable, .enable = exynos4_pd_enable,
.disable = s5pv310_pd_disable, .disable = exynos4_pd_disable,
.base = S5P_PMU_LCD1_CONF, .base = S5P_PMU_LCD1_CONF,
}, },
}, },
...@@ -110,8 +110,8 @@ struct platform_device s5pv310_device_pd[] = { ...@@ -110,8 +110,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 4, .id = 4,
.dev = { .dev = {
.platform_data = &(struct samsung_pd_info) { .platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable, .enable = exynos4_pd_enable,
.disable = s5pv310_pd_disable, .disable = exynos4_pd_disable,
.base = S5P_PMU_TV_CONF, .base = S5P_PMU_TV_CONF,
}, },
}, },
...@@ -120,8 +120,8 @@ struct platform_device s5pv310_device_pd[] = { ...@@ -120,8 +120,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 5, .id = 5,
.dev = { .dev = {
.platform_data = &(struct samsung_pd_info) { .platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable, .enable = exynos4_pd_enable,
.disable = s5pv310_pd_disable, .disable = exynos4_pd_disable,
.base = S5P_PMU_CAM_CONF, .base = S5P_PMU_CAM_CONF,
}, },
}, },
...@@ -130,8 +130,8 @@ struct platform_device s5pv310_device_pd[] = { ...@@ -130,8 +130,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 6, .id = 6,
.dev = { .dev = {
.platform_data = &(struct samsung_pd_info) { .platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable, .enable = exynos4_pd_enable,
.disable = s5pv310_pd_disable, .disable = exynos4_pd_disable,
.base = S5P_PMU_GPS_CONF, .base = S5P_PMU_GPS_CONF,
}, },
}, },
......
/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c /* linux/arch/arm/mach-exynos4/dev-sysmmu.c
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* EXYNOS4 - System MMU support
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
...@@ -13,11 +15,33 @@ ...@@ -13,11 +15,33 @@
#include <mach/map.h> #include <mach/map.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/sysmmu.h>
#include <plat/s5p-clock.h>
/* These names must be equal to the clock names in mach-exynos4/clock.c */
const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
"SYSMMU_MDMA" ,
"SYSMMU_SSS" ,
"SYSMMU_FIMC0" ,
"SYSMMU_FIMC1" ,
"SYSMMU_FIMC2" ,
"SYSMMU_FIMC3" ,
"SYSMMU_JPEG" ,
"SYSMMU_FIMD0" ,
"SYSMMU_FIMD1" ,
"SYSMMU_PCIe" ,
"SYSMMU_G2D" ,
"SYSMMU_ROTATOR",
"SYSMMU_MDMA2" ,
"SYSMMU_TV" ,
"SYSMMU_MFC_L" ,
"SYSMMU_MFC_R" ,
};
static struct resource s5pv310_sysmmu_resource[] = { static struct resource exynos4_sysmmu_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_SYSMMU_MDMA, .start = EXYNOS4_PA_SYSMMU_MDMA,
.end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -26,8 +50,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -26,8 +50,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[2] = { [2] = {
.start = S5PV310_PA_SYSMMU_SSS, .start = EXYNOS4_PA_SYSMMU_SSS,
.end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[3] = { [3] = {
...@@ -36,8 +60,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -36,8 +60,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[4] = { [4] = {
.start = S5PV310_PA_SYSMMU_FIMC0, .start = EXYNOS4_PA_SYSMMU_FIMC0,
.end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[5] = { [5] = {
...@@ -46,8 +70,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -46,8 +70,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[6] = { [6] = {
.start = S5PV310_PA_SYSMMU_FIMC1, .start = EXYNOS4_PA_SYSMMU_FIMC1,
.end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[7] = { [7] = {
...@@ -56,8 +80,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -56,8 +80,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[8] = { [8] = {
.start = S5PV310_PA_SYSMMU_FIMC2, .start = EXYNOS4_PA_SYSMMU_FIMC2,
.end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[9] = { [9] = {
...@@ -66,8 +90,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -66,8 +90,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[10] = { [10] = {
.start = S5PV310_PA_SYSMMU_FIMC3, .start = EXYNOS4_PA_SYSMMU_FIMC3,
.end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[11] = { [11] = {
...@@ -76,8 +100,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -76,8 +100,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[12] = { [12] = {
.start = S5PV310_PA_SYSMMU_JPEG, .start = EXYNOS4_PA_SYSMMU_JPEG,
.end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[13] = { [13] = {
...@@ -86,8 +110,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -86,8 +110,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[14] = { [14] = {
.start = S5PV310_PA_SYSMMU_FIMD0, .start = EXYNOS4_PA_SYSMMU_FIMD0,
.end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[15] = { [15] = {
...@@ -96,8 +120,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -96,8 +120,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[16] = { [16] = {
.start = S5PV310_PA_SYSMMU_FIMD1, .start = EXYNOS4_PA_SYSMMU_FIMD1,
.end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[17] = { [17] = {
...@@ -106,8 +130,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -106,8 +130,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[18] = { [18] = {
.start = S5PV310_PA_SYSMMU_PCIe, .start = EXYNOS4_PA_SYSMMU_PCIe,
.end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[19] = { [19] = {
...@@ -116,8 +140,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -116,8 +140,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[20] = { [20] = {
.start = S5PV310_PA_SYSMMU_G2D, .start = EXYNOS4_PA_SYSMMU_G2D,
.end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[21] = { [21] = {
...@@ -126,8 +150,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -126,8 +150,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[22] = { [22] = {
.start = S5PV310_PA_SYSMMU_ROTATOR, .start = EXYNOS4_PA_SYSMMU_ROTATOR,
.end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[23] = { [23] = {
...@@ -136,8 +160,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -136,8 +160,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[24] = { [24] = {
.start = S5PV310_PA_SYSMMU_MDMA2, .start = EXYNOS4_PA_SYSMMU_MDMA2,
.end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[25] = { [25] = {
...@@ -146,8 +170,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -146,8 +170,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[26] = { [26] = {
.start = S5PV310_PA_SYSMMU_TV, .start = EXYNOS4_PA_SYSMMU_TV,
.end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[27] = { [27] = {
...@@ -156,8 +180,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -156,8 +180,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[28] = { [28] = {
.start = S5PV310_PA_SYSMMU_MFC_L, .start = EXYNOS4_PA_SYSMMU_MFC_L,
.end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[29] = { [29] = {
...@@ -166,8 +190,8 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -166,8 +190,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
[30] = { [30] = {
.start = S5PV310_PA_SYSMMU_MFC_R, .start = EXYNOS4_PA_SYSMMU_MFC_R,
.end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1, .end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[31] = { [31] = {
...@@ -177,11 +201,32 @@ static struct resource s5pv310_sysmmu_resource[] = { ...@@ -177,11 +201,32 @@ static struct resource s5pv310_sysmmu_resource[] = {
}, },
}; };
struct platform_device s5pv310_device_sysmmu = { struct platform_device exynos4_device_sysmmu = {
.name = "s5p-sysmmu", .name = "s5p-sysmmu",
.id = 32, .id = 32,
.num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource), .num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
.resource = s5pv310_sysmmu_resource, .resource = exynos4_sysmmu_resource,
}; };
EXPORT_SYMBOL(exynos4_device_sysmmu);
static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
{
sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
if (IS_ERR(sysmmu_clk[ips]))
sysmmu_clk[ips] = NULL;
else
clk_put(sysmmu_clk[ips]);
}
void sysmmu_clk_enable(sysmmu_ips ips)
{
if (sysmmu_clk[ips])
clk_enable(sysmmu_clk[ips]);
}
EXPORT_SYMBOL(s5pv310_device_sysmmu); void sysmmu_clk_disable(sysmmu_ips ips)
{
if (sysmmu_clk[ips])
clk_disable(sysmmu_clk[ips]);
}
/* /* linux/arch/arm/mach-exynos4/dma.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com> * Jaswinder Singh <jassi.brar@samsung.com>
* *
...@@ -30,10 +34,10 @@ ...@@ -30,10 +34,10 @@
static u64 dma_dmamask = DMA_BIT_MASK(32); static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5pv310_pdma0_resource[] = { static struct resource exynos4_pdma0_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_PDMA0, .start = EXYNOS4_PA_PDMA0,
.end = S5PV310_PA_PDMA0 + SZ_4K, .end = EXYNOS4_PA_PDMA0 + SZ_4K,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = { ...@@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = {
}, },
}; };
static struct s3c_pl330_platdata s5pv310_pdma0_pdata = { static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
.peri = { .peri = {
[0] = DMACH_PCM0_RX, [0] = DMACH_PCM0_RX,
[1] = DMACH_PCM0_TX, [1] = DMACH_PCM0_TX,
...@@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = { ...@@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
}, },
}; };
static struct platform_device s5pv310_device_pdma0 = { static struct platform_device exynos4_device_pdma0 = {
.name = "s3c-pl330", .name = "s3c-pl330",
.id = 0, .id = 0,
.num_resources = ARRAY_SIZE(s5pv310_pdma0_resource), .num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
.resource = s5pv310_pdma0_resource, .resource = exynos4_pdma0_resource,
.dev = { .dev = {
.dma_mask = &dma_dmamask, .dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32), .coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv310_pdma0_pdata, .platform_data = &exynos4_pdma0_pdata,
}, },
}; };
static struct resource s5pv310_pdma1_resource[] = { static struct resource exynos4_pdma1_resource[] = {
[0] = { [0] = {
.start = S5PV310_PA_PDMA1, .start = EXYNOS4_PA_PDMA1,
.end = S5PV310_PA_PDMA1 + SZ_4K, .end = EXYNOS4_PA_PDMA1 + SZ_4K,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
...@@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = { ...@@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = {
}, },
}; };
static struct s3c_pl330_platdata s5pv310_pdma1_pdata = { static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
.peri = { .peri = {
[0] = DMACH_PCM0_RX, [0] = DMACH_PCM0_RX,
[1] = DMACH_PCM0_TX, [1] = DMACH_PCM0_TX,
...@@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = { ...@@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
}, },
}; };
static struct platform_device s5pv310_device_pdma1 = { static struct platform_device exynos4_device_pdma1 = {
.name = "s3c-pl330", .name = "s3c-pl330",
.id = 1, .id = 1,
.num_resources = ARRAY_SIZE(s5pv310_pdma1_resource), .num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
.resource = s5pv310_pdma1_resource, .resource = exynos4_pdma1_resource,
.dev = { .dev = {
.dma_mask = &dma_dmamask, .dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32), .coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv310_pdma1_pdata, .platform_data = &exynos4_pdma1_pdata,
}, },
}; };
static struct platform_device *s5pv310_dmacs[] __initdata = { static struct platform_device *exynos4_dmacs[] __initdata = {
&s5pv310_device_pdma0, &exynos4_device_pdma0,
&s5pv310_device_pdma1, &exynos4_device_pdma1,
}; };
static int __init s5pv310_dma_init(void) static int __init exynos4_dma_init(void)
{ {
platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs)); platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
return 0; return 0;
} }
arch_initcall(s5pv310_dma_init); arch_initcall(exynos4_dma_init);
/* linux/arch/arm/mach-s5pv310/gpiolib.c /* linux/arch/arm/mach-exynos4/gpiolib.c
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* S5PV310 - GPIOlib support * EXYNOS4 - GPIOlib support
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -43,168 +43,217 @@ static struct s3c_gpio_cfg gpio_cfg_noint = { ...@@ -43,168 +43,217 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
* Note: The initialization of 'base' member of s3c_gpio_chip structure * Note: The initialization of 'base' member of s3c_gpio_chip structure
* uses the above macro and depends on the banks being listed in order here. * uses the above macro and depends on the banks being listed in order here.
*/ */
static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = { static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
{ {
.chip = { .chip = {
.base = S5PV310_GPA0(0), .base = EXYNOS4_GPA0(0),
.ngpio = S5PV310_GPIO_A0_NR, .ngpio = EXYNOS4_GPIO_A0_NR,
.label = "GPA0", .label = "GPA0",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPA1(0), .base = EXYNOS4_GPA1(0),
.ngpio = S5PV310_GPIO_A1_NR, .ngpio = EXYNOS4_GPIO_A1_NR,
.label = "GPA1", .label = "GPA1",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPB(0), .base = EXYNOS4_GPB(0),
.ngpio = S5PV310_GPIO_B_NR, .ngpio = EXYNOS4_GPIO_B_NR,
.label = "GPB", .label = "GPB",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPC0(0), .base = EXYNOS4_GPC0(0),
.ngpio = S5PV310_GPIO_C0_NR, .ngpio = EXYNOS4_GPIO_C0_NR,
.label = "GPC0", .label = "GPC0",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPC1(0), .base = EXYNOS4_GPC1(0),
.ngpio = S5PV310_GPIO_C1_NR, .ngpio = EXYNOS4_GPIO_C1_NR,
.label = "GPC1", .label = "GPC1",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPD0(0), .base = EXYNOS4_GPD0(0),
.ngpio = S5PV310_GPIO_D0_NR, .ngpio = EXYNOS4_GPIO_D0_NR,
.label = "GPD0", .label = "GPD0",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPD1(0), .base = EXYNOS4_GPD1(0),
.ngpio = S5PV310_GPIO_D1_NR, .ngpio = EXYNOS4_GPIO_D1_NR,
.label = "GPD1", .label = "GPD1",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPE0(0), .base = EXYNOS4_GPE0(0),
.ngpio = S5PV310_GPIO_E0_NR, .ngpio = EXYNOS4_GPIO_E0_NR,
.label = "GPE0", .label = "GPE0",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPE1(0), .base = EXYNOS4_GPE1(0),
.ngpio = S5PV310_GPIO_E1_NR, .ngpio = EXYNOS4_GPIO_E1_NR,
.label = "GPE1", .label = "GPE1",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPE2(0), .base = EXYNOS4_GPE2(0),
.ngpio = S5PV310_GPIO_E2_NR, .ngpio = EXYNOS4_GPIO_E2_NR,
.label = "GPE2", .label = "GPE2",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPE3(0), .base = EXYNOS4_GPE3(0),
.ngpio = S5PV310_GPIO_E3_NR, .ngpio = EXYNOS4_GPIO_E3_NR,
.label = "GPE3", .label = "GPE3",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPE4(0), .base = EXYNOS4_GPE4(0),
.ngpio = S5PV310_GPIO_E4_NR, .ngpio = EXYNOS4_GPIO_E4_NR,
.label = "GPE4", .label = "GPE4",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPF0(0), .base = EXYNOS4_GPF0(0),
.ngpio = S5PV310_GPIO_F0_NR, .ngpio = EXYNOS4_GPIO_F0_NR,
.label = "GPF0", .label = "GPF0",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPF1(0), .base = EXYNOS4_GPF1(0),
.ngpio = S5PV310_GPIO_F1_NR, .ngpio = EXYNOS4_GPIO_F1_NR,
.label = "GPF1", .label = "GPF1",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPF2(0), .base = EXYNOS4_GPF2(0),
.ngpio = S5PV310_GPIO_F2_NR, .ngpio = EXYNOS4_GPIO_F2_NR,
.label = "GPF2", .label = "GPF2",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPF3(0), .base = EXYNOS4_GPF3(0),
.ngpio = S5PV310_GPIO_F3_NR, .ngpio = EXYNOS4_GPIO_F3_NR,
.label = "GPF3", .label = "GPF3",
}, },
}, },
}; };
static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
{ {
.chip = { .chip = {
.base = S5PV310_GPJ0(0), .base = EXYNOS4_GPJ0(0),
.ngpio = S5PV310_GPIO_J0_NR, .ngpio = EXYNOS4_GPIO_J0_NR,
.label = "GPJ0", .label = "GPJ0",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPJ1(0), .base = EXYNOS4_GPJ1(0),
.ngpio = S5PV310_GPIO_J1_NR, .ngpio = EXYNOS4_GPIO_J1_NR,
.label = "GPJ1", .label = "GPJ1",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPK0(0), .base = EXYNOS4_GPK0(0),
.ngpio = S5PV310_GPIO_K0_NR, .ngpio = EXYNOS4_GPIO_K0_NR,
.label = "GPK0", .label = "GPK0",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPK1(0), .base = EXYNOS4_GPK1(0),
.ngpio = S5PV310_GPIO_K1_NR, .ngpio = EXYNOS4_GPIO_K1_NR,
.label = "GPK1", .label = "GPK1",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPK2(0), .base = EXYNOS4_GPK2(0),
.ngpio = S5PV310_GPIO_K2_NR, .ngpio = EXYNOS4_GPIO_K2_NR,
.label = "GPK2", .label = "GPK2",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPK3(0), .base = EXYNOS4_GPK3(0),
.ngpio = S5PV310_GPIO_K3_NR, .ngpio = EXYNOS4_GPIO_K3_NR,
.label = "GPK3", .label = "GPK3",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPL0(0), .base = EXYNOS4_GPL0(0),
.ngpio = S5PV310_GPIO_L0_NR, .ngpio = EXYNOS4_GPIO_L0_NR,
.label = "GPL0", .label = "GPL0",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPL1(0), .base = EXYNOS4_GPL1(0),
.ngpio = S5PV310_GPIO_L1_NR, .ngpio = EXYNOS4_GPIO_L1_NR,
.label = "GPL1", .label = "GPL1",
}, },
}, { }, {
.chip = { .chip = {
.base = S5PV310_GPL2(0), .base = EXYNOS4_GPL2(0),
.ngpio = S5PV310_GPIO_L2_NR, .ngpio = EXYNOS4_GPIO_L2_NR,
.label = "GPL2", .label = "GPL2",
}, },
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY0(0),
.ngpio = EXYNOS4_GPIO_Y0_NR,
.label = "GPY0",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY1(0),
.ngpio = EXYNOS4_GPIO_Y1_NR,
.label = "GPY1",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY2(0),
.ngpio = EXYNOS4_GPIO_Y2_NR,
.label = "GPY2",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY3(0),
.ngpio = EXYNOS4_GPIO_Y3_NR,
.label = "GPY3",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY4(0),
.ngpio = EXYNOS4_GPIO_Y4_NR,
.label = "GPY4",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY5(0),
.ngpio = EXYNOS4_GPIO_Y5_NR,
.label = "GPY5",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY6(0),
.ngpio = EXYNOS4_GPIO_Y6_NR,
.label = "GPY6",
},
}, { }, {
.base = (S5P_VA_GPIO2 + 0xC00), .base = (S5P_VA_GPIO2 + 0xC00),
.config = &gpio_cfg_noint, .config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(0), .irq_base = IRQ_EINT(0),
.chip = { .chip = {
.base = S5PV310_GPX0(0), .base = EXYNOS4_GPX0(0),
.ngpio = S5PV310_GPIO_X0_NR, .ngpio = EXYNOS4_GPIO_X0_NR,
.label = "GPX0", .label = "GPX0",
.to_irq = samsung_gpiolib_to_irq, .to_irq = samsung_gpiolib_to_irq,
}, },
...@@ -213,8 +262,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { ...@@ -213,8 +262,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint, .config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(8), .irq_base = IRQ_EINT(8),
.chip = { .chip = {
.base = S5PV310_GPX1(0), .base = EXYNOS4_GPX1(0),
.ngpio = S5PV310_GPIO_X1_NR, .ngpio = EXYNOS4_GPIO_X1_NR,
.label = "GPX1", .label = "GPX1",
.to_irq = samsung_gpiolib_to_irq, .to_irq = samsung_gpiolib_to_irq,
}, },
...@@ -223,8 +272,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { ...@@ -223,8 +272,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint, .config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(16), .irq_base = IRQ_EINT(16),
.chip = { .chip = {
.base = S5PV310_GPX2(0), .base = EXYNOS4_GPX2(0),
.ngpio = S5PV310_GPIO_X2_NR, .ngpio = EXYNOS4_GPIO_X2_NR,
.label = "GPX2", .label = "GPX2",
.to_irq = samsung_gpiolib_to_irq, .to_irq = samsung_gpiolib_to_irq,
}, },
...@@ -233,72 +282,84 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { ...@@ -233,72 +282,84 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint, .config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(24), .irq_base = IRQ_EINT(24),
.chip = { .chip = {
.base = S5PV310_GPX3(0), .base = EXYNOS4_GPX3(0),
.ngpio = S5PV310_GPIO_X3_NR, .ngpio = EXYNOS4_GPIO_X3_NR,
.label = "GPX3", .label = "GPX3",
.to_irq = samsung_gpiolib_to_irq, .to_irq = samsung_gpiolib_to_irq,
}, },
}, },
}; };
static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = { static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
{ {
.chip = { .chip = {
.base = S5PV310_GPZ(0), .base = EXYNOS4_GPZ(0),
.ngpio = S5PV310_GPIO_Z_NR, .ngpio = EXYNOS4_GPIO_Z_NR,
.label = "GPZ", .label = "GPZ",
}, },
}, },
}; };
static __init int s5pv310_gpiolib_init(void) static __init int exynos4_gpiolib_init(void)
{ {
struct s3c_gpio_chip *chip; struct s3c_gpio_chip *chip;
int i; int i;
int group = 0;
int nr_chips; int nr_chips;
/* GPIO part 1 */ /* GPIO part 1 */
chip = s5pv310_gpio_part1_4bit; chip = exynos4_gpio_part1_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit); nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
for (i = 0; i < nr_chips; i++, chip++) { for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL) if (chip->config == NULL) {
chip->config = &gpio_cfg; chip->config = &gpio_cfg;
/* Assign the GPIO interrupt group */
chip->group = group++;
}
if (chip->base == NULL) if (chip->base == NULL)
chip->base = S5P_VA_GPIO1 + (i) * 0x20; chip->base = S5P_VA_GPIO1 + (i) * 0x20;
} }
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips); samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
/* GPIO part 2 */ /* GPIO part 2 */
chip = s5pv310_gpio_part2_4bit; chip = exynos4_gpio_part2_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit); nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
for (i = 0; i < nr_chips; i++, chip++) { for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL) if (chip->config == NULL) {
chip->config = &gpio_cfg; chip->config = &gpio_cfg;
/* Assign the GPIO interrupt group */
chip->group = group++;
}
if (chip->base == NULL) if (chip->base == NULL)
chip->base = S5P_VA_GPIO2 + (i) * 0x20; chip->base = S5P_VA_GPIO2 + (i) * 0x20;
} }
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips); samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
/* GPIO part 3 */ /* GPIO part 3 */
chip = s5pv310_gpio_part3_4bit; chip = exynos4_gpio_part3_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit); nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
for (i = 0; i < nr_chips; i++, chip++) { for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL) if (chip->config == NULL) {
chip->config = &gpio_cfg; chip->config = &gpio_cfg;
/* Assign the GPIO interrupt group */
chip->group = group++;
}
if (chip->base == NULL) if (chip->base == NULL)
chip->base = S5P_VA_GPIO3 + (i) * 0x20; chip->base = S5P_VA_GPIO3 + (i) * 0x20;
} }
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips); samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
return 0; return 0;
} }
core_initcall(s5pv310_gpiolib_init); core_initcall(exynos4_gpiolib_init);
/* /*
* linux/arch/arm/mach-s5pv310/headsmp.S * linux/arch/arm/mach-exynos4/headsmp.S
* *
* Cloned from linux/arch/arm/mach-realview/headsmp.S * Cloned from linux/arch/arm/mach-realview/headsmp.S
* *
...@@ -16,11 +16,11 @@ ...@@ -16,11 +16,11 @@
__INIT __INIT
/* /*
* s5pv310 specific entry point for secondary CPUs. This provides * exynos4 specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're * a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise. * ready for them to initialise.
*/ */
ENTRY(s5pv310_secondary_startup) ENTRY(exynos4_secondary_startup)
mrc p15, 0, r0, c0, c0, 5 mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15 and r0, r0, #15
adr r4, 1f adr r4, 1f
......
/* linux arch/arm/mach-s5pv310/hotplug.c /* linux arch/arm/mach-exynos4/hotplug.c
* *
* Cloned from linux/arch/arm/mach-realview/hotplug.c * Cloned from linux/arch/arm/mach-realview/hotplug.c
* *
...@@ -30,13 +30,13 @@ static inline void cpu_enter_lowpower(void) ...@@ -30,13 +30,13 @@ static inline void cpu_enter_lowpower(void)
* Turn off coherency * Turn off coherency
*/ */
" mrc p15, 0, %0, c1, c0, 1\n" " mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, #0x20\n" " bic %0, %0, %3\n"
" mcr p15, 0, %0, c1, c0, 1\n" " mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n" " mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n" " bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n" " mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v) : "=&r" (v)
: "r" (0), "Ir" (CR_C) : "r" (0), "Ir" (CR_C), "Ir" (0x40)
: "cc"); : "cc");
} }
...@@ -49,10 +49,10 @@ static inline void cpu_leave_lowpower(void) ...@@ -49,10 +49,10 @@ static inline void cpu_leave_lowpower(void)
" orr %0, %0, %1\n" " orr %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n" " mcr p15, 0, %0, c1, c0, 0\n"
" mrc p15, 0, %0, c1, c0, 1\n" " mrc p15, 0, %0, c1, c0, 1\n"
" orr %0, %0, #0x20\n" " orr %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 1\n" " mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v) : "=&r" (v)
: "Ir" (CR_C) : "Ir" (CR_C), "Ir" (0x40)
: "cc"); : "cc");
} }
......
/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S /* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
* *
......
/* arch/arm/mach-s5pv310/include/mach/entry-macro.S /* arch/arm/mach-exynos4/include/mach/entry-macro.S
* *
* Cloned from arch/arm/mach-realview/include/mach/entry-macro.S * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
* *
* Low-level IRQ helper macros for S5PV310 platforms * Low-level IRQ helper macros for EXYNOS4 platforms
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
......
/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
/* GPIO bank sizes */
#define EXYNOS4_GPIO_A0_NR (8)
#define EXYNOS4_GPIO_A1_NR (6)
#define EXYNOS4_GPIO_B_NR (8)
#define EXYNOS4_GPIO_C0_NR (5)
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
#define EXYNOS4_GPIO_E0_NR (5)
#define EXYNOS4_GPIO_E1_NR (8)
#define EXYNOS4_GPIO_E2_NR (6)
#define EXYNOS4_GPIO_E3_NR (8)
#define EXYNOS4_GPIO_E4_NR (8)
#define EXYNOS4_GPIO_F0_NR (8)
#define EXYNOS4_GPIO_F1_NR (8)
#define EXYNOS4_GPIO_F2_NR (8)
#define EXYNOS4_GPIO_F3_NR (6)
#define EXYNOS4_GPIO_J0_NR (8)
#define EXYNOS4_GPIO_J1_NR (5)
#define EXYNOS4_GPIO_K0_NR (7)
#define EXYNOS4_GPIO_K1_NR (7)
#define EXYNOS4_GPIO_K2_NR (7)
#define EXYNOS4_GPIO_K3_NR (7)
#define EXYNOS4_GPIO_L0_NR (8)
#define EXYNOS4_GPIO_L1_NR (3)
#define EXYNOS4_GPIO_L2_NR (8)
#define EXYNOS4_GPIO_X0_NR (8)
#define EXYNOS4_GPIO_X1_NR (8)
#define EXYNOS4_GPIO_X2_NR (8)
#define EXYNOS4_GPIO_X3_NR (8)
#define EXYNOS4_GPIO_Y0_NR (6)
#define EXYNOS4_GPIO_Y1_NR (4)
#define EXYNOS4_GPIO_Y2_NR (6)
#define EXYNOS4_GPIO_Y3_NR (8)
#define EXYNOS4_GPIO_Y4_NR (8)
#define EXYNOS4_GPIO_Y5_NR (8)
#define EXYNOS4_GPIO_Y6_NR (8)
#define EXYNOS4_GPIO_Z_NR (7)
/* GPIO bank numbers */
#define EXYNOS4_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p_gpio_number {
EXYNOS4_GPIO_A0_START = 0,
EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
EXYNOS4_GPIO_Y0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
EXYNOS4_GPIO_Y1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
EXYNOS4_GPIO_Y2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
EXYNOS4_GPIO_Y3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
EXYNOS4_GPIO_Y4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
EXYNOS4_GPIO_Y5_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
EXYNOS4_GPIO_Y6_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
};
/* EXYNOS4 GPIO number definitions */
#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
/* the end of the EXYNOS4 specific gpios */
#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
#define S3C_GPIO_END EXYNOS4_GPIO_END
/* define the number of gpios we need to the one after the GPZ() range */
#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */
/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h /* linux/arch/arm/mach-exynos4/include/mach/hardware.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* S5PV310 - Hardware support * EXYNOS4 - Hardware support
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-s5pv310/include/mach/io.h /* linux/arch/arm/mach-exynos4/include/mach/io.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org> * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
* *
* Based on arch/arm/mach-s5p6442/include/mach/io.h * Based on arch/arm/mach-s5p6442/include/mach/io.h
* *
* Default IO routines for S5PV310 * Default IO routines for EXYNOS4
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h /* linux/arch/arm/mach-exynos4/include/mach/irqs.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* S5PV310 - IRQ definitions * EXYNOS4 - IRQ definitions
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -85,6 +85,9 @@ ...@@ -85,6 +85,9 @@
#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0) #define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
#define IRQ_RTC_TIC COMBINER_IRQ(23, 1) #define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
#define IRQ_UART0 COMBINER_IRQ(26, 0) #define IRQ_UART0 COMBINER_IRQ(26, 0)
#define IRQ_UART1 COMBINER_IRQ(26, 1) #define IRQ_UART1 COMBINER_IRQ(26, 1)
#define IRQ_UART2 COMBINER_IRQ(26, 2) #define IRQ_UART2 COMBINER_IRQ(26, 2)
...@@ -108,6 +111,11 @@ ...@@ -108,6 +111,11 @@
#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0) #define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1) #define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
#define IRQ_MCT_L1 COMBINER_IRQ(35, 3) #define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
...@@ -131,6 +139,7 @@ ...@@ -131,6 +139,7 @@
#define IRQ_MCT_L0 COMBINER_IRQ(51, 0) #define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
#define IRQ_WDT COMBINER_IRQ(53, 0) #define IRQ_WDT COMBINER_IRQ(53, 0)
#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
#define MAX_COMBINER_NR 54 #define MAX_COMBINER_NR 54
...@@ -139,8 +148,13 @@ ...@@ -139,8 +148,13 @@
#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) #define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) #define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
/* Set the default NR_IRQS */ /* optional GPIO interrupts */
#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32)
#define IRQ_GPIO1_NR_GROUPS 16
#define IRQ_GPIO2_NR_GROUPS 9
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
#define NR_IRQS (S5P_IRQ_EINT_BASE + 32) /* Set the default NR_IRQS */
#define NR_IRQS (IRQ_GPIO_END)
#endif /* __ASM_ARCH_IRQS_H */ #endif /* __ASM_ARCH_IRQS_H */
/* linux/arch/arm/mach-exynos4/include/mach/map.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
/*
* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
* So need to define it, and here is to avoid redefinition warning.
*/
#define S3C_UART_OFFSET (0x10000)
#include <plat/map-s5p.h>
#define EXYNOS4_PA_SYSRAM 0x02020000
#define EXYNOS4_PA_FIMC0 0x11800000
#define EXYNOS4_PA_FIMC1 0x11810000
#define EXYNOS4_PA_FIMC2 0x11820000
#define EXYNOS4_PA_FIMC3 0x11830000
#define EXYNOS4_PA_I2S0 0x03830000
#define EXYNOS4_PA_I2S1 0xE3100000
#define EXYNOS4_PA_I2S2 0xE2A00000
#define EXYNOS4_PA_PCM0 0x03840000
#define EXYNOS4_PA_PCM1 0x13980000
#define EXYNOS4_PA_PCM2 0x13990000
#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
#define EXYNOS4_PA_ONENAND 0x0C000000
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
#define EXYNOS4_PA_CHIPID 0x10000000
#define EXYNOS4_PA_SYSCON 0x10010000
#define EXYNOS4_PA_PMU 0x10020000
#define EXYNOS4_PA_CMU 0x10030000
#define EXYNOS4_PA_SYSTIMER 0x10050000
#define EXYNOS4_PA_WATCHDOG 0x10060000
#define EXYNOS4_PA_RTC 0x10070000
#define EXYNOS4_PA_KEYPAD 0x100A0000
#define EXYNOS4_PA_DMC0 0x10400000
#define EXYNOS4_PA_COMBINER 0x10448000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_GIC_CPU 0x10500100
#define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_GIC_DIST 0x10501000
#define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_MDMA 0x10810000
#define EXYNOS4_PA_PDMA0 0x12680000
#define EXYNOS4_PA_PDMA1 0x12690000
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
#define EXYNOS4_PA_GPIO1 0x11400000
#define EXYNOS4_PA_GPIO2 0x11000000
#define EXYNOS4_PA_GPIO3 0x03860000
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define EXYNOS4_PA_SATA 0x12560000
#define EXYNOS4_PA_SATAPHY 0x125D0000
#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
#define EXYNOS4_PA_SROMC 0x12570000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS4_PA_AC97 0x139A0000
#define EXYNOS4_PA_SPDIF 0x139B0000
#define EXYNOS4_PA_TIMER 0x139D0000
#define EXYNOS4_PA_SDRAM 0x40000000
/* Compatibiltiy Defines */
#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_SROMC EXYNOS4_PA_SROMC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
/* UART */
#define S3C_PA_UART EXYNOS4_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#define S5P_PA_UART4 S5P_PA_UART(4)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */
/* linux/arch/arm/mach-s5pv310/include/mach/memory.h /* linux/arch/arm/mach-exynos4/include/mach/memory.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* S5PV310 - Memory definitions * EXYNOS4 - Memory definitions
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/regs-pmu.h>
static inline void s3c_pm_debug_init_uart(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_prepare_irqs(void)
{
unsigned int tmp;
tmp = __raw_readl(S5P_WAKEUP_MASK);
tmp &= ~(1 << 31);
__raw_writel(tmp, S5P_WAKEUP_MASK);
__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
}
static inline void s3c_pm_arch_stop_clocks(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_show_resume_irqs(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
/* nothing here yet */
}
/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h /* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* Copyright 2008 Openmoko, Inc. * Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics * Copyright 2008 Simtec Electronics
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
* *
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
* *
* S5PV310 - pwm clock and timer support * EXYNOS4 - pwm clock and timer support
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h /* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* S5PV310 - Clock register definitions * EXYNOS4 - Clock register definitions
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -17,13 +17,13 @@ ...@@ -17,13 +17,13 @@
#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) #define S5P_CLKREG(x) (S5P_VA_CMU + (x))
#define S5P_INFORM0 S5P_CLKREG(0x800)
#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) #define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) #define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800)
#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) #define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) #define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
...@@ -33,18 +33,24 @@ ...@@ -33,18 +33,24 @@
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) #define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) #define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) #define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) #define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) #define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) #define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) #define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) #define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) #define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
...@@ -58,25 +64,36 @@ ...@@ -58,25 +64,36 @@
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) #define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) #define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) #define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) #define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) #define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) #define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) #define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) #define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) #define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) #define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) #define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504)
#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) #define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000) #define S5P_APLL_LOCK S5P_CLKREG(0x14000)
#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) #define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
...@@ -94,21 +111,18 @@ ...@@ -94,21 +111,18 @@
#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) #define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900)
/* APLL_LOCK */
#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ #define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
/* APLL_CON0 */
#define S5P_APLLCON0_ENABLE_SHIFT (31) #define S5P_APLLCON0_ENABLE_SHIFT (31)
#define S5P_APLLCON0_LOCKED_SHIFT (29) #define S5P_APLLCON0_LOCKED_SHIFT (29)
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) #define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) #define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
/* CLK_SRC_CPU */
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) #define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) #define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
/* CLKDIV_CPU0 */
#define S5P_CLKDIV_CPU0_CORE_SHIFT (0) #define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) #define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) #define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
...@@ -124,7 +138,6 @@ ...@@ -124,7 +138,6 @@
#define S5P_CLKDIV_CPU0_APLL_SHIFT (24) #define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) #define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
/* CLKDIV_DMC0 */
#define S5P_CLKDIV_DMC0_ACP_SHIFT (0) #define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) #define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) #define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
...@@ -142,7 +155,6 @@ ...@@ -142,7 +155,6 @@
#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) #define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) #define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
/* CLKDIV_TOP */
#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) #define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) #define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) #define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
...@@ -154,13 +166,14 @@ ...@@ -154,13 +166,14 @@
#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) #define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) #define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
#define S5P_CLKDIV_BUS_GDLR_SHIFT (0) #define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) #define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) #define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) #define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
/* Compatibility defines */ /* Compatibility defines and inclusion */
#include <mach/regs-pmu.h>
#define S5P_EPLL_CON S5P_EPLL_CON0 #define S5P_EPLL_CON S5P_EPLL_CON0
......
/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h /* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* S5PV310 - GPIO (including EINT) register definitions * EXYNOS4 - GPIO (including EINT) register definitions
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -16,17 +16,17 @@ ...@@ -16,17 +16,17 @@
#include <mach/map.h> #include <mach/map.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00) #define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4)) #define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80) #define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4)) #define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00) #define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4)) #define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40) #define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4)) #define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) #define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
...@@ -34,9 +34,9 @@ ...@@ -34,9 +34,9 @@
#define EINT_MODE S3C_GPIO_SFN(0xf) #define EINT_MODE S3C_GPIO_SFN(0xf)
#define EINT_GPIO_0(x) S5PV310_GPX0(x) #define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
#define EINT_GPIO_1(x) S5PV310_GPX1(x) #define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
#define EINT_GPIO_2(x) S5PV310_GPX2(x) #define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
#define EINT_GPIO_3(x) S5PV310_GPX3(x) #define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
#endif /* __ASM_ARCH_REGS_GPIO_H */ #endif /* __ASM_ARCH_REGS_GPIO_H */
/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h /* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* S5PV310 - IRQ register definitions * EXYNOS4 - IRQ register definitions
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* arch/arm/mach-exynos4/include/mach/regs-mct.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 MCT configutation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_MCT_H
#define __ASM_ARCH_REGS_MCT_H __FILE__
#include <mach/map.h>
#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300)
#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400)
#define MCT_L_TCNTB_OFFSET (0x00)
#define MCT_L_ICNTB_OFFSET (0x08)
#define MCT_L_TCON_OFFSET (0x20)
#define MCT_L_INT_CSTAT_OFFSET (0x30)
#define MCT_L_INT_ENB_OFFSET (0x34)
#define MCT_L_WSTAT_OFFSET (0x40)
#define MCT_G_TCON_START (1 << 8)
#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
#define MCT_L_TCON_INT_START (1 << 1)
#define MCT_L_TCON_TIMER_START (1 << 0)
#endif /* __ASM_ARCH_REGS_MCT_H */
/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h /* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* S5PV310 - SROMC and DMC register definitions * EXYNOS4 - SROMC and DMC register definitions
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - Power management unit definition
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_PMU_H
#define __ASM_ARCH_REGS_PMU_H __FILE__
#include <mach/map.h>
#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
#define S5P_USE_STANDBY_WFI0 (1 << 16)
#define S5P_USE_STANDBY_WFI1 (1 << 17)
#define S5P_USE_STANDBY_WFE0 (1 << 24)
#define S5P_USE_STANDBY_WFE1 (1 << 25)
#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
#define S5P_MIPI_DPHY_ENABLE (1 << 0)
#define S5P_MIPI_DPHY_SRESETN (1 << 1)
#define S5P_MIPI_DPHY_MRESETN (1 << 2)
#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
#define S5P_INFORM0 S5P_PMUREG(0x0800)
#define S5P_INFORM1 S5P_PMUREG(0x0804)
#define S5P_INFORM2 S5P_PMUREG(0x0808)
#define S5P_INFORM3 S5P_PMUREG(0x080C)
#define S5P_INFORM4 S5P_PMUREG(0x0810)
#define S5P_INFORM5 S5P_PMUREG(0x0814)
#define S5P_INFORM6 S5P_PMUREG(0x0818)
#define S5P_INFORM7 S5P_PMUREG(0x081C)
#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
#define S5P_INT_LOCAL_PWR_EN 0x7
#define S5P_CHECK_SLEEP 0x00000BAD
#endif /* __ASM_ARCH_REGS_PMU_H */
/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h /* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* S5PV310 - System MMU register * EXYNOS4 - System MMU register
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -19,6 +19,10 @@ ...@@ -19,6 +19,10 @@
#define S5P_MMU_FLUSH 0x00C #define S5P_MMU_FLUSH 0x00C
#define S5P_PT_BASE_ADDR 0x014 #define S5P_PT_BASE_ADDR 0x014
#define S5P_INT_STATUS 0x018 #define S5P_INT_STATUS 0x018
#define S5P_INT_CLEAR 0x01C
#define S5P_PAGE_FAULT_ADDR 0x024 #define S5P_PAGE_FAULT_ADDR 0x024
#define S5P_AW_FAULT_ADDR 0x028
#define S5P_AR_FAULT_ADDR 0x02C
#define S5P_DEFAULT_SLAVE_ADDR 0x030
#endif /* __ASM_ARCH_REGS_SYSMMU_H */ #endif /* __ASM_ARCH_REGS_SYSMMU_H */
/* linux/arch/arm/mach-s5pv310/include/mach/smp.h /* linux/arch/arm/mach-exynos4/include/mach/smp.h
* *
* Cloned from arch/arm/mach-realview/include/mach/smp.h * Cloned from arch/arm/mach-realview/include/mach/smp.h
*/ */
......
/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung sysmmu driver for EXYNOS4
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_SYSMMU_H
#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
enum exynos4_sysmmu_ips {
SYSMMU_MDMA,
SYSMMU_SSS,
SYSMMU_FIMC0,
SYSMMU_FIMC1,
SYSMMU_FIMC2,
SYSMMU_FIMC3,
SYSMMU_JPEG,
SYSMMU_FIMD0,
SYSMMU_FIMD1,
SYSMMU_PCIe,
SYSMMU_G2D,
SYSMMU_ROTATOR,
SYSMMU_MDMA2,
SYSMMU_TV,
SYSMMU_MFC_L,
SYSMMU_MFC_R,
EXYNOS4_SYSMMU_TOTAL_IPNUM,
};
#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM
extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
typedef enum exynos4_sysmmu_ips sysmmu_ips;
void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
void sysmmu_clk_enable(sysmmu_ips ips);
void sysmmu_clk_disable(sysmmu_ips ips);
#endif /* __ASM_ARM_ARCH_SYSMMU_H */
/* linux/arch/arm/mach-s5pv310/include/mach/system.h /* linux/arch/arm/mach-exynos4/include/mach/system.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* S5PV310 - system support header * EXYNOS4 - system support header
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-s5pv310/include/mach/timex.h /* linux/arch/arm/mach-exynos4/include/mach/timex.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* Copyright (c) 2003-2010 Simtec Electronics * Copyright (c) 2003-2010 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk> * Ben Dooks <ben@simtec.co.uk>
* *
* Based on arch/arm/mach-s5p6442/include/mach/timex.h * Based on arch/arm/mach-s5p6442/include/mach/timex.h
* *
* S5PV310 - time parameters * EXYNOS4 - time parameters
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h /* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* S5PV310 - uncompress code * EXYNOS4 - uncompress code
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h /* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com
* *
* Copyright 2010 Ben Dooks <ben-linux@fluff.org> * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
* *
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
* *
* S5PV310 vmalloc definition * EXYNOS4 vmalloc definition
*/ */
#ifndef __ASM_ARCH_VMALLOC_H #ifndef __ASM_ARCH_VMALLOC_H
......
/* linux/arch/arm/mach-s5pv310/init.c /* linux/arch/arm/mach-exynos4/init.c
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com/
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = { static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
[0] = { [0] = {
.name = "uclk1", .name = "uclk1",
.divisor = 1, .divisor = 1,
...@@ -24,7 +24,7 @@ static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = { ...@@ -24,7 +24,7 @@ static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
}; };
/* uart registration process */ /* uart registration process */
void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{ {
struct s3c2410_uartcfg *tcfg = cfg; struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt; u32 ucnt;
...@@ -32,8 +32,8 @@ void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) ...@@ -32,8 +32,8 @@ void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
if (!tcfg->clocks) { if (!tcfg->clocks) {
tcfg->has_fracval = 1; tcfg->has_fracval = 1;
tcfg->clocks = s5pv310_serial_clocks; tcfg->clocks = exynos4_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks); tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
} }
} }
......
/* linux/arch/arm/mach-s5pv310/irq-combiner.c /* linux/arch/arm/mach-exynos4/irq-combiner.c
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* Based on arch/arm/common/gic.c * Based on arch/arm/common/gic.c
......
/* linux/arch/arm/mach-s5pv310/irq-eint.c /* linux/arch/arm/mach-exynos4/irq-eint.c
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* S5PV310 - IRQ EINT support * EXYNOS4 - IRQ EINT support
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -27,7 +27,7 @@ static DEFINE_SPINLOCK(eint_lock); ...@@ -27,7 +27,7 @@ static DEFINE_SPINLOCK(eint_lock);
static unsigned int eint0_15_data[16]; static unsigned int eint0_15_data[16];
static unsigned int s5pv310_get_irq_nr(unsigned int number) static unsigned int exynos4_get_irq_nr(unsigned int number)
{ {
u32 ret = 0; u32 ret = 0;
...@@ -48,7 +48,7 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number) ...@@ -48,7 +48,7 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
return ret; return ret;
} }
static inline void s5pv310_irq_eint_mask(struct irq_data *data) static inline void exynos4_irq_eint_mask(struct irq_data *data)
{ {
u32 mask; u32 mask;
...@@ -59,7 +59,7 @@ static inline void s5pv310_irq_eint_mask(struct irq_data *data) ...@@ -59,7 +59,7 @@ static inline void s5pv310_irq_eint_mask(struct irq_data *data)
spin_unlock(&eint_lock); spin_unlock(&eint_lock);
} }
static void s5pv310_irq_eint_unmask(struct irq_data *data) static void exynos4_irq_eint_unmask(struct irq_data *data)
{ {
u32 mask; u32 mask;
...@@ -70,19 +70,19 @@ static void s5pv310_irq_eint_unmask(struct irq_data *data) ...@@ -70,19 +70,19 @@ static void s5pv310_irq_eint_unmask(struct irq_data *data)
spin_unlock(&eint_lock); spin_unlock(&eint_lock);
} }
static inline void s5pv310_irq_eint_ack(struct irq_data *data) static inline void exynos4_irq_eint_ack(struct irq_data *data)
{ {
__raw_writel(eint_irq_to_bit(data->irq), __raw_writel(eint_irq_to_bit(data->irq),
S5P_EINT_PEND(EINT_REG_NR(data->irq))); S5P_EINT_PEND(EINT_REG_NR(data->irq)));
} }
static void s5pv310_irq_eint_maskack(struct irq_data *data) static void exynos4_irq_eint_maskack(struct irq_data *data)
{ {
s5pv310_irq_eint_mask(data); exynos4_irq_eint_mask(data);
s5pv310_irq_eint_ack(data); exynos4_irq_eint_ack(data);
} }
static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type) static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
{ {
int offs = EINT_OFFSET(data->irq); int offs = EINT_OFFSET(data->irq);
int shift; int shift;
...@@ -145,19 +145,19 @@ static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type) ...@@ -145,19 +145,19 @@ static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
return 0; return 0;
} }
static struct irq_chip s5pv310_irq_eint = { static struct irq_chip exynos4_irq_eint = {
.name = "s5pv310-eint", .name = "exynos4-eint",
.irq_mask = s5pv310_irq_eint_mask, .irq_mask = exynos4_irq_eint_mask,
.irq_unmask = s5pv310_irq_eint_unmask, .irq_unmask = exynos4_irq_eint_unmask,
.irq_mask_ack = s5pv310_irq_eint_maskack, .irq_mask_ack = exynos4_irq_eint_maskack,
.irq_ack = s5pv310_irq_eint_ack, .irq_ack = exynos4_irq_eint_ack,
.irq_set_type = s5pv310_irq_eint_set_type, .irq_set_type = exynos4_irq_eint_set_type,
#ifdef CONFIG_PM #ifdef CONFIG_PM
.irq_set_wake = s3c_irqext_wake, .irq_set_wake = s3c_irqext_wake,
#endif #endif
}; };
/* s5pv310_irq_demux_eint /* exynos4_irq_demux_eint
* *
* This function demuxes the IRQ from from EINTs 16 to 31. * This function demuxes the IRQ from from EINTs 16 to 31.
* It is designed to be inlined into the specific handler * It is designed to be inlined into the specific handler
...@@ -165,7 +165,7 @@ static struct irq_chip s5pv310_irq_eint = { ...@@ -165,7 +165,7 @@ static struct irq_chip s5pv310_irq_eint = {
* *
* Each EINT pend/mask registers handle eight of them. * Each EINT pend/mask registers handle eight of them.
*/ */
static inline void s5pv310_irq_demux_eint(unsigned int start) static inline void exynos4_irq_demux_eint(unsigned int start)
{ {
unsigned int irq; unsigned int irq;
...@@ -182,13 +182,13 @@ static inline void s5pv310_irq_demux_eint(unsigned int start) ...@@ -182,13 +182,13 @@ static inline void s5pv310_irq_demux_eint(unsigned int start)
} }
} }
static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{ {
s5pv310_irq_demux_eint(IRQ_EINT(16)); exynos4_irq_demux_eint(IRQ_EINT(16));
s5pv310_irq_demux_eint(IRQ_EINT(24)); exynos4_irq_demux_eint(IRQ_EINT(24));
} }
static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc) static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{ {
u32 *irq_data = get_irq_data(irq); u32 *irq_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq); struct irq_chip *chip = get_irq_chip(irq);
...@@ -203,27 +203,27 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc) ...@@ -203,27 +203,27 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
chip->irq_unmask(&desc->irq_data); chip->irq_unmask(&desc->irq_data);
} }
int __init s5pv310_init_irq_eint(void) int __init exynos4_init_irq_eint(void)
{ {
int irq; int irq;
for (irq = 0 ; irq <= 31 ; irq++) { for (irq = 0 ; irq <= 31 ; irq++) {
set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint); set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
set_irq_handler(IRQ_EINT(irq), handle_level_irq); set_irq_handler(IRQ_EINT(irq), handle_level_irq);
set_irq_flags(IRQ_EINT(irq), IRQF_VALID); set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
} }
set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31); set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
for (irq = 0 ; irq <= 15 ; irq++) { for (irq = 0 ; irq <= 15 ; irq++) {
eint0_15_data[irq] = IRQ_EINT(irq); eint0_15_data[irq] = IRQ_EINT(irq);
set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]); set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
set_irq_chained_handler(s5pv310_get_irq_nr(irq), set_irq_chained_handler(exynos4_get_irq_nr(irq),
s5pv310_irq_eint0_15); exynos4_irq_eint0_15);
} }
return 0; return 0;
} }
arch_initcall(s5pv310_init_irq_eint); arch_initcall(exynos4_init_irq_eint);
/* linux/arch/arm/mach-s5pv310/localtimer.c /* linux/arch/arm/mach-exynos4/localtimer.c
* *
* Cloned from linux/arch/arm/mach-realview/localtimer.c * Cloned from linux/arch/arm/mach-realview/localtimer.c
* *
......
/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/smsc911x.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/exynos4.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/sdhci.h>
#include <mach/map.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = ARMLEX4210_UCON_DEFAULT,
.ulcon = ARMLEX4210_ULCON_DEFAULT,
.ufcon = ARMLEX4210_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = ARMLEX4210_UCON_DEFAULT,
.ulcon = ARMLEX4210_ULCON_DEFAULT,
.ufcon = ARMLEX4210_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = ARMLEX4210_UCON_DEFAULT,
.ulcon = ARMLEX4210_ULCON_DEFAULT,
.ufcon = ARMLEX4210_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = ARMLEX4210_UCON_DEFAULT,
.ulcon = ARMLEX4210_ULCON_DEFAULT,
.ufcon = ARMLEX4210_UFCON_DEFAULT,
},
};
static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
#endif
};
static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = EXYNOS4_GPX2(5),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
.max_width = 4,
};
static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
.max_width = 4,
};
static void __init armlex4210_sdhci_init(void)
{
s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
}
static void __init armlex4210_wlan_init(void)
{
/* enable */
s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
/* reset */
s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
/* wakeup */
s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
}
static struct resource armlex4210_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(3),
.end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_EINT(27),
.end = IRQ_EINT(27),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
},
};
static struct smsc911x_platform_config smsc9215_config = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
.phy_interface = PHY_INTERFACE_MODE_MII,
.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
};
static struct platform_device armlex4210_smsc911x = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
.resource = armlex4210_smsc911x_resources,
.dev = {
.platform_data = &smsc9215_config,
},
};
static struct platform_device *armlex4210_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_rtc,
&s3c_device_wdt,
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&armlex4210_smsc911x,
&exynos4_device_ahci,
};
static void __init armlex4210_smsc911x_init(void)
{
u32 cs1;
/* configure nCS1 width to 16 bits */
cs1 = __raw_readl(S5P_SROM_BW) &
~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
(0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
(1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
S5P_SROM_BW__NCS1__SHIFT;
__raw_writel(cs1, S5P_SROM_BW);
/* set timing for nCS1 suitable for ethernet chip */
__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
(0x9 << S5P_SROM_BCX__TACP__SHIFT) |
(0xc << S5P_SROM_BCX__TCAH__SHIFT) |
(0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
(0x6 << S5P_SROM_BCX__TACC__SHIFT) |
(0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}
static void __init armlex4210_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(armlex4210_uartcfgs,
ARRAY_SIZE(armlex4210_uartcfgs));
}
static void __init armlex4210_machine_init(void)
{
armlex4210_smsc911x_init();
armlex4210_sdhci_init();
armlex4210_wlan_init();
platform_add_devices(armlex4210_devices,
ARRAY_SIZE(armlex4210_devices));
}
MACHINE_START(ARMLEX4210, "ARMLEX4210")
/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = exynos4_init_irq,
.map_io = armlex4210_map_io,
.init_machine = armlex4210_machine_init,
.timer = &exynos4_timer,
MACHINE_END
/*
* linux/arch/arm/mach-exynos4/mach-nuri.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/mmc/host.h>
#include <linux/fb.h>
#include <linux/pwm_backlight.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
#include <mach/map.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define NURI_ULCON_DEFAULT S3C2410_LCON_CS8
#define NURI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG256 | \
S5PV210_UFCON_RXTRIG256)
enum fixed_regulator_id {
FIXED_REG_ID_MMC = 0,
};
static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
{
.hwport = 0,
.ucon = NURI_UCON_DEFAULT,
.ulcon = NURI_ULCON_DEFAULT,
.ufcon = NURI_UFCON_DEFAULT,
},
{
.hwport = 1,
.ucon = NURI_UCON_DEFAULT,
.ulcon = NURI_ULCON_DEFAULT,
.ufcon = NURI_UFCON_DEFAULT,
},
{
.hwport = 2,
.ucon = NURI_UCON_DEFAULT,
.ulcon = NURI_ULCON_DEFAULT,
.ufcon = NURI_UFCON_DEFAULT,
},
{
.hwport = 3,
.ucon = NURI_UCON_DEFAULT,
.ulcon = NURI_ULCON_DEFAULT,
.ufcon = NURI_UFCON_DEFAULT,
},
};
/* eMMC */
static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE | MMC_CAP_ERASE),
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply emmc_supplies[] = {
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
REGULATOR_SUPPLY("vmmc", "dw_mmc"),
};
static struct regulator_init_data emmc_fixed_voltage_init_data = {
.constraints = {
.name = "VMEM_VDD_2.8V",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(emmc_supplies),
.consumer_supplies = emmc_supplies,
};
static struct fixed_voltage_config emmc_fixed_voltage_config = {
.supply_name = "MASSMEMORY_EN (inverted)",
.microvolts = 2800000,
.gpio = EXYNOS4_GPL1(1),
.enable_high = false,
.init_data = &emmc_fixed_voltage_init_data,
};
static struct platform_device emmc_fixed_voltage = {
.name = "reg-fixed-voltage",
.id = FIXED_REG_ID_MMC,
.dev = {
.platform_data = &emmc_fixed_voltage_config,
},
};
/* SD */
static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE,
.ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */
.ext_cd_gpio_invert = 1,
.cd_type = S3C_SDHCI_CD_GPIO,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* WLAN */
static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.cd_type = S3C_SDHCI_CD_EXTERNAL,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static void __init nuri_sdhci_init(void)
{
s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
}
/* GPIO KEYS */
static struct gpio_keys_button nuri_gpio_keys_tables[] = {
{
.code = KEY_VOLUMEUP,
.gpio = EXYNOS4_GPX2(0), /* XEINT16 */
.desc = "gpio-keys: KEY_VOLUMEUP",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_VOLUMEDOWN,
.gpio = EXYNOS4_GPX2(1), /* XEINT17 */
.desc = "gpio-keys: KEY_VOLUMEDOWN",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_POWER,
.gpio = EXYNOS4_GPX2(7), /* XEINT23 */
.desc = "gpio-keys: KEY_POWER",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
},
};
static struct gpio_keys_platform_data nuri_gpio_keys_data = {
.buttons = nuri_gpio_keys_tables,
.nbuttons = ARRAY_SIZE(nuri_gpio_keys_tables),
};
static struct platform_device nuri_gpio_keys = {
.name = "gpio-keys",
.dev = {
.platform_data = &nuri_gpio_keys_data,
},
};
static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
{
int gpio = EXYNOS4_GPE1(5);
gpio_request(gpio, "LVDS_nSHDN");
gpio_direction_output(gpio, power);
gpio_free(gpio);
}
static int nuri_bl_init(struct device *dev)
{
int ret, gpio = EXYNOS4_GPE2(3);
ret = gpio_request(gpio, "LCD_LDO_EN");
if (!ret)
gpio_direction_output(gpio, 0);
return ret;
}
static int nuri_bl_notify(struct device *dev, int brightness)
{
if (brightness < 1)
brightness = 0;
gpio_set_value(EXYNOS4_GPE2(3), 1);
return brightness;
}
static void nuri_bl_exit(struct device *dev)
{
gpio_free(EXYNOS4_GPE2(3));
}
/* nuri pwm backlight */
static struct platform_pwm_backlight_data nuri_backlight_data = {
.pwm_id = 0,
.pwm_period_ns = 30000,
.max_brightness = 100,
.dft_brightness = 50,
.init = nuri_bl_init,
.notify = nuri_bl_notify,
.exit = nuri_bl_exit,
};
static struct platform_device nuri_backlight_device = {
.name = "pwm-backlight",
.id = -1,
.dev = {
.parent = &s3c_device_timer[0].dev,
.platform_data = &nuri_backlight_data,
},
};
static struct plat_lcd_data nuri_lcd_platform_data = {
.set_power = nuri_lcd_power_on,
};
static struct platform_device nuri_lcd_device = {
.name = "platform-lcd",
.id = -1,
.dev = {
.platform_data = &nuri_lcd_platform_data,
},
};
/* I2C1 */
static struct i2c_board_info i2c1_devs[] __initdata = {
/* Gyro, To be updated */
};
/* GPIO I2C 5 (PMIC) */
static struct i2c_board_info i2c5_devs[] __initdata = {
/* max8997, To be updated */
};
static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&emmc_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_wdt,
&s3c_device_timer[0],
/* NURI Devices */
&nuri_gpio_keys,
&nuri_lcd_device,
&nuri_backlight_device,
};
static void __init nuri_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
}
static void __init nuri_machine_init(void)
{
nuri_sdhci_init();
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
}
MACHINE_START(NURI, "NURI")
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = exynos4_init_irq,
.map_io = nuri_map_io,
.init_machine = nuri_machine_init,
.timer = &exynos4_timer,
MACHINE_END
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/* /*
* linux/arch/arm/mach-s5pv310/setup-i2c0.c * linux/arch/arm/mach-exynos4/setup-i2c0.c
* *
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com/
...@@ -21,6 +21,6 @@ struct platform_device; /* don't need the contents */ ...@@ -21,6 +21,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c0_cfg_gpio(struct platform_device *dev) void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{ {
s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2, s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
} }
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...@@ -181,7 +181,7 @@ static void __init s3c64xx_cpufreq_config_regulator(void) ...@@ -181,7 +181,7 @@ static void __init s3c64xx_cpufreq_config_regulator(void)
} }
#endif #endif
static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
{ {
int ret; int ret;
struct cpufreq_frequency_table *freq; struct cpufreq_frequency_table *freq;
......
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