Commit 9f3a6cad authored by Jia Zhang's avatar Jia Zhang Committed by Greg Kroah-Hartman

x86/microcode/intel: Extend BDW late-loading further with LLC size check

commit 7e702d17 upstream.

Commit b94b7373 ("x86/microcode/intel: Extend BDW late-loading with a
revision check") reduced the impact of erratum BDF90 for Broadwell model
79.

The impact can be reduced further by checking the size of the last level
cache portion per core.

Tony: "The erratum says the problem only occurs on the large-cache SKUs.
So we only need to avoid the update if we are on a big cache SKU that is
also running old microcode."

For more details, see erratum BDF90 in document #334165 (Intel Xeon
Processor E7-8800/4800 v4 Product Family Specification Update) from
September 2017.

Fixes: b94b7373 ("x86/microcode/intel: Extend BDW late-loading with a revision check")
Signed-off-by: default avatarJia Zhang <zhang.jia@linux.alibaba.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarTony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/1516321542-31161-1-git-send-email-zhang.jia@linux.alibaba.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent dc1932c6
...@@ -40,6 +40,9 @@ ...@@ -40,6 +40,9 @@
#include <asm/setup.h> #include <asm/setup.h>
#include <asm/msr.h> #include <asm/msr.h>
/* last level cache size per core */
static int llc_size_per_core;
/* /*
* Temporary microcode blobs pointers storage. We note here during early load * Temporary microcode blobs pointers storage. We note here during early load
* the pointers to microcode blobs we've got from whatever storage (detached * the pointers to microcode blobs we've got from whatever storage (detached
...@@ -1053,12 +1056,14 @@ static bool is_blacklisted(unsigned int cpu) ...@@ -1053,12 +1056,14 @@ static bool is_blacklisted(unsigned int cpu)
/* /*
* Late loading on model 79 with microcode revision less than 0x0b000021 * Late loading on model 79 with microcode revision less than 0x0b000021
* may result in a system hang. This behavior is documented in item * and LLC size per core bigger than 2.5MB may result in a system hang.
* BDF90, #334165 (Intel Xeon Processor E7-8800/4800 v4 Product Family). * This behavior is documented in item BDF90, #334165 (Intel Xeon
* Processor E7-8800/4800 v4 Product Family).
*/ */
if (c->x86 == 6 && if (c->x86 == 6 &&
c->x86_model == INTEL_FAM6_BROADWELL_X && c->x86_model == INTEL_FAM6_BROADWELL_X &&
c->x86_mask == 0x01 && c->x86_mask == 0x01 &&
llc_size_per_core > 2621440 &&
c->microcode < 0x0b000021) { c->microcode < 0x0b000021) {
pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode); pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
...@@ -1125,6 +1130,15 @@ static struct microcode_ops microcode_intel_ops = { ...@@ -1125,6 +1130,15 @@ static struct microcode_ops microcode_intel_ops = {
.microcode_fini_cpu = microcode_fini_cpu, .microcode_fini_cpu = microcode_fini_cpu,
}; };
static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c)
{
u64 llc_size = c->x86_cache_size * 1024;
do_div(llc_size, c->x86_max_cores);
return (int)llc_size;
}
struct microcode_ops * __init init_intel_microcode(void) struct microcode_ops * __init init_intel_microcode(void)
{ {
struct cpuinfo_x86 *c = &boot_cpu_data; struct cpuinfo_x86 *c = &boot_cpu_data;
...@@ -1135,6 +1149,8 @@ struct microcode_ops * __init init_intel_microcode(void) ...@@ -1135,6 +1149,8 @@ struct microcode_ops * __init init_intel_microcode(void)
return NULL; return NULL;
} }
llc_size_per_core = calc_llc_size_per_core(c);
return &microcode_intel_ops; return &microcode_intel_ops;
} }
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