Commit 9fe51c55 authored by Cezary Rojewski's avatar Cezary Rojewski Committed by Mark Brown

ASoC: Intel: Introduce AVS driver

Declare base structures and core DSP operations for the avs solution.
The base structures describe PCI HDAudio bus device and platform-type
differentiations. First set of operations added controls the lifecycle
of any Audio DSP core: (un)powering, (un)resetting and (un)stalling.
Signed-off-by: default avatarAmadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Signed-off-by: default avatarCezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20220311153544.136854-4-cezary.rojewski@intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent da039809
......@@ -209,5 +209,16 @@ config SND_SOC_INTEL_KEEMBAY
If you have a Intel Keembay platform then enable this option
by saying Y or m.
config SND_SOC_INTEL_AVS
tristate "Intel AVS driver"
depends on PCI && ACPI
depends on COMMON_CLK
select SND_SOC_ACPI
select SND_HDA_EXT_CORE
help
Enable support for Intel(R) cAVS 1.5 platforms with DSP
capabilities. This includes Skylake, Kabylake, Amberlake and
Apollolake.
# ASoC codec drivers
source "sound/soc/intel/boards/Kconfig"
......@@ -7,6 +7,7 @@ obj-$(CONFIG_SND_SST_ATOM_HIFI2_PLATFORM) += atom/
obj-$(CONFIG_SND_SOC_INTEL_CATPT) += catpt/
obj-$(CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON) += skylake/
obj-$(CONFIG_SND_SOC_INTEL_KEEMBAY) += keembay/
obj-$(CONFIG_SND_SOC_INTEL_AVS) += avs/
# Machine support
obj-$(CONFIG_SND_SOC) += boards/
# SPDX-License-Identifier: GPL-2.0-only
snd-soc-avs-objs := dsp.o
obj-$(CONFIG_SND_SOC_INTEL_AVS) += snd-soc-avs.o
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
*
* Authors: Cezary Rojewski <cezary.rojewski@intel.com>
* Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
*/
#ifndef __SOUND_SOC_INTEL_AVS_H
#define __SOUND_SOC_INTEL_AVS_H
#include <linux/device.h>
#include <sound/hda_codec.h>
struct avs_dev;
struct avs_dsp_ops {
int (* const power)(struct avs_dev *, u32, bool);
int (* const reset)(struct avs_dev *, u32, bool);
int (* const stall)(struct avs_dev *, u32, bool);
};
#define avs_dsp_op(adev, op, ...) \
((adev)->spec->dsp_ops->op(adev, ## __VA_ARGS__))
#define avs_platattr_test(adev, attr) \
((adev)->spec->attributes & AVS_PLATATTR_##attr)
/* Platform specific descriptor */
struct avs_spec {
const char *name;
const struct avs_dsp_ops *const dsp_ops;
const u32 core_init_mask; /* used during DSP boot */
const u64 attributes; /* bitmask of AVS_PLATATTR_* */
};
/*
* struct avs_dev - Intel HD-Audio driver data
*
* @dev: PCI device
* @dsp_ba: DSP bar address
* @spec: platform-specific descriptor
*/
struct avs_dev {
struct hda_bus base;
struct device *dev;
void __iomem *dsp_ba;
const struct avs_spec *spec;
};
/* from hda_bus to avs_dev */
#define hda_to_avs(hda) container_of(hda, struct avs_dev, base)
/* from hdac_bus to avs_dev */
#define hdac_to_avs(hdac) hda_to_avs(to_hda_bus(hdac))
/* from device to avs_dev */
#define to_avs_dev(dev) \
({ \
struct hdac_bus *__bus = dev_get_drvdata(dev); \
hdac_to_avs(__bus); \
})
int avs_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power);
int avs_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset);
int avs_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall);
int avs_dsp_core_enable(struct avs_dev *adev, u32 core_mask);
int avs_dsp_core_disable(struct avs_dev *adev, u32 core_mask);
#endif /* __SOUND_SOC_INTEL_AVS_H */
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
//
// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
// Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
//
#include <linux/module.h>
#include <sound/hdaudio_ext.h>
#include "avs.h"
#include "registers.h"
#define AVS_ADSPCS_INTERVAL_US 500
#define AVS_ADSPCS_TIMEOUT_US 50000
int avs_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
{
u32 value, mask, reg;
int ret;
mask = AVS_ADSPCS_SPA_MASK(core_mask);
value = power ? mask : 0;
snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
mask = AVS_ADSPCS_CPA_MASK(core_mask);
value = power ? mask : 0;
ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
reg, (reg & mask) == value,
AVS_ADSPCS_INTERVAL_US,
AVS_ADSPCS_TIMEOUT_US);
if (ret)
dev_err(adev->dev, "core_mask %d power %s failed: %d\n",
core_mask, power ? "on" : "off", ret);
return ret;
}
int avs_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset)
{
u32 value, mask, reg;
int ret;
mask = AVS_ADSPCS_CRST_MASK(core_mask);
value = reset ? mask : 0;
snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
reg, (reg & mask) == value,
AVS_ADSPCS_INTERVAL_US,
AVS_ADSPCS_TIMEOUT_US);
if (ret)
dev_err(adev->dev, "core_mask %d %s reset failed: %d\n",
core_mask, reset ? "enter" : "exit", ret);
return ret;
}
int avs_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall)
{
u32 value, mask, reg;
int ret;
mask = AVS_ADSPCS_CSTALL_MASK(core_mask);
value = stall ? mask : 0;
snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
reg, (reg & mask) == value,
AVS_ADSPCS_INTERVAL_US,
AVS_ADSPCS_TIMEOUT_US);
if (ret)
dev_err(adev->dev, "core_mask %d %sstall failed: %d\n",
core_mask, stall ? "" : "un", ret);
return ret;
}
int avs_dsp_core_enable(struct avs_dev *adev, u32 core_mask)
{
int ret;
ret = avs_dsp_op(adev, power, core_mask, true);
if (ret)
return ret;
ret = avs_dsp_op(adev, reset, core_mask, false);
if (ret)
return ret;
return avs_dsp_op(adev, stall, core_mask, false);
}
int avs_dsp_core_disable(struct avs_dev *adev, u32 core_mask)
{
/* No error checks to allow for complete DSP shutdown. */
avs_dsp_op(adev, stall, core_mask, true);
avs_dsp_op(adev, reset, core_mask, true);
return avs_dsp_op(adev, power, core_mask, false);
}
MODULE_LICENSE("GPL");
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
*
* Authors: Cezary Rojewski <cezary.rojewski@intel.com>
* Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
*/
#ifndef __SOUND_SOC_INTEL_AVS_REGS_H
#define __SOUND_SOC_INTEL_AVS_REGS_H
/* Intel HD Audio General DSP Registers */
#define AVS_ADSP_GEN_BASE 0x0
#define AVS_ADSP_REG_ADSPCS (AVS_ADSP_GEN_BASE + 0x04)
#define AVS_ADSPCS_CRST_MASK(cm) (cm)
#define AVS_ADSPCS_CSTALL_MASK(cm) ((cm) << 8)
#define AVS_ADSPCS_SPA_MASK(cm) ((cm) << 16)
#define AVS_ADSPCS_CPA_MASK(cm) ((cm) << 24)
#define AVS_MAIN_CORE_MASK BIT(0)
#endif /* __SOUND_SOC_INTEL_AVS_REGS_H */
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