Commit a0553e01 authored by Quentin Schulz's avatar Quentin Schulz Committed by Paul Burton

MIPS: mscc: ocelot: add MIIM1 bus

There is an additional MIIM (MDIO) bus in this SoC so let's declare it
in the dtsi.

This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
support for internal PHY reset on this bus on the contrary of MIIM0 so
there is only one register address space and not two.
Signed-off-by: default avatarQuentin Schulz <quentin.schulz@bootlin.com>
Acked-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20014/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
parent 49e5bb13
......@@ -178,6 +178,11 @@ uart2_pins: uart2-pins {
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
miim1: miim1 {
pins = "GPIO_14", "GPIO_15";
function = "miim1";
};
};
mdio0: mdio@107009c {
......@@ -201,5 +206,16 @@ phy3: ethernet-phy@3 {
reg = <3>;
};
};
mdio1: mdio@10700c0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x10700c0 0x24>;
interrupts = <15>;
pinctrl-names = "default";
pinctrl-0 = <&miim1>;
status = "disabled";
};
};
};
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