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Commit a06b9560 authored by Gatien Chevallier's avatar Gatien Chevallier Committed by Alexandre Torgue
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ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards 

ETZPC is a firewall controller. Put all peripherals filtered by the
ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for
backward compatibility.
Signed-off-by: default avatarGatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@foss.st.com>
parent ad426352
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Showing with 565 additions and 559 deletions
arch/arm/boot/dts/st/stm32mp131.dtsi
View file @ a06b9560
......@@ -745,6 +745,153 @@ dmamux1: dma-router@48002000 {
dma-channels = <16>;
};
rcc: rcc@50000000 {
compatible = "st,stm32mp13-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_CSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
};
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
};
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&rcc SYSCFG>;
};
lptimer4: timer@50023000 {
compatible = "st,stm32-lptimer";
reg = <0x50023000 0x400>;
interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
timer {
compatible = "st,stm32-lptimer-timer";
status = "disabled";
};
};
lptimer5: timer@50024000 {
compatible = "st,stm32-lptimer";
reg = <0x50024000 0x400>;
interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
timer {
compatible = "st,stm32-lptimer-timer";
status = "disabled";
};
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc MDMA>;
#dma-cells = <5>;
dma-channels = <32>;
dma-requests = <48>;
};
crc1: crc@58009000 {
compatible = "st,stm32f7-crc";
reg = <0x58009000 0x400>;
clocks = <&rcc CRC1>;
status = "disabled";
};
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
usbh_ehci: usb@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
status = "disabled";
};
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
rtc: rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_RTCAPB>,
<&scmi_clk CK_SCMI_RTC>;
clock-names = "pclk", "rtc_ck";
status = "disabled";
};
bsec: efuse@5c005000 {
compatible = "st,stm32mp13-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
part_number_otp: part_number_otp@4 {
reg = <0x4 0x2>;
bits = <0 12>;
};
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
};
etzpc: bus@5c007000 {
compatible = "simple-bus";
reg = <0x5c007000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
adc_2: adc@48004000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48004000 0x400>;
......@@ -1079,32 +1226,6 @@ timer@16 {
};
};
rcc: rcc@50000000 {
compatible = "st,stm32mp13-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_CSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
};
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
};
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&rcc SYSCFG>;
};
lptimer2: timer@50021000 {
#address-cells = <1>;
#size-cells = <0>;
......@@ -1168,48 +1289,6 @@ timer {
};
};
lptimer4: timer@50023000 {
compatible = "st,stm32-lptimer";
reg = <0x50023000 0x400>;
interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
timer {
compatible = "st,stm32-lptimer-timer";
status = "disabled";
};
};
lptimer5: timer@50024000 {
compatible = "st,stm32-lptimer";
reg = <0x50024000 0x400>;
interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
timer {
compatible = "st,stm32-lptimer-timer";
status = "disabled";
};
};
hash: hash@54003000 {
compatible = "st,stm32mp13-hash";
reg = <0x54003000 0x400>;
......@@ -1229,16 +1308,6 @@ rng: rng@54004000 {
status = "disabled";
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc MDMA>;
#dma-cells = <5>;
dma-channels = <32>;
dma-requests = <48>;
};
fmc: memory-controller@58002000 {
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
......@@ -1315,40 +1384,6 @@ sdmmc2: mmc@58007000 {
status = "disabled";
};
crc1: crc@58009000 {
compatible = "st,stm32f7-crc";
reg = <0x58009000 0x400>;
clocks = <&rcc CRC1>;
status = "disabled";
};
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
usbh_ehci: usb@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
status = "disabled";
};
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
......@@ -1371,33 +1406,6 @@ usbphyc_port1: usb-phy@1 {
reg = <1>;
};
};
rtc: rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_RTCAPB>,
<&scmi_clk CK_SCMI_RTC>;
clock-names = "pclk", "rtc_ck";
status = "disabled";
};
bsec: efuse@5c005000 {
compatible = "st,stm32mp13-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
part_number_otp: part_number_otp@4 {
reg = <0x4 0x2>;
bits = <0 12>;
};
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
};
/*
......
arch/arm/boot/dts/st/stm32mp133.dtsi
View file @ a06b9560
......@@ -33,7 +33,10 @@ m_can2: can@4400f000 {
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};
};
};
&etzpc {
adc_1: adc@48003000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48003000 0x400>;
......@@ -64,5 +67,4 @@ channel@18 {
};
};
};
};
};
arch/arm/boot/dts/st/stm32mp13xc.dtsi
View file @ a06b9560
......@@ -4,8 +4,7 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
soc {
&etzpc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
......@@ -14,5 +13,4 @@ cryp: crypto@54002000 {
resets = <&rcc CRYP1_R>;
status = "disabled";
};
};
};
arch/arm/boot/dts/st/stm32mp13xf.dtsi
View file @ a06b9560
......@@ -4,8 +4,7 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
soc {
&etzpc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
......@@ -14,5 +13,4 @@ cryp: crypto@54002000 {
resets = <&rcc CRYP1_R>;
status = "disabled";
};
};
};
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