Commit a1435469 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher

drm/amdgpu: add gmc support for dimgrey_cavefish

Same as navy_flounder.
Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarJiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ee64e01e
...@@ -763,6 +763,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) ...@@ -763,6 +763,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH:
default: default:
adev->gmc.gart_size = 512ULL << 20; adev->gmc.gart_size = 512ULL << 20;
break; break;
...@@ -829,6 +830,7 @@ static int gmc_v10_0_sw_init(void *handle) ...@@ -829,6 +830,7 @@ static int gmc_v10_0_sw_init(void *handle)
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH:
adev->num_vmhubs = 2; adev->num_vmhubs = 2;
/* /*
* To fulfill 4-level page support, * To fulfill 4-level page support,
...@@ -943,6 +945,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -943,6 +945,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH:
break; break;
default: default:
break; break;
......
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