Commit a1b0b977 authored by Weijun Yang's avatar Weijun Yang Committed by Ulf Hansson

mmc: sdhci-sirf: fake version and capbility registers

chips have some issues for version and capbility registers, here we fake
them.
Signed-off-by: default avatarWeijun Yang <Weijun.Yang@csr.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent d1ba44a4
...@@ -219,6 +219,7 @@ config MMC_SDHCI_SIRF ...@@ -219,6 +219,7 @@ config MMC_SDHCI_SIRF
tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs" tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
depends on ARCH_SIRF depends on ARCH_SIRF
depends on MMC_SDHCI_PLTFM depends on MMC_SDHCI_PLTFM
select MMC_SDHCI_IO_ACCESSORS
help help
This selects the SDHCI support for SiRF System-on-Chip devices. This selects the SDHCI support for SiRF System-on-Chip devices.
......
...@@ -43,6 +43,39 @@ static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width) ...@@ -43,6 +43,39 @@ static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
} }
static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
{
u32 val = readl(host->ioaddr + reg);
if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
(host->mmc->caps & MMC_CAP_UHS_SDR50))) {
/* fake CAP_1 register */
val = SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
}
if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
u32 prss = val;
/* fake chips as V3.0 host conreoller */
prss &= ~(0xFF << 16);
val = prss | (SDHCI_SPEC_300 << 16);
}
return val;
}
static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
{
u16 ret = 0;
ret = readw(host->ioaddr + reg);
if (unlikely(reg == SDHCI_HOST_VERSION)) {
ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
ret |= SDHCI_SPEC_300;
}
return ret;
}
static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode) static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
{ {
int tuning_seq_cnt = 3; int tuning_seq_cnt = 3;
...@@ -113,6 +146,8 @@ static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode) ...@@ -113,6 +146,8 @@ static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
} }
static struct sdhci_ops sdhci_sirf_ops = { static struct sdhci_ops sdhci_sirf_ops = {
.read_l = sdhci_sirf_readl_le,
.read_w = sdhci_sirf_readw_le,
.platform_execute_tuning = sdhci_sirf_execute_tuning, .platform_execute_tuning = sdhci_sirf_execute_tuning,
.set_clock = sdhci_set_clock, .set_clock = sdhci_set_clock,
.get_max_clock = sdhci_pltfm_clk_get_max_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock,
......
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