Commit a1bc5cdf authored by Linus Torvalds's avatar Linus Torvalds
parents 8dca6f33 85953876
......@@ -628,9 +628,11 @@ static int pfm_write_ibr_dbr(int mode, pfm_context_t *ctx, void *arg, int count,
#include "perfmon_itanium.h"
#include "perfmon_mckinley.h"
#include "perfmon_montecito.h"
#include "perfmon_generic.h"
static pmu_config_t *pmu_confs[]={
&pmu_conf_mont,
&pmu_conf_mck,
&pmu_conf_ita,
&pmu_conf_gen, /* must be last */
......
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......@@ -635,3 +635,39 @@ mem_init (void)
ia32_mem_init();
#endif
}
#ifdef CONFIG_MEMORY_HOTPLUG
void online_page(struct page *page)
{
ClearPageReserved(page);
set_page_count(page, 1);
__free_page(page);
totalram_pages++;
num_physpages++;
}
int add_memory(u64 start, u64 size)
{
pg_data_t *pgdat;
struct zone *zone;
unsigned long start_pfn = start >> PAGE_SHIFT;
unsigned long nr_pages = size >> PAGE_SHIFT;
int ret;
pgdat = NODE_DATA(0);
zone = pgdat->node_zones + ZONE_NORMAL;
ret = __add_pages(zone, start_pfn, nr_pages);
if (ret)
printk("%s: Problem encountered in __add_pages() as ret=%d\n",
__FUNCTION__, ret);
return ret;
}
int remove_memory(u64 start, u64 size)
{
return -EINVAL;
}
#endif
......@@ -454,14 +454,13 @@ static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
return 0;
}
static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
static void __devinit
pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
{
struct pci_bus_region region;
int i;
int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \
PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
for (i = 0; i < limit; i++) {
for (i = start; i < limit; i++) {
if (!dev->resource[i].flags)
continue;
region.start = dev->resource[i].start;
......@@ -472,6 +471,16 @@ static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
}
}
static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
{
pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
}
static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
{
pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
}
/*
* Called after each bus is probed, but before its children are examined.
*/
......@@ -482,7 +491,7 @@ pcibios_fixup_bus (struct pci_bus *b)
if (b->self) {
pci_read_bridge_bases(b);
pcibios_fixup_device_resources(b->self);
pcibios_fixup_bridge_resources(b->self);
}
list_for_each_entry(dev, &b->devices, bus_list)
pcibios_fixup_device_resources(dev);
......
......@@ -40,8 +40,8 @@ struct sn_flush_device_common {
unsigned long sfdl_force_int_addr;
unsigned long sfdl_flush_value;
volatile unsigned long *sfdl_flush_addr;
uint32_t sfdl_persistent_busnum;
uint32_t sfdl_persistent_segment;
u32 sfdl_persistent_busnum;
u32 sfdl_persistent_segment;
struct pcibus_info *sfdl_pcibus_info;
};
......@@ -56,7 +56,7 @@ struct sn_flush_device_kernel {
*/
struct sn_flush_nasid_entry {
struct sn_flush_device_kernel **widget_p; // Used as an array of wid_num
uint64_t iio_itte[8];
u64 iio_itte[8];
};
struct hubdev_info {
......@@ -70,8 +70,8 @@ struct hubdev_info {
void *hdi_nodepda;
void *hdi_node_vertex;
uint32_t max_segment_number;
uint32_t max_pcibus_number;
u32 max_segment_number;
u32 max_pcibus_number;
};
extern void hubdev_init_node(nodepda_t *, cnodeid_t);
......
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......@@ -25,28 +25,28 @@
/* widget configuration registers */
struct widget_cfg{
uint32_t w_id; /* 0x04 */
uint32_t w_pad_0; /* 0x00 */
uint32_t w_status; /* 0x0c */
uint32_t w_pad_1; /* 0x08 */
uint32_t w_err_upper_addr; /* 0x14 */
uint32_t w_pad_2; /* 0x10 */
uint32_t w_err_lower_addr; /* 0x1c */
uint32_t w_pad_3; /* 0x18 */
uint32_t w_control; /* 0x24 */
uint32_t w_pad_4; /* 0x20 */
uint32_t w_req_timeout; /* 0x2c */
uint32_t w_pad_5; /* 0x28 */
uint32_t w_intdest_upper_addr; /* 0x34 */
uint32_t w_pad_6; /* 0x30 */
uint32_t w_intdest_lower_addr; /* 0x3c */
uint32_t w_pad_7; /* 0x38 */
uint32_t w_err_cmd_word; /* 0x44 */
uint32_t w_pad_8; /* 0x40 */
uint32_t w_llp_cfg; /* 0x4c */
uint32_t w_pad_9; /* 0x48 */
uint32_t w_tflush; /* 0x54 */
uint32_t w_pad_10; /* 0x50 */
u32 w_id; /* 0x04 */
u32 w_pad_0; /* 0x00 */
u32 w_status; /* 0x0c */
u32 w_pad_1; /* 0x08 */
u32 w_err_upper_addr; /* 0x14 */
u32 w_pad_2; /* 0x10 */
u32 w_err_lower_addr; /* 0x1c */
u32 w_pad_3; /* 0x18 */
u32 w_control; /* 0x24 */
u32 w_pad_4; /* 0x20 */
u32 w_req_timeout; /* 0x2c */
u32 w_pad_5; /* 0x28 */
u32 w_intdest_upper_addr; /* 0x34 */
u32 w_pad_6; /* 0x30 */
u32 w_intdest_lower_addr; /* 0x3c */
u32 w_pad_7; /* 0x38 */
u32 w_err_cmd_word; /* 0x44 */
u32 w_pad_8; /* 0x40 */
u32 w_llp_cfg; /* 0x4c */
u32 w_pad_9; /* 0x48 */
u32 w_tflush; /* 0x54 */
u32 w_pad_10; /* 0x50 */
};
/*
......@@ -63,7 +63,7 @@ struct xwidget_info{
struct xwidget_hwid xwi_hwid; /* Widget Identification */
char xwi_masterxid; /* Hub's Widget Port Number */
void *xwi_hubinfo; /* Hub's provider private info */
uint64_t *xwi_hub_provider; /* prom provider functions */
u64 *xwi_hub_provider; /* prom provider functions */
void *xwi_vertex;
};
......
......@@ -132,8 +132,8 @@ static inline u64 sal_get_pcibus_info(u64 segment, u64 busnum, u64 address)
* Retrieve the pci device information given the bus and device|function number.
*/
static inline u64
sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
u64 sn_irq_info)
sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
u64 sn_irq_info)
{
struct ia64_sal_retval ret_stuff;
ret_stuff.status = 0;
......@@ -141,7 +141,7 @@ sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
SAL_CALL_NOLOCK(ret_stuff,
(u64) SN_SAL_IOIF_GET_PCIDEV_INFO,
(u64) segment, (u64) bus_number, (u64) devfn,
(u64) segment, (u64) bus_number, (u64) devfn,
(u64) pci_dev,
sn_irq_info, 0, 0);
return ret_stuff.v0;
......@@ -268,7 +268,7 @@ static void sn_fixup_ionodes(void)
*/
static void
sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
int64_t * pci_addrs)
s64 * pci_addrs)
{
struct pci_controller *controller = PCI_CONTROLLER(dev->bus);
unsigned int i;
......@@ -328,7 +328,7 @@ void sn_pci_fixup_slot(struct pci_dev *dev)
struct pci_bus *host_pci_bus;
struct pci_dev *host_pci_dev;
struct pcidev_info *pcidev_info;
int64_t pci_addrs[PCI_ROM_RESOURCE + 1];
s64 pci_addrs[PCI_ROM_RESOURCE + 1];
struct sn_irq_info *sn_irq_info;
unsigned long size;
unsigned int bus_no, devfn;
......
......@@ -28,7 +28,7 @@ extern int sn_ioif_inited;
static struct list_head **sn_irq_lh;
static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */
static inline uint64_t sn_intr_alloc(nasid_t local_nasid, int local_widget,
static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
u64 sn_irq_info,
int req_irq, nasid_t req_nasid,
int req_slice)
......@@ -123,7 +123,7 @@ static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
sn_irq_lh[irq], list) {
uint64_t bridge;
u64 bridge;
int local_widget, status;
nasid_t local_nasid;
struct sn_irq_info *new_irq_info;
......@@ -134,7 +134,7 @@ static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
break;
memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
bridge = (uint64_t) new_irq_info->irq_bridge;
bridge = (u64) new_irq_info->irq_bridge;
if (!bridge) {
kfree(new_irq_info);
break; /* irq is not a device interrupt */
......@@ -349,10 +349,10 @@ static void force_interrupt(int irq)
*/
static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
{
uint64_t regval;
u64 regval;
int irr_reg_num;
int irr_bit;
uint64_t irr_reg;
u64 irr_reg;
struct pcidev_info *pcidev_info;
struct pcibus_info *pcibus_info;
......
......@@ -245,7 +245,7 @@ static int cx_device_reload(struct cx_dev *cx_dev)
cx_dev->bt);
}
static inline uint64_t tiocx_intr_alloc(nasid_t nasid, int widget,
static inline u64 tiocx_intr_alloc(nasid_t nasid, int widget,
u64 sn_irq_info,
int req_irq, nasid_t req_nasid,
int req_slice)
......@@ -302,7 +302,7 @@ struct sn_irq_info *tiocx_irq_alloc(nasid_t nasid, int widget, int irq,
void tiocx_irq_free(struct sn_irq_info *sn_irq_info)
{
uint64_t bridge = (uint64_t) sn_irq_info->irq_bridge;
u64 bridge = (u64) sn_irq_info->irq_bridge;
nasid_t nasid = NASID_GET(bridge);
int widget;
......@@ -313,12 +313,12 @@ void tiocx_irq_free(struct sn_irq_info *sn_irq_info)
}
}
uint64_t tiocx_dma_addr(uint64_t addr)
u64 tiocx_dma_addr(u64 addr)
{
return PHYS_TO_TIODMA(addr);
}
uint64_t tiocx_swin_base(int nasid)
u64 tiocx_swin_base(int nasid)
{
return TIO_SWIN_BASE(nasid, TIOCX_CORELET);
}
......@@ -335,8 +335,8 @@ EXPORT_SYMBOL(tiocx_swin_base);
static void tio_conveyor_set(nasid_t nasid, int enable_flag)
{
uint64_t ice_frz;
uint64_t disable_cb = (1ull << 61);
u64 ice_frz;
u64 disable_cb = (1ull << 61);
if (!(nasid & 1))
return;
......@@ -388,7 +388,7 @@ static int is_fpga_tio(int nasid, int *bt)
static int bitstream_loaded(nasid_t nasid)
{
uint64_t cx_credits;
u64 cx_credits;
cx_credits = REMOTE_HUB_L(nasid, TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3);
cx_credits &= TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK;
......@@ -404,14 +404,14 @@ static int tiocx_reload(struct cx_dev *cx_dev)
nasid_t nasid = cx_dev->cx_id.nasid;
if (bitstream_loaded(nasid)) {
uint64_t cx_id;
u64 cx_id;
int rv;
rv = ia64_sn_sysctl_tio_clock_reset(nasid);
if (rv) {
printk(KERN_ALERT "CX port JTAG reset failed.\n");
} else {
cx_id = *(volatile uint64_t *)
cx_id = *(volatile u64 *)
(TIO_SWIN_BASE(nasid, TIOCX_CORELET) +
WIDGET_ID);
part_num = XWIDGET_PART_NUM(cx_id);
......
......@@ -18,10 +18,10 @@ int pcibr_invalidate_ate = 0; /* by default don't invalidate ATE on free */
* mark_ate: Mark the ate as either free or inuse.
*/
static void mark_ate(struct ate_resource *ate_resource, int start, int number,
uint64_t value)
u64 value)
{
uint64_t *ate = ate_resource->ate;
u64 *ate = ate_resource->ate;
int index;
int length = 0;
......@@ -38,7 +38,7 @@ static int find_free_ate(struct ate_resource *ate_resource, int start,
int count)
{
uint64_t *ate = ate_resource->ate;
u64 *ate = ate_resource->ate;
int index;
int start_free;
......@@ -119,7 +119,7 @@ static inline int alloc_ate_resource(struct ate_resource *ate_resource,
int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count)
{
int status = 0;
uint64_t flag;
u64 flag;
flag = pcibr_lock(pcibus_info);
status = alloc_ate_resource(&pcibus_info->pbi_int_ate_resource, count);
......@@ -139,7 +139,7 @@ int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count)
* Setup an Address Translation Entry as specified. Use either the Bridge
* internal maps or the external map RAM, as appropriate.
*/
static inline uint64_t *pcibr_ate_addr(struct pcibus_info *pcibus_info,
static inline u64 *pcibr_ate_addr(struct pcibus_info *pcibus_info,
int ate_index)
{
if (ate_index < pcibus_info->pbi_int_ate_size) {
......@@ -153,7 +153,7 @@ static inline uint64_t *pcibr_ate_addr(struct pcibus_info *pcibus_info,
*/
void inline
ate_write(struct pcibus_info *pcibus_info, int ate_index, int count,
volatile uint64_t ate)
volatile u64 ate)
{
while (count-- > 0) {
if (ate_index < pcibus_info->pbi_int_ate_size) {
......@@ -171,9 +171,9 @@ ate_write(struct pcibus_info *pcibus_info, int ate_index, int count,
void pcibr_ate_free(struct pcibus_info *pcibus_info, int index)
{
volatile uint64_t ate;
volatile u64 ate;
int count;
uint64_t flags;
u64 flags;
if (pcibr_invalidate_ate) {
/* For debugging purposes, clear the valid bit in the ATE */
......
......@@ -41,21 +41,21 @@ extern int sn_ioif_inited;
static dma_addr_t
pcibr_dmamap_ate32(struct pcidev_info *info,
uint64_t paddr, size_t req_size, uint64_t flags)
u64 paddr, size_t req_size, u64 flags)
{
struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
pdi_pcibus_info;
uint8_t internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info->
u8 internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info->
pdi_linux_pcidev->devfn)) - 1;
int ate_count;
int ate_index;
uint64_t ate_flags = flags | PCI32_ATE_V;
uint64_t ate;
uint64_t pci_addr;
uint64_t xio_addr;
uint64_t offset;
u64 ate_flags = flags | PCI32_ATE_V;
u64 ate;
u64 pci_addr;
u64 xio_addr;
u64 offset;
/* PIC in PCI-X mode does not supports 32bit PageMap mode */
if (IS_PIC_SOFT(pcibus_info) && IS_PCIX(pcibus_info)) {
......@@ -109,12 +109,12 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
}
static dma_addr_t
pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
uint64_t dma_attributes)
pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
u64 dma_attributes)
{
struct pcibus_info *pcibus_info = (struct pcibus_info *)
((info->pdi_host_pcidev_info)->pdi_pcibus_info);
uint64_t pci_addr;
u64 pci_addr;
/* Translate to Crosstalk View of Physical Address */
pci_addr = (IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
......@@ -127,7 +127,7 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
/* Handle Bridge Chipset differences */
if (IS_PIC_SOFT(pcibus_info)) {
pci_addr |=
((uint64_t) pcibus_info->
((u64) pcibus_info->
pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT);
} else
pci_addr |= TIOCP_PCI64_CMDTYPE_MEM;
......@@ -142,17 +142,17 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
static dma_addr_t
pcibr_dmatrans_direct32(struct pcidev_info * info,
uint64_t paddr, size_t req_size, uint64_t flags)
u64 paddr, size_t req_size, u64 flags)
{
struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
pdi_pcibus_info;
uint64_t xio_addr;
u64 xio_addr;
uint64_t xio_base;
uint64_t offset;
uint64_t endoff;
u64 xio_base;
u64 offset;
u64 endoff;
if (IS_PCIX(pcibus_info)) {
return 0;
......@@ -209,14 +209,14 @@ pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction)
* unlike the PIC Device(x) Write Request Buffer Flush register.
*/
void sn_dma_flush(uint64_t addr)
void sn_dma_flush(u64 addr)
{
nasid_t nasid;
int is_tio;
int wid_num;
int i, j;
uint64_t flags;
uint64_t itte;
u64 flags;
u64 itte;
struct hubdev_info *hubinfo;
volatile struct sn_flush_device_kernel *p;
volatile struct sn_flush_device_common *common;
......@@ -299,8 +299,8 @@ void sn_dma_flush(uint64_t addr)
* If CE ever needs the sn_dma_flush mechanism, we will have
* to account for that here and in tioce_bus_fixup().
*/
uint32_t tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID));
uint32_t revnum = XWIDGET_PART_REV_NUM(tio_id);
u32 tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID));
u32 revnum = XWIDGET_PART_REV_NUM(tio_id);
/* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */
if ((1 << XWIDGET_PART_REV_NUM_REV(revnum)) & PV907516) {
......@@ -315,7 +315,7 @@ void sn_dma_flush(uint64_t addr)
*common->sfdl_flush_addr = 0;
/* force an interrupt. */
*(volatile uint32_t *)(common->sfdl_force_int_addr) = 1;
*(volatile u32 *)(common->sfdl_force_int_addr) = 1;
/* wait for the interrupt to come back. */
while (*(common->sfdl_flush_addr) != 0x10f)
......
......@@ -23,7 +23,7 @@ int
sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp)
{
struct ia64_sal_retval ret_stuff;
uint64_t busnum;
u64 busnum;
ret_stuff.status = 0;
ret_stuff.v0 = 0;
......@@ -40,7 +40,7 @@ sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
void *resp)
{
struct ia64_sal_retval ret_stuff;
uint64_t busnum;
u64 busnum;
ret_stuff.status = 0;
ret_stuff.v0 = 0;
......@@ -56,7 +56,7 @@ sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
{
struct ia64_sal_retval ret_stuff;
uint64_t busnum;
u64 busnum;
int segment;
ret_stuff.status = 0;
ret_stuff.v0 = 0;
......@@ -159,9 +159,9 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
/* Setup the PMU ATE map */
soft->pbi_int_ate_resource.lowest_free_index = 0;
soft->pbi_int_ate_resource.ate =
kmalloc(soft->pbi_int_ate_size * sizeof(uint64_t), GFP_KERNEL);
kmalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
memset(soft->pbi_int_ate_resource.ate, 0,
(soft->pbi_int_ate_size * sizeof(uint64_t)));
(soft->pbi_int_ate_size * sizeof(u64)));
if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) {
/* TIO PCI Bridge: find nearest node with CPUs */
......@@ -203,7 +203,7 @@ void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
struct pcidev_info *pcidev_info;
struct pcibus_info *pcibus_info;
int bit = sn_irq_info->irq_int_bit;
uint64_t xtalk_addr = sn_irq_info->irq_xtalkaddr;
u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
if (pcidev_info) {
......
......@@ -23,7 +23,7 @@ union br_ptr {
/*
* Control Register Access -- Read/Write 0000_0020
*/
void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
......@@ -43,7 +43,7 @@ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
}
}
void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u64 bits)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
......@@ -66,10 +66,10 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
/*
* PCI/PCIX Target Flush Register Access -- Read Only 0000_0050
*/
uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
u64 pcireg_tflush_get(struct pcibus_info *pcibus_info)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
u64 ret = 0;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
......@@ -96,10 +96,10 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
/*
* Interrupt Status Register Access -- Read Only 0000_0100
*/
uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
u64 pcireg_intr_status_get(struct pcibus_info * pcibus_info)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
u64 ret = 0;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
......@@ -121,7 +121,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
/*
* Interrupt Enable Register Access -- Read/Write 0000_0108
*/
void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
......@@ -141,7 +141,7 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
}
}
void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u64 bits)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
......@@ -165,7 +165,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
* Intr Host Address Register (int_addr) -- Read/Write 0000_0130 - 0000_0168
*/
void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
uint64_t addr)
u64 addr)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
......@@ -217,10 +217,10 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
/*
* Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
*/
uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
u64 pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
u64 ret = 0;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
......@@ -242,7 +242,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
}
void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
uint64_t val)
u64 val)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
......@@ -262,10 +262,10 @@ void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
}
}
uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
u64 __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
{
union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t __iomem *ret = NULL;
u64 __iomem *ret = NULL;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
......
......@@ -16,7 +16,7 @@
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/tioca_provider.h>
uint32_t tioca_gart_found;
u32 tioca_gart_found;
EXPORT_SYMBOL(tioca_gart_found); /* used by agp-sgi */
LIST_HEAD(tioca_list);
......@@ -34,8 +34,8 @@ static int tioca_gart_init(struct tioca_kernel *);
static int
tioca_gart_init(struct tioca_kernel *tioca_kern)
{
uint64_t ap_reg;
uint64_t offset;
u64 ap_reg;
u64 offset;
struct page *tmp;
struct tioca_common *tioca_common;
struct tioca __iomem *ca_base;
......@@ -214,7 +214,7 @@ void
tioca_fastwrite_enable(struct tioca_kernel *tioca_kern)
{
int cap_ptr;
uint32_t reg;
u32 reg;
struct tioca __iomem *tioca_base;
struct pci_dev *pdev;
struct tioca_common *common;
......@@ -276,7 +276,7 @@ EXPORT_SYMBOL(tioca_fastwrite_enable); /* used by agp-sgi */
* We will always use 0x1
* 55:55 - Swap bytes Currently unused
*/
static uint64_t
static u64
tioca_dma_d64(unsigned long paddr)
{
dma_addr_t bus_addr;
......@@ -318,15 +318,15 @@ tioca_dma_d64(unsigned long paddr)
* and so a given CA can only directly target nodes in the range
* xxx - xxx+255.
*/
static uint64_t
tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr)
static u64
tioca_dma_d48(struct pci_dev *pdev, u64 paddr)
{
struct tioca_common *tioca_common;
struct tioca __iomem *ca_base;
uint64_t ct_addr;
u64 ct_addr;
dma_addr_t bus_addr;
uint32_t node_upper;
uint64_t agp_dma_extn;
u32 node_upper;
u64 agp_dma_extn;
struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
......@@ -367,10 +367,10 @@ tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr)
* dma_addr_t is guarenteed to be contiguous in CA bus space.
*/
static dma_addr_t
tioca_dma_mapped(struct pci_dev *pdev, uint64_t paddr, size_t req_size)
tioca_dma_mapped(struct pci_dev *pdev, u64 paddr, size_t req_size)
{
int i, ps, ps_shift, entry, entries, mapsize, last_entry;
uint64_t xio_addr, end_xio_addr;
u64 xio_addr, end_xio_addr;
struct tioca_common *tioca_common;
struct tioca_kernel *tioca_kern;
dma_addr_t bus_addr = 0;
......@@ -514,10 +514,10 @@ tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
* The mapping mode used is based on the devices dma_mask. As a last resort
* use the GART mapped mode.
*/
static uint64_t
tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
static u64
tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count)
{
uint64_t mapaddr;
u64 mapaddr;
/*
* If card is 64 or 48 bit addresable, use a direct mapping. 32
......@@ -554,8 +554,8 @@ tioca_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
{
struct tioca_common *soft = arg;
struct ia64_sal_retval ret_stuff;
uint64_t segment;
uint64_t busnum;
u64 segment;
u64 busnum;
ret_stuff.status = 0;
ret_stuff.v0 = 0;
......@@ -620,7 +620,7 @@ tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
INIT_LIST_HEAD(&tioca_kern->ca_dmamaps);
tioca_kern->ca_closest_node =
nasid_to_cnodeid(tioca_common->ca_closest_nasid);
tioca_common->ca_kernel_private = (uint64_t) tioca_kern;
tioca_common->ca_kernel_private = (u64) tioca_kern;
bus = pci_find_bus(tioca_common->ca_common.bs_persist_segment,
tioca_common->ca_common.bs_persist_busnum);
......
......@@ -81,10 +81,10 @@
* 61 - 0 since this is not an MSI transaction
* 60:54 - reserved, MBZ
*/
static uint64_t
static u64
tioce_dma_d64(unsigned long ct_addr)
{
uint64_t bus_addr;
u64 bus_addr;
bus_addr = ct_addr | (1UL << 63);
......@@ -141,9 +141,9 @@ pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base,
* length, and if enough resources exist, fill in the ATE's and construct a
* tioce_dmamap struct to track the mapping.
*/
static uint64_t
static u64
tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
uint64_t ct_addr, int len)
u64 ct_addr, int len)
{
int i;
int j;
......@@ -152,11 +152,11 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
int entries;
int nates;
int pagesize;
uint64_t *ate_shadow;
uint64_t *ate_reg;
uint64_t addr;
u64 *ate_shadow;
u64 *ate_reg;
u64 addr;
struct tioce *ce_mmr;
uint64_t bus_base;
u64 bus_base;
struct tioce_dmamap *map;
ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
......@@ -224,7 +224,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
addr = ct_addr;
for (j = 0; j < nates; j++) {
uint64_t ate;
u64 ate;
ate = ATE_MAKE(addr, pagesize);
ate_shadow[i + j] = ate;
......@@ -252,15 +252,15 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
*
* Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
*/
static uint64_t
tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr)
static u64
tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr)
{
int dma_ok;
int port;
struct tioce *ce_mmr;
struct tioce_kernel *ce_kern;
uint64_t ct_upper;
uint64_t ct_lower;
u64 ct_upper;
u64 ct_lower;
dma_addr_t bus_addr;
ct_upper = ct_addr & ~0x3fffffffUL;
......@@ -269,7 +269,7 @@ tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr)
pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
if (ce_kern->ce_port[port].dirmap_refcnt == 0) {
uint64_t tmp;
u64 tmp;
ce_kern->ce_port[port].dirmap_shadow = ct_upper;
writeq(ct_upper, &ce_mmr->ce_ure_dir_map[port]);
......@@ -295,10 +295,10 @@ tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr)
* Given a TIOCE bus address, set the appropriate bit to indicate barrier
* attributes.
*/
static uint64_t
tioce_dma_barrier(uint64_t bus_addr, int on)
static u64
tioce_dma_barrier(u64 bus_addr, int on)
{
uint64_t barrier_bit;
u64 barrier_bit;
/* barrier not supported in M40/M40S mode */
if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr))
......@@ -351,7 +351,7 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
list_for_each_entry(map, &ce_kern->ce_dmamap_list,
ce_dmamap_list) {
uint64_t last;
u64 last;
last = map->pci_start + map->nbytes - 1;
if (bus_addr >= map->pci_start && bus_addr <= last)
......@@ -385,17 +385,17 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
* This is the main wrapper for mapping host physical pages to CE PCI space.
* The mapping mode used is based on the device's dma_mask.
*/
static uint64_t
tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count,
static u64
tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
int barrier)
{
unsigned long flags;
uint64_t ct_addr;
uint64_t mapaddr = 0;
u64 ct_addr;
u64 mapaddr = 0;
struct tioce_kernel *ce_kern;
struct tioce_dmamap *map;
int port;
uint64_t dma_mask;
u64 dma_mask;
dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask;
......@@ -425,7 +425,7 @@ tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count,
* address bits than this device can support.
*/
list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) {
uint64_t last;
u64 last;
last = map->ct_start + map->nbytes - 1;
if (ct_addr >= map->ct_start &&
......@@ -501,8 +501,8 @@ tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count,
* Simply call tioce_do_dma_map() to create a map with the barrier bit clear
* in the address.
*/
static uint64_t
tioce_dma(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
static u64
tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count)
{
return tioce_do_dma_map(pdev, paddr, byte_count, 0);
}
......@@ -515,8 +515,8 @@ tioce_dma(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
*
* Simply call tioce_do_dma_map() to create a map with the barrier bit set
* in the address.
*/ static uint64_t
tioce_dma_consistent(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
*/ static u64
tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count)
{
return tioce_do_dma_map(pdev, paddr, byte_count, 1);
}
......@@ -551,7 +551,7 @@ tioce_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
tioce_kern_init(struct tioce_common *tioce_common)
{
int i;
uint32_t tmp;
u32 tmp;
struct tioce *tioce_mmr;
struct tioce_kernel *tioce_kern;
......@@ -563,7 +563,7 @@ tioce_kern_init(struct tioce_common *tioce_common)
tioce_kern->ce_common = tioce_common;
spin_lock_init(&tioce_kern->ce_lock);
INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list);
tioce_common->ce_kernel_private = (uint64_t) tioce_kern;
tioce_common->ce_kernel_private = (u64) tioce_kern;
/*
* Determine the secondary bus number of the port2 logical PPB.
......@@ -575,7 +575,7 @@ tioce_kern_init(struct tioce_common *tioce_common)
raw_pci_ops->read(tioce_common->ce_pcibus.bs_persist_segment,
tioce_common->ce_pcibus.bs_persist_busnum,
PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1, &tmp);
tioce_kern->ce_port1_secondary = (uint8_t) tmp;
tioce_kern->ce_port1_secondary = (u8) tmp;
/*
* Set PMU pagesize to the largest size available, and zero out
......@@ -615,7 +615,7 @@ tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
struct pcidev_info *pcidev_info;
struct tioce_common *ce_common;
struct tioce *ce_mmr;
uint64_t force_int_val;
u64 force_int_val;
if (!sn_irq_info->irq_bridge)
return;
......@@ -687,7 +687,7 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
struct tioce_common *ce_common;
struct tioce *ce_mmr;
int bit;
uint64_t vector;
u64 vector;
pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
if (!pcidev_info)
......@@ -699,7 +699,7 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
bit = sn_irq_info->irq_int_bit;
__sn_setq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit));
vector = (uint64_t)sn_irq_info->irq_irq << INTR_VECTOR_SHFT;
vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT;
vector |= sn_irq_info->irq_xtalkaddr;
writeq(vector, &ce_mmr->ce_adm_int_dest[bit]);
__sn_clrq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit));
......
......@@ -927,7 +927,7 @@ static inline s64
ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
{
struct ia64_pal_retval iprv;
PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
if (vector)
*vector = iprv.v0;
*progress = iprv.v1;
......
......@@ -25,8 +25,8 @@
* Limits for PMC and PMD are set to less than maximum architected values
* but should be sufficient for a while
*/
#define IA64_NUM_PMC_REGS 32
#define IA64_NUM_PMD_REGS 32
#define IA64_NUM_PMC_REGS 64
#define IA64_NUM_PMD_REGS 64
#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
......
......@@ -40,7 +40,7 @@ struct sn_irq_info {
int irq_cpuid; /* kernel logical cpuid */
int irq_irq; /* the IRQ number */
int irq_int_bit; /* Bridge interrupt pin */
uint64_t irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
int irq_bridge_type;/* pciio asic type (pciio.h) */
void *irq_bridge; /* bridge generating irq */
void *irq_pciioinfo; /* associated pciio_info_t */
......
......@@ -44,9 +44,9 @@
#define PCI32_MAPPED_BASE 0x40000000
#define PCI32_DIRECT_BASE 0x80000000
#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \
(uint64_t)(x) >= PCI32_MAPPED_BASE)
#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE)
#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
(u64)(x) >= PCI32_MAPPED_BASE)
#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
/*
......@@ -63,7 +63,7 @@
(IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
#define MINIMAL_ATE_FLAG(addr, size) \
(MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
(MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
/* bit 29 of the pci address is the SWAP bit */
#define ATE_SWAPSHIFT 29
......@@ -90,27 +90,27 @@
* PMU resources.
*/
struct ate_resource{
uint64_t *ate;
uint64_t num_ate;
uint64_t lowest_free_index;
u64 *ate;
u64 num_ate;
u64 lowest_free_index;
};
struct pcibus_info {
struct pcibus_bussoft pbi_buscommon; /* common header */
uint32_t pbi_moduleid;
u32 pbi_moduleid;
short pbi_bridge_type;
short pbi_bridge_mode;
struct ate_resource pbi_int_ate_resource;
uint64_t pbi_int_ate_size;
u64 pbi_int_ate_size;
uint64_t pbi_dir_xbase;
u64 pbi_dir_xbase;
char pbi_hub_xid;
uint64_t pbi_devreg[8];
u64 pbi_devreg[8];
uint32_t pbi_valid_devices;
uint32_t pbi_enabled_devices;
u32 pbi_valid_devices;
u32 pbi_enabled_devices;
spinlock_t pbi_lock;
};
......@@ -136,22 +136,22 @@ extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
/*
* prototypes for the bridge asic register access routines in pcibr_reg.c
*/
extern void pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
extern void pcireg_control_bit_set(struct pcibus_info *, uint64_t);
extern uint64_t pcireg_tflush_get(struct pcibus_info *);
extern uint64_t pcireg_intr_status_get(struct pcibus_info *);
extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
extern void pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
extern void pcireg_control_bit_set(struct pcibus_info *, u64);
extern u64 pcireg_tflush_get(struct pcibus_info *);
extern u64 pcireg_intr_status_get(struct pcibus_info *);
extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
extern void pcireg_force_intr_set(struct pcibus_info *, int);
extern uint64_t pcireg_wrb_flush_get(struct pcibus_info *, int);
extern void pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
extern uint64_t * pcireg_int_ate_addr(struct pcibus_info *, int);
extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
extern u64 * pcireg_int_ate_addr(struct pcibus_info *, int);
extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
extern int pcibr_ate_alloc(struct pcibus_info *, int);
extern void pcibr_ate_free(struct pcibus_info *, int);
extern void ate_write(struct pcibus_info *, int, int, uint64_t);
extern void ate_write(struct pcibus_info *, int, int, u64);
extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
void *resp);
extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
......
......@@ -29,13 +29,13 @@
*/
struct pcibus_bussoft {
uint32_t bs_asic_type; /* chipset type */
uint32_t bs_xid; /* xwidget id */
uint32_t bs_persist_busnum; /* Persistent Bus Number */
uint32_t bs_persist_segment; /* Segment Number */
uint64_t bs_legacy_io; /* legacy io pio addr */
uint64_t bs_legacy_mem; /* legacy mem pio addr */
uint64_t bs_base; /* widget base */
u32 bs_asic_type; /* chipset type */
u32 bs_xid; /* xwidget id */
u32 bs_persist_busnum; /* Persistent Bus Number */
u32 bs_persist_segment; /* Segment Number */
u64 bs_legacy_io; /* legacy io pio addr */
u64 bs_legacy_mem; /* legacy mem pio addr */
u64 bs_base; /* widget base */
struct xwidget_info *bs_xwidget_info;
};
......
......@@ -55,8 +55,8 @@ struct sn_pci_controller {
#define PCIIO_VENDOR_ID_NONE (-1)
struct pcidev_info {
uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
......
This diff is collapsed.
This diff is collapsed.
......@@ -273,7 +273,7 @@ ia64_sn_console_putc(char ch)
ret_stuff.v0 = 0;
ret_stuff.v1 = 0;
ret_stuff.v2 = 0;
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0);
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
return ret_stuff.status;
}
......@@ -290,7 +290,7 @@ ia64_sn_console_putb(const char *buf, int len)
ret_stuff.v0 = 0;
ret_stuff.v1 = 0;
ret_stuff.v2 = 0;
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0);
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
if ( ret_stuff.status == 0 ) {
return ret_stuff.v0;
......@@ -310,7 +310,7 @@ ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
ret_stuff.v0 = 0;
ret_stuff.v1 = 0;
ret_stuff.v2 = 0;
SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0);
SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
return ret_stuff.status;
}
......@@ -398,7 +398,7 @@ ia64_sn_console_intr_status(void)
* Enable an interrupt on the SAL console device.
*/
static inline void
ia64_sn_console_intr_enable(uint64_t intr)
ia64_sn_console_intr_enable(u64 intr)
{
struct ia64_sal_retval ret_stuff;
......@@ -415,7 +415,7 @@ ia64_sn_console_intr_enable(uint64_t intr)
* Disable an interrupt on the SAL console device.
*/
static inline void
ia64_sn_console_intr_disable(uint64_t intr)
ia64_sn_console_intr_disable(u64 intr)
{
struct ia64_sal_retval ret_stuff;
......@@ -441,7 +441,7 @@ ia64_sn_console_xmit_chars(char *buf, int len)
ret_stuff.v1 = 0;
ret_stuff.v2 = 0;
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
(uint64_t)buf, (uint64_t)len,
(u64)buf, (u64)len,
0, 0, 0, 0, 0);
if (ret_stuff.status == 0) {
......
......@@ -19,47 +19,47 @@
*/
struct tioca {
uint64_t ca_id; /* 0x000000 */
uint64_t ca_control1; /* 0x000008 */
uint64_t ca_control2; /* 0x000010 */
uint64_t ca_status1; /* 0x000018 */
uint64_t ca_status2; /* 0x000020 */
uint64_t ca_gart_aperature; /* 0x000028 */
uint64_t ca_gfx_detach; /* 0x000030 */
uint64_t ca_inta_dest_addr; /* 0x000038 */
uint64_t ca_intb_dest_addr; /* 0x000040 */
uint64_t ca_err_int_dest_addr; /* 0x000048 */
uint64_t ca_int_status; /* 0x000050 */
uint64_t ca_int_status_alias; /* 0x000058 */
uint64_t ca_mult_error; /* 0x000060 */
uint64_t ca_mult_error_alias; /* 0x000068 */
uint64_t ca_first_error; /* 0x000070 */
uint64_t ca_int_mask; /* 0x000078 */
uint64_t ca_crm_pkterr_type; /* 0x000080 */
uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */
uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */
uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */
uint64_t ca_crm_tnumto; /* 0x0000A0 */
uint64_t ca_gart_err; /* 0x0000A8 */
uint64_t ca_pcierr_type; /* 0x0000B0 */
uint64_t ca_pcierr_addr; /* 0x0000B8 */
uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */
uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */
uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */
uint64_t ca_force_inta; /* 0x0000F0 */
uint64_t ca_force_intb; /* 0x0000F8 */
uint64_t ca_debug_vector_sel; /* 0x000100 */
uint64_t ca_debug_mux_core_sel; /* 0x000108 */
uint64_t ca_debug_mux_pci_sel; /* 0x000110 */
uint64_t ca_debug_domain_sel; /* 0x000118 */
uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */
uint64_t ca_gart_ptr_table; /* 0x200 */
uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */
u64 ca_id; /* 0x000000 */
u64 ca_control1; /* 0x000008 */
u64 ca_control2; /* 0x000010 */
u64 ca_status1; /* 0x000018 */
u64 ca_status2; /* 0x000020 */
u64 ca_gart_aperature; /* 0x000028 */
u64 ca_gfx_detach; /* 0x000030 */
u64 ca_inta_dest_addr; /* 0x000038 */
u64 ca_intb_dest_addr; /* 0x000040 */
u64 ca_err_int_dest_addr; /* 0x000048 */
u64 ca_int_status; /* 0x000050 */
u64 ca_int_status_alias; /* 0x000058 */
u64 ca_mult_error; /* 0x000060 */
u64 ca_mult_error_alias; /* 0x000068 */
u64 ca_first_error; /* 0x000070 */
u64 ca_int_mask; /* 0x000078 */
u64 ca_crm_pkterr_type; /* 0x000080 */
u64 ca_crm_pkterr_type_alias; /* 0x000088 */
u64 ca_crm_ct_error_detail_1; /* 0x000090 */
u64 ca_crm_ct_error_detail_2; /* 0x000098 */
u64 ca_crm_tnumto; /* 0x0000A0 */
u64 ca_gart_err; /* 0x0000A8 */
u64 ca_pcierr_type; /* 0x0000B0 */
u64 ca_pcierr_addr; /* 0x0000B8 */
u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
u64 ca_force_inta; /* 0x0000F0 */
u64 ca_force_intb; /* 0x0000F8 */
u64 ca_debug_vector_sel; /* 0x000100 */
u64 ca_debug_mux_core_sel; /* 0x000108 */
u64 ca_debug_mux_pci_sel; /* 0x000110 */
u64 ca_debug_domain_sel; /* 0x000118 */
u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
u64 ca_gart_ptr_table; /* 0x200 */
u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
};
/*
......
......@@ -56,31 +56,31 @@ struct tioca_kernel {
/*
* General GART stuff
*/
uint64_t ca_ap_size; /* size of aperature in bytes */
uint32_t ca_gart_entries; /* # uint64_t entries in gart */
uint32_t ca_ap_pagesize; /* aperature page size in bytes */
uint64_t ca_ap_bus_base; /* bus address of CA aperature */
uint64_t ca_gart_size; /* gart size in bytes */
uint64_t *ca_gart; /* gart table vaddr */
uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */
uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */
u64 ca_ap_size; /* size of aperature in bytes */
u32 ca_gart_entries; /* # u64 entries in gart */
u32 ca_ap_pagesize; /* aperature page size in bytes */
u64 ca_ap_bus_base; /* bus address of CA aperature */
u64 ca_gart_size; /* gart size in bytes */
u64 *ca_gart; /* gart table vaddr */
u64 ca_gart_coretalk_addr; /* gart coretalk addr */
u8 ca_gart_iscoherent; /* used in tioca_tlbflush */
/* PCI GART convenience values */
uint64_t ca_pciap_base; /* pci aperature bus base address */
uint64_t ca_pciap_size; /* pci aperature size (bytes) */
uint64_t ca_pcigart_base; /* gfx GART bus base address */
uint64_t *ca_pcigart; /* gfx GART vm address */
uint32_t ca_pcigart_entries;
uint32_t ca_pcigart_start; /* PCI start index in ca_gart */
u64 ca_pciap_base; /* pci aperature bus base address */
u64 ca_pciap_size; /* pci aperature size (bytes) */
u64 ca_pcigart_base; /* gfx GART bus base address */
u64 *ca_pcigart; /* gfx GART vm address */
u32 ca_pcigart_entries;
u32 ca_pcigart_start; /* PCI start index in ca_gart */
void *ca_pcigart_pagemap;
/* AGP GART convenience values */
uint64_t ca_gfxap_base; /* gfx aperature bus base address */
uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */
uint64_t ca_gfxgart_base; /* gfx GART bus base address */
uint64_t *ca_gfxgart; /* gfx GART vm address */
uint32_t ca_gfxgart_entries;
uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */
u64 ca_gfxap_base; /* gfx aperature bus base address */
u64 ca_gfxap_size; /* gfx aperature size (bytes) */
u64 ca_gfxgart_base; /* gfx GART bus base address */
u64 *ca_gfxgart; /* gfx GART vm address */
u32 ca_gfxgart_entries;
u32 ca_gfxgart_start; /* agpgart start index in ca_gart */
};
/*
......@@ -93,11 +93,11 @@ struct tioca_kernel {
struct tioca_common {
struct pcibus_bussoft ca_common; /* common pciio header */
uint32_t ca_rev;
uint32_t ca_closest_nasid;
u32 ca_rev;
u32 ca_closest_nasid;
uint64_t ca_prom_private;
uint64_t ca_kernel_private;
u64 ca_prom_private;
u64 ca_kernel_private;
};
/**
......@@ -139,9 +139,9 @@ tioca_paddr_to_gart(unsigned long paddr)
*/
static inline unsigned long
tioca_physpage_to_gart(uint64_t page_addr)
tioca_physpage_to_gart(u64 page_addr)
{
uint64_t coretalk_addr;
u64 coretalk_addr;
coretalk_addr = PHYS_TO_TIODMA(page_addr);
if (!coretalk_addr) {
......@@ -161,7 +161,7 @@ tioca_physpage_to_gart(uint64_t page_addr)
static inline void
tioca_tlbflush(struct tioca_kernel *tioca_kernel)
{
volatile uint64_t tmp;
volatile u64 tmp;
volatile struct tioca *ca_base;
struct tioca_common *tioca_common;
......@@ -200,7 +200,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
tmp = __sn_readq_relaxed(&ca_base->ca_control2);
}
extern uint32_t tioca_gart_found;
extern u32 tioca_gart_found;
extern struct list_head tioca_list;
extern int tioca_init_provider(void);
extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
......
This diff is collapsed.
......@@ -21,9 +21,9 @@
struct tioce_common {
struct pcibus_bussoft ce_pcibus; /* common pciio header */
uint32_t ce_rev;
uint64_t ce_kernel_private;
uint64_t ce_prom_private;
u32 ce_rev;
u64 ce_kernel_private;
u64 ce_prom_private;
};
struct tioce_kernel {
......@@ -31,31 +31,31 @@ struct tioce_kernel {
spinlock_t ce_lock;
struct list_head ce_dmamap_list;
uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES];
uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
uint32_t ce_ate3240_pagesize;
u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES];
u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
u32 ce_ate3240_pagesize;
uint8_t ce_port1_secondary;
u8 ce_port1_secondary;
/* per-port resources */
struct {
int dirmap_refcnt;
uint64_t dirmap_shadow;
u64 dirmap_shadow;
} ce_port[TIOCE_NUM_PORTS];
};
struct tioce_dmamap {
struct list_head ce_dmamap_list; /* headed by tioce_kernel */
uint32_t refcnt;
u32 refcnt;
uint64_t nbytes; /* # bytes mapped */
u64 nbytes; /* # bytes mapped */
uint64_t ct_start; /* coretalk start address */
uint64_t pci_start; /* bus start address */
u64 ct_start; /* coretalk start address */
u64 pci_start; /* bus start address */
uint64_t *ate_hw; /* hw ptr of first ate in map */
uint64_t *ate_shadow; /* shadow ptr of firat ate */
uint16_t ate_count; /* # ate's in the map */
u64 *ate_hw; /* hw ptr of first ate in map */
u64 *ate_shadow; /* shadow ptr of firat ate */
u16 ate_count; /* # ate's in the map */
};
extern int tioce_init_provider(void);
......
This diff is collapsed.
......@@ -40,10 +40,10 @@ struct cx_drv {
};
/* create DMA address by stripping AS bits */
#define TIOCX_DMA_ADDR(a) (uint64_t)((uint64_t)(a) & 0xffffcfffffffffUL)
#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
#define TIOCX_TO_TIOCX_DMA_ADDR(a) (uint64_t)(((uint64_t)(a) & 0xfffffffff) | \
((((uint64_t)(a)) & 0xffffc000000000UL) <<2))
#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \
((((u64)(a)) & 0xffffc000000000UL) <<2))
#define TIO_CE_ASIC_PARTNUM 0xce00
#define TIOCX_CORELET 3
......@@ -63,10 +63,10 @@ extern int cx_device_unregister(struct cx_dev *);
extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
extern int cx_driver_unregister(struct cx_drv *);
extern int cx_driver_register(struct cx_drv *);
extern uint64_t tiocx_dma_addr(uint64_t addr);
extern uint64_t tiocx_swin_base(int nasid);
extern void tiocx_mmr_store(int nasid, uint64_t offset, uint64_t value);
extern uint64_t tiocx_mmr_load(int nasid, uint64_t offset);
extern u64 tiocx_dma_addr(u64 addr);
extern u64 tiocx_swin_base(int nasid);
extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
extern u64 tiocx_mmr_load(int nasid, u64 offset);
#endif // __KERNEL__
#endif // _ASM_IA64_SN_TIO_TIOCX__
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