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Commit a512360f authored by Jon Hunter's avatar Jon Hunter Committed by Bjorn Helgaas
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PCI: tegra194: Fix MCFG quirk build regressions 

7f100744 ("PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata")
caused a few build regressions:

  - 7f100744 removed the Makefile rule for CONFIG_PCIE_TEGRA194, so
    pcie-tegra.c can no longer be built as a module.  Restore that rule.

  - 7f100744 added "#ifdef CONFIG_PCIE_TEGRA194" around the native
    driver, but that's only set when the driver is built-in (for a module,
    CONFIG_PCIE_TEGRA194_MODULE is defined).

    The ACPI quirk is completely independent of the rest of the native
    driver, so move the quirk to its own file and remove the #ifdef in the
    native driver.

  - 7f100744 added symbols that are always defined but used only when
    CONFIG_PCIEASPM, which causes warnings when CONFIG_PCIEASPM is not set:

      drivers/pci/controller/dwc/pcie-tegra194.c:259:18: warning: ‘event_cntr_data_offset’ defined but not used [-Wunused-const-variable=]
      drivers/pci/controller/dwc/pcie-tegra194.c:250:18: warning: ‘event_cntr_ctrl_offset’ defined but not used [-Wunused-const-variable=]
      drivers/pci/controller/dwc/pcie-tegra194.c:243:27: warning: ‘pcie_gen_freq’ defined but not used [-Wunused-const-variable=]

Fixes: 7f100744 ("PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata")
Link: https://lore.kernel.org/r/20210610064134.336781-1-jonathanh@nvidia.comSigned-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarThierry Reding <treding@nvidia.com>
parent 3bd6b827
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Showing with 128 additions and 121 deletions
drivers/pci/controller/dwc/Makefile
View file @ a512360f
......@@ -18,6 +18,7 @@ obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
obj-$(CONFIG_PCI_MESON) += pci-meson.o
obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
......@@ -38,6 +39,6 @@ ifdef CONFIG_ACPI
ifdef CONFIG_PCI_QUIRKS
obj-$(CONFIG_ARM64) += pcie-al.o
obj-$(CONFIG_ARM64) += pcie-hisi.o
obj-$(CONFIG_ARM64) += pcie-tegra194.o
obj-$(CONFIG_ARM64) += pcie-tegra194-acpi.o
endif
endif
drivers/pci/controller/dwc/pcie-tegra194-acpi.c 0 → 100644
View file @ a512360f
// SPDX-License-Identifier: GPL-2.0+
/*
* ACPI quirks for Tegra194 PCIe host controller
*
* Copyright (C) 2021 NVIDIA Corporation.
*
* Author: Vidya Sagar <vidyas@nvidia.com>
*/
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/pci-ecam.h>
#include "pcie-designware.h"
struct tegra194_pcie_ecam {
void __iomem *config_base;
void __iomem *iatu_base;
void __iomem *dbi_base;
};
static int tegra194_acpi_init(struct pci_config_window *cfg)
{
struct device *dev = cfg->parent;
struct tegra194_pcie_ecam *pcie_ecam;
pcie_ecam = devm_kzalloc(dev, sizeof(*pcie_ecam), GFP_KERNEL);
if (!pcie_ecam)
return -ENOMEM;
pcie_ecam->config_base = cfg->win;
pcie_ecam->iatu_base = cfg->win + SZ_256K;
pcie_ecam->dbi_base = cfg->win + SZ_512K;
cfg->priv = pcie_ecam;
return 0;
}
static void atu_reg_write(struct tegra194_pcie_ecam *pcie_ecam, int index,
u32 val, u32 reg)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
writel(val, pcie_ecam->iatu_base + offset + reg);
}
static void program_outbound_atu(struct tegra194_pcie_ecam *pcie_ecam,
int index, int type, u64 cpu_addr,
u64 pci_addr, u64 size)
{
atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr),
PCIE_ATU_LOWER_BASE);
atu_reg_write(pcie_ecam, index, upper_32_bits(cpu_addr),
PCIE_ATU_UPPER_BASE);
atu_reg_write(pcie_ecam, index, lower_32_bits(pci_addr),
PCIE_ATU_LOWER_TARGET);
atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr + size - 1),
PCIE_ATU_LIMIT);
atu_reg_write(pcie_ecam, index, upper_32_bits(pci_addr),
PCIE_ATU_UPPER_TARGET);
atu_reg_write(pcie_ecam, index, type, PCIE_ATU_CR1);
atu_reg_write(pcie_ecam, index, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static void __iomem *tegra194_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
{
struct pci_config_window *cfg = bus->sysdata;
struct tegra194_pcie_ecam *pcie_ecam = cfg->priv;
u32 busdev;
int type;
if (bus->number < cfg->busr.start || bus->number > cfg->busr.end)
return NULL;
if (bus->number == cfg->busr.start) {
if (PCI_SLOT(devfn) == 0)
return pcie_ecam->dbi_base + where;
else
return NULL;
}
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
if (bus->parent->number == cfg->busr.start) {
if (PCI_SLOT(devfn) == 0)
type = PCIE_ATU_TYPE_CFG0;
else
return NULL;
} else {
type = PCIE_ATU_TYPE_CFG1;
}
program_outbound_atu(pcie_ecam, 0, type, cfg->res.start, busdev,
SZ_256K);
return pcie_ecam->config_base + where;
}
const struct pci_ecam_ops tegra194_pcie_ops = {
.init = tegra194_acpi_init,
.pci_ops = {
.map_bus = tegra194_map_bus,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
}
};
drivers/pci/controller/dwc/pcie-tegra194.c
View file @ a512360f
......@@ -22,8 +22,6 @@
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/pci-ecam.h>
#include <linux/phy/phy.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
......@@ -247,24 +245,6 @@ static const unsigned int pcie_gen_freq[] = {
GEN4_CORE_CLK_FREQ
};
static const u32 event_cntr_ctrl_offset[] = {
0x1d8,
0x1a8,
0x1a8,
0x1a8,
0x1c4,
0x1d8
};
static const u32 event_cntr_data_offset[] = {
0x1dc,
0x1ac,
0x1ac,
0x1ac,
0x1c8,
0x1dc
};
struct tegra_pcie_dw {
struct device *dev;
struct resource *appl_res;
......@@ -313,104 +293,6 @@ struct tegra_pcie_dw_of_data {
enum dw_pcie_device_mode mode;
};
#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
struct tegra194_pcie_ecam {
void __iomem *config_base;
void __iomem *iatu_base;
void __iomem *dbi_base;
};
static int tegra194_acpi_init(struct pci_config_window *cfg)
{
struct device *dev = cfg->parent;
struct tegra194_pcie_ecam *pcie_ecam;
pcie_ecam = devm_kzalloc(dev, sizeof(*pcie_ecam), GFP_KERNEL);
if (!pcie_ecam)
return -ENOMEM;
pcie_ecam->config_base = cfg->win;
pcie_ecam->iatu_base = cfg->win + SZ_256K;
pcie_ecam->dbi_base = cfg->win + SZ_512K;
cfg->priv = pcie_ecam;
return 0;
}
static void atu_reg_write(struct tegra194_pcie_ecam *pcie_ecam, int index,
u32 val, u32 reg)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
writel(val, pcie_ecam->iatu_base + offset + reg);
}
static void program_outbound_atu(struct tegra194_pcie_ecam *pcie_ecam,
int index, int type, u64 cpu_addr,
u64 pci_addr, u64 size)
{
atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr),
PCIE_ATU_LOWER_BASE);
atu_reg_write(pcie_ecam, index, upper_32_bits(cpu_addr),
PCIE_ATU_UPPER_BASE);
atu_reg_write(pcie_ecam, index, lower_32_bits(pci_addr),
PCIE_ATU_LOWER_TARGET);
atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr + size - 1),
PCIE_ATU_LIMIT);
atu_reg_write(pcie_ecam, index, upper_32_bits(pci_addr),
PCIE_ATU_UPPER_TARGET);
atu_reg_write(pcie_ecam, index, type, PCIE_ATU_CR1);
atu_reg_write(pcie_ecam, index, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static void __iomem *tegra194_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
{
struct pci_config_window *cfg = bus->sysdata;
struct tegra194_pcie_ecam *pcie_ecam = cfg->priv;
u32 busdev;
int type;
if (bus->number < cfg->busr.start || bus->number > cfg->busr.end)
return NULL;
if (bus->number == cfg->busr.start) {
if (PCI_SLOT(devfn) == 0)
return pcie_ecam->dbi_base + where;
else
return NULL;
}
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
if (bus->parent->number == cfg->busr.start) {
if (PCI_SLOT(devfn) == 0)
type = PCIE_ATU_TYPE_CFG0;
else
return NULL;
} else {
type = PCIE_ATU_TYPE_CFG1;
}
program_outbound_atu(pcie_ecam, 0, type, cfg->res.start, busdev,
SZ_256K);
return pcie_ecam->config_base + where;
}
const struct pci_ecam_ops tegra194_pcie_ops = {
.init = tegra194_acpi_init,
.pci_ops = {
.map_bus = tegra194_map_bus,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
}
};
#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
#ifdef CONFIG_PCIE_TEGRA194
static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
{
return container_of(pci, struct tegra_pcie_dw, pci);
......@@ -694,6 +576,24 @@ static struct pci_ops tegra_pci_ops = {
};
#if defined(CONFIG_PCIEASPM)
static const u32 event_cntr_ctrl_offset[] = {
0x1d8,
0x1a8,
0x1a8,
0x1a8,
0x1c4,
0x1d8
};
static const u32 event_cntr_data_offset[] = {
0x1dc,
0x1ac,
0x1ac,
0x1ac,
0x1c8,
0x1dc
};
static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
{
u32 val;
......@@ -2411,5 +2311,3 @@ MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
MODULE_LICENSE("GPL v2");
#endif /* CONFIG_PCIE_TEGRA194 */
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