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Commit a51ed6cf authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'renesas-dt2-for-v4.12' of... 

Merge tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Second Round of Renesas ARM Based SoC DT Updates for v4.12

Corrections:
* Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
* Correct Z clock for r8a7792 SoC
* Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
* Correct ethernet clock parent on r7s72100 SoC
* Correct DU clock for r8a7794/silk board

Cleanups:
* Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs

Enhancements:
* Enable rtc r7s72100/genmai board
* Add Z2 clock for r8a7794 SoC
* Add DU clock for r8a7794 SoC
* Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
* Add reset control properties for r8a774[35] SoCs

* tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
  ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name
  ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name
  ARM: dts: genmai: Enable rtc and rtc_x1 clock
  ARM: dts: rskrza1: add rtc DT support
  ARM: dts: rskrza1: set rtc_x1 clock value
  ARM: dts: r7s72100: add rtc to device tree
  ARM: dts: r7s72100: add RTC_X clock inputs to device tree
  ARM: dts: r7s72100: add rtc clock to device tree
  ARM: dts: koelsch: Correct clock frequency of X2 DU clock input
  ARM: dts: r8a7794: Add Z2 clock
  ARM: dts: r8a7792: Correct Z clock
  ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks
  ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks
  ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks
  ARM: dts: r7s72100: fix ethernet clock parent
  ARM: dts: silk: Correct clock of DU1
  ARM: dts: alt: Correct clock of DU1
  ARM: dts: r8a7794: Correct clock of DU1
  ARM: dts: r8a7794: Add DU1 clock to device tree
  ARM: dts: r7s72100: add power-domains to sdhi
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 9ef0f50a eb77d726
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Showing with 151 additions and 19 deletions
arch/arm/boot/dts/r7s72100-genmai.dts
View file @ a51ed6cf
......@@ -44,6 +44,10 @@ &usb_x1_clk {
clock-frequency = <48000000>;
};
&rtc_x1_clk {
clock-frequency = <32768>;
};
&mtu2 {
status = "okay";
};
......@@ -59,6 +63,10 @@ eeprom@50 {
};
};
&rtc {
status = "okay";
};
&scif2 {
status = "okay";
};
......
arch/arm/boot/dts/r7s72100-rskrza1.dts
View file @ a51ed6cf
......@@ -43,6 +43,10 @@ &usb_x1_clk {
clock-frequency = <48000000>;
};
&rtc_x1_clk {
clock-frequency = <32768>;
};
&mtu2 {
status = "okay";
};
......@@ -69,6 +73,10 @@ &ostm1 {
status = "okay";
};
&rtc {
status = "okay";
};
&scif2 {
status = "okay";
};
arch/arm/boot/dts/r7s72100.dtsi
View file @ a51ed6cf
......@@ -51,6 +51,20 @@ usb_x1_clk: usb_x1 {
clock-frequency = <0>;
};
rtc_x1_clk: rtc_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board to 32678 */
clock-frequency = <0>;
};
rtc_x3_clk: rtc_x3 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board to 4000000 */
clock-frequency = <0>;
};
/* Fixed factor clocks */
b_clk: b {
#clock-cells = <0>;
......@@ -117,11 +131,20 @@ mstp5_clks: mstp5_clks@fcfe0428 {
clock-output-names = "ostm0", "ostm1";
};
mstp6_clks: mstp6_clks@fcfe042c {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe042c 4>;
clocks = <&p0_clk>;
clock-indices = <R7S72100_CLK_RTC>;
clock-output-names = "rtc";
};
mstp7_clks: mstp7_clks@fcfe0430 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0430 4>;
clocks = <&p0_clk>;
clocks = <&b_clk>;
clock-indices = <R7S72100_CLK_ETHER>;
clock-output-names = "ether";
};
......@@ -501,6 +524,7 @@ GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
clock-names = "core", "cd";
power-domains = <&cpg_clocks>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
......@@ -516,6 +540,7 @@ GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
clock-names = "core", "cd";
power-domains = <&cpg_clocks>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
......@@ -538,4 +563,18 @@ ostm1: timer@fcfec400 {
power-domains = <&cpg_clocks>;
status = "disabled";
};
rtc: rtc@fcff1000 {
compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
reg = <0xfcff1000 0x2e>;
interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
GIC_SPI 277 IRQ_TYPE_EDGE_RISING
GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm", "period", "carry";
clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
<&rtc_x3_clk>, <&extal_clk>;
clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
power-domains = <&cpg_clocks>;
status = "disabled";
};
};
arch/arm/boot/dts/r8a7743.dtsi
View file @ a51ed6cf
......@@ -62,6 +62,7 @@ gic: interrupt-controller@f1001000 {
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
irqc: interrupt-controller@e61c0000 {
......@@ -81,6 +82,7 @@ irqc: interrupt-controller@e61c0000 {
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
timer {
......@@ -102,6 +104,7 @@ cpg: clock-controller@e6150000 {
clock-names = "extal", "usb_extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
prr: chipid@ff000044 {
......@@ -148,6 +151,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <15>;
};
......@@ -180,6 +184,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <15>;
};
......@@ -195,6 +200,7 @@ scifa0: serial@e6c40000 {
<&dmac1 0x21>, <&dmac1 0x22>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
......@@ -209,6 +215,7 @@ scifa1: serial@e6c50000 {
<&dmac1 0x25>, <&dmac1 0x26>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
......@@ -223,6 +230,7 @@ scifa2: serial@e6c60000 {
<&dmac1 0x27>, <&dmac1 0x28>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
};
......@@ -237,6 +245,7 @@ scifa3: serial@e6c70000 {
<&dmac1 0x1b>, <&dmac1 0x1c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 1106>;
status = "disabled";
};
......@@ -251,6 +260,7 @@ scifa4: serial@e6c78000 {
<&dmac1 0x1f>, <&dmac1 0x20>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 1107>;
status = "disabled";
};
......@@ -265,6 +275,7 @@ scifa5: serial@e6c80000 {
<&dmac1 0x23>, <&dmac1 0x24>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 1108>;
status = "disabled";
};
......@@ -279,6 +290,7 @@ scifb0: serial@e6c20000 {
<&dmac1 0x3d>, <&dmac1 0x3e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
......@@ -293,6 +305,7 @@ scifb1: serial@e6c30000 {
<&dmac1 0x19>, <&dmac1 0x1a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
};
......@@ -307,6 +320,7 @@ scifb2: serial@e6ce0000 {
<&dmac1 0x1d>, <&dmac1 0x1e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 216>;
status = "disabled";
};
......@@ -322,6 +336,7 @@ scif0: serial@e6e60000 {
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 721>;
status = "disabled";
};
......@@ -337,6 +352,7 @@ scif1: serial@e6e68000 {
<&dmac1 0x2d>, <&dmac1 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 720>;
status = "disabled";
};
......@@ -352,6 +368,7 @@ scif2: serial@e6e58000 {
<&dmac1 0x2b>, <&dmac1 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 719>;
status = "disabled";
};
......@@ -367,6 +384,7 @@ scif3: serial@e6ea8000 {
<&dmac1 0x2f>, <&dmac1 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 718>;
status = "disabled";
};
......@@ -382,6 +400,7 @@ scif4: serial@e6ee0000 {
<&dmac1 0xfb>, <&dmac1 0xfc>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 715>;
status = "disabled";
};
......@@ -397,6 +416,7 @@ scif5: serial@e6ee8000 {
<&dmac1 0xfd>, <&dmac1 0xfe>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 714>;
status = "disabled";
};
......@@ -412,6 +432,7 @@ hscif0: serial@e62c0000 {
<&dmac1 0x39>, <&dmac1 0x3a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 717>;
status = "disabled";
};
......@@ -427,6 +448,7 @@ hscif1: serial@e62c8000 {
<&dmac1 0x4d>, <&dmac1 0x4e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
};
......@@ -442,6 +464,7 @@ hscif2: serial@e62d0000 {
<&dmac1 0x3b>, <&dmac1 0x3c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 713>;
status = "disabled";
};
......@@ -451,6 +474,7 @@ ether: ethernet@ee700000 {
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 813>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm/boot/dts/r8a7745.dtsi
View file @ a51ed6cf
......@@ -62,6 +62,7 @@ gic: interrupt-controller@f1001000 {
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
irqc: interrupt-controller@e61c0000 {
......@@ -81,6 +82,7 @@ irqc: interrupt-controller@e61c0000 {
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
timer {
......@@ -102,6 +104,7 @@ cpg: clock-controller@e6150000 {
clock-names = "extal", "usb_extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
prr: chipid@ff000044 {
......@@ -148,6 +151,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <15>;
};
......@@ -180,6 +184,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <15>;
};
......@@ -195,6 +200,7 @@ scifa0: serial@e6c40000 {
<&dmac1 0x21>, <&dmac1 0x22>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
......@@ -209,6 +215,7 @@ scifa1: serial@e6c50000 {
<&dmac1 0x25>, <&dmac1 0x26>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
......@@ -223,6 +230,7 @@ scifa2: serial@e6c60000 {
<&dmac1 0x27>, <&dmac1 0x28>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
};
......@@ -237,6 +245,7 @@ scifa3: serial@e6c70000 {
<&dmac1 0x1b>, <&dmac1 0x1c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 1106>;
status = "disabled";
};
......@@ -251,6 +260,7 @@ scifa4: serial@e6c78000 {
<&dmac1 0x1f>, <&dmac1 0x20>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 1107>;
status = "disabled";
};
......@@ -265,6 +275,7 @@ scifa5: serial@e6c80000 {
<&dmac1 0x23>, <&dmac1 0x24>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 1108>;
status = "disabled";
};
......@@ -279,6 +290,7 @@ scifb0: serial@e6c20000 {
<&dmac1 0x3d>, <&dmac1 0x3e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
......@@ -293,6 +305,7 @@ scifb1: serial@e6c30000 {
<&dmac1 0x19>, <&dmac1 0x1a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
};
......@@ -307,6 +320,7 @@ scifb2: serial@e6ce0000 {
<&dmac1 0x1d>, <&dmac1 0x1e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 216>;
status = "disabled";
};
......@@ -322,6 +336,7 @@ scif0: serial@e6e60000 {
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 721>;
status = "disabled";
};
......@@ -337,6 +352,7 @@ scif1: serial@e6e68000 {
<&dmac1 0x2d>, <&dmac1 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 720>;
status = "disabled";
};
......@@ -352,6 +368,7 @@ scif2: serial@e6e58000 {
<&dmac1 0x2b>, <&dmac1 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 719>;
status = "disabled";
};
......@@ -367,6 +384,7 @@ scif3: serial@e6ea8000 {
<&dmac1 0x2f>, <&dmac1 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 718>;
status = "disabled";
};
......@@ -382,6 +400,7 @@ scif4: serial@e6ee0000 {
<&dmac1 0xfb>, <&dmac1 0xfc>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 715>;
status = "disabled";
};
......@@ -397,6 +416,7 @@ scif5: serial@e6ee8000 {
<&dmac1 0xfd>, <&dmac1 0xfe>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 714>;
status = "disabled";
};
......@@ -412,6 +432,7 @@ hscif0: serial@e62c0000 {
<&dmac1 0x39>, <&dmac1 0x3a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 717>;
status = "disabled";
};
......@@ -427,6 +448,7 @@ hscif1: serial@e62c8000 {
<&dmac1 0x4d>, <&dmac1 0x4e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
};
......@@ -442,6 +464,7 @@ hscif2: serial@e62d0000 {
<&dmac1 0x3b>, <&dmac1 0x3c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 713>;
status = "disabled";
};
......@@ -451,6 +474,7 @@ ether: ethernet@ee700000 {
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 813>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm/boot/dts/r8a7790.dtsi
View file @ a51ed6cf
......@@ -1101,7 +1101,7 @@ usb_extal_clk: usb_extal {
};
/* External CAN clock */
can_clk: can_clk {
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
......@@ -1443,8 +1443,11 @@ mstp10_clks: mstp10_clks@e6150998 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
clocks = <&p_clk>,
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&p_clk>,
<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
......
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ a51ed6cf
......@@ -292,7 +292,7 @@ hdmi_con_out: endpoint {
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
clock-frequency = <74250000>;
};
x13_clk: x13-clock {
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ a51ed6cf
......@@ -1126,7 +1126,7 @@ usb_extal_clk: usb_extal {
};
/* External CAN clock */
can_clk: can_clk {
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
......@@ -1447,8 +1447,11 @@ mstp10_clks: mstp10_clks@e6150998 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
clocks = <&p_clk>,
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&p_clk>,
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
......
arch/arm/boot/dts/r8a7792.dtsi
View file @ a51ed6cf
......@@ -46,7 +46,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1000000000>;
clocks = <&cpg_clocks R8A7792_CLK_Z>;
clocks = <&z_clk>;
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
};
......@@ -766,7 +766,7 @@ cpg_clocks: cpg_clocks@e6150000 {
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "z";
"lb", "qspi";
#power-domain-cells = <0>;
};
......@@ -778,6 +778,13 @@ pll1_div2_clk: pll1_div2 {
clock-div = <2>;
clock-mult = <1>;
};
z_clk: z {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL0>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
zx_clk: zx {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
......
arch/arm/boot/dts/r8a7793.dtsi
View file @ a51ed6cf
......@@ -1269,8 +1269,11 @@ mstp10_clks: mstp10_clks@e6150998 {
compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
clocks = <&p_clk>,
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&p_clk>,
<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
......
arch/arm/boot/dts/r8a7794-alt.dts
View file @ a51ed6cf
......@@ -168,7 +168,7 @@ &du {
status = "okay";
clocks = <&mstp7_clks R8A7794_CLK_DU0>,
<&mstp7_clks R8A7794_CLK_DU0>,
<&mstp7_clks R8A7794_CLK_DU1>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
......
arch/arm/boot/dts/r8a7794-silk.dts
View file @ a51ed6cf
......@@ -424,7 +424,7 @@ &du {
status = "okay";
clocks = <&mstp7_clks R8A7794_CLK_DU0>,
<&mstp7_clks R8A7794_CLK_DU0>,
<&mstp7_clks R8A7794_CLK_DU1>,
<&x2_clk>, <&x3_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
......
arch/arm/boot/dts/r8a7794.dtsi
View file @ a51ed6cf
......@@ -43,6 +43,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
clocks = <&z2_clk>;
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
next-level-cache = <&L2_CA7>;
};
......@@ -925,7 +926,7 @@ du: display@feb00000 {
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7794_CLK_DU0>,
<&mstp7_clks R8A7794_CLK_DU0>;
<&mstp7_clks R8A7794_CLK_DU1>;
clock-names = "du.0", "du.1";
status = "disabled";
......@@ -1064,6 +1065,13 @@ pll1_div2_clk: pll1_div2 {
clock-div = <2>;
clock-mult = <1>;
};
z2_clk: z2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
......@@ -1270,19 +1278,21 @@ mstp7_clks: mstp7_clks@e615014c {
clocks = <&mp_clk>, <&hp_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&zx_clk>;
<&zx_clk>, <&zx_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
R8A7794_CLK_SCIF0
R8A7794_CLK_DU1 R8A7794_CLK_DU0
>;
clock-output-names =
"ehci", "hsusb",
"hscif2", "scif5", "scif4", "hscif1", "hscif0",
"scif3", "scif2", "scif1", "scif0", "du0";
"scif3", "scif2", "scif1", "scif0",
"du1", "du0";
};
mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
......
include/dt-bindings/clock/r7s72100-clock.h
View file @ a51ed6cf
......@@ -29,6 +29,9 @@
#define R7S72100_CLK_OSTM0 1
#define R7S72100_CLK_OSTM1 0
/* MSTP6 */
#define R7S72100_CLK_RTC 0
/* MSTP7 */
#define R7S72100_CLK_ETHER 4
......
include/dt-bindings/clock/r8a7792-clock.h
View file @ a51ed6cf
......@@ -17,7 +17,6 @@
#define R8A7792_CLK_PLL3 3
#define R8A7792_CLK_LB 4
#define R8A7792_CLK_QSPI 5
#define R8A7792_CLK_Z 6
/* MSTP0 */
#define R8A7792_CLK_MSIOF0 0
......
include/dt-bindings/clock/r8a7794-clock.h
View file @ a51ed6cf
......@@ -82,6 +82,7 @@
#define R8A7794_CLK_SCIF2 19
#define R8A7794_CLK_SCIF1 20
#define R8A7794_CLK_SCIF0 21
#define R8A7794_CLK_DU1 23
#define R8A7794_CLK_DU0 24
/* MSTP8 */
......
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