Commit a7384598 authored by Sudeep Holla's avatar Sudeep Holla

arm64: dts: add clock support for all the cpus

This patch adds the CPU clocks so that the CPU DVFS can be enabled.
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
Acked-by: default avatarLiviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
parent 050c69e8
...@@ -66,6 +66,7 @@ A57_0: cpu@0 { ...@@ -66,6 +66,7 @@ A57_0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A57_L2>; next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
}; };
A57_1: cpu@1 { A57_1: cpu@1 {
...@@ -74,6 +75,7 @@ A57_1: cpu@1 { ...@@ -74,6 +75,7 @@ A57_1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A57_L2>; next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
}; };
A53_0: cpu@100 { A53_0: cpu@100 {
...@@ -82,6 +84,7 @@ A53_0: cpu@100 { ...@@ -82,6 +84,7 @@ A53_0: cpu@100 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
}; };
A53_1: cpu@101 { A53_1: cpu@101 {
...@@ -90,6 +93,7 @@ A53_1: cpu@101 { ...@@ -90,6 +93,7 @@ A53_1: cpu@101 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
}; };
A53_2: cpu@102 { A53_2: cpu@102 {
...@@ -98,6 +102,7 @@ A53_2: cpu@102 { ...@@ -98,6 +102,7 @@ A53_2: cpu@102 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
}; };
A53_3: cpu@103 { A53_3: cpu@103 {
...@@ -106,6 +111,7 @@ A53_3: cpu@103 { ...@@ -106,6 +111,7 @@ A53_3: cpu@103 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
}; };
A57_L2: l2-cache0 { A57_L2: l2-cache0 {
......
...@@ -66,6 +66,7 @@ A57_0: cpu@0 { ...@@ -66,6 +66,7 @@ A57_0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A57_L2>; next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
}; };
A57_1: cpu@1 { A57_1: cpu@1 {
...@@ -74,6 +75,7 @@ A57_1: cpu@1 { ...@@ -74,6 +75,7 @@ A57_1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A57_L2>; next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
}; };
A53_0: cpu@100 { A53_0: cpu@100 {
...@@ -82,6 +84,7 @@ A53_0: cpu@100 { ...@@ -82,6 +84,7 @@ A53_0: cpu@100 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
}; };
A53_1: cpu@101 { A53_1: cpu@101 {
...@@ -90,6 +93,7 @@ A53_1: cpu@101 { ...@@ -90,6 +93,7 @@ A53_1: cpu@101 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
}; };
A53_2: cpu@102 { A53_2: cpu@102 {
...@@ -98,6 +102,7 @@ A53_2: cpu@102 { ...@@ -98,6 +102,7 @@ A53_2: cpu@102 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
}; };
A53_3: cpu@103 { A53_3: cpu@103 {
...@@ -106,6 +111,7 @@ A53_3: cpu@103 { ...@@ -106,6 +111,7 @@ A53_3: cpu@103 {
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&A53_L2>; next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
}; };
A57_L2: l2-cache0 { A57_L2: l2-cache0 {
......
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