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Commit a7726350 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC cleanup from Olof Johansson:
 "Here is a collection of cleanup patches.  Among the pieces that stand
  out are:

   - The deletion of h720x platforms
   - Split of at91 non-dt platforms to their own Kconfig file to keep
     them separate
   - General cleanups and refactoring of i.MX and MXS platforms
   - Some restructuring of clock tables for OMAP
   - Convertion of PMC driver for Tegra to dt-only
   - Some renames of sunxi -> sun4i (Allwinner A10)
   - ... plus a bunch of other stuff that I haven't mentioned"

* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits)
  ARM: i.MX: remove unused ARCH_* configs
  ARM i.MX53: remove platform ahci support
  ARM: sunxi: Rework the restart code
  irqchip: sunxi: Rename sunxi to sun4i
  irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro
  clocksource: sunxi: Rename sunxi to sun4i
  clocksource: sunxi: make use of CLKSRC_OF
  clocksource: sunxi: Cleanup the timer code
  ARM: at91: remove trailing semicolon from macros
  ARM: at91/setup: fix trivial typos
  ARM: EXYNOS: remove "config EXYNOS_DEV_DRM"
  ARM: EXYNOS: change the name of USB ohci header
  ARM: SAMSUNG: Remove unnecessary code for dma
  ARM: S3C24XX: Remove unused GPIO drive strength register definitions
  ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method
  ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2412
  ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2410
  ARM: S3C24XX: Removed unneeded dependency on ARCH_S3C24XX for boards
  ARM: SAMSUNG: Fix typo "CONFIG_SAMSUNG_DEV_RTC"
  ARM: S5P64X0: Fix typo "CONFIG_S5P64X0_SETUP_SDHCI"
  ...
parents 4d26aa30 afcf7924
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Showing with 2919 additions and 6386 deletions
Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt → Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
View file @ a7726350
......@@ -2,7 +2,7 @@ Allwinner Sunxi Interrupt Controller
Required properties:
- compatible : should be "allwinner,sunxi-ic"
- compatible : should be "allwinner,sun4i-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
......@@ -97,7 +97,7 @@ The interrupt sources are as follows:
Example:
intc: interrupt-controller {
compatible = "allwinner,sunxi-ic";
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <2>;
......
Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt → Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
View file @ a7726350
......@@ -2,7 +2,7 @@ Allwinner A1X SoCs Timer Controller
Required properties:
- compatible : should be "allwinner,sunxi-timer"
- compatible : should be "allwinner,sun4i-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupt of the first timer
- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
......@@ -10,7 +10,7 @@ Required properties:
Example:
timer {
compatible = "allwinner,sunxi-timer";
compatible = "allwinner,sun4i-timer";
reg = <0x01c20c00 0x400>;
interrupts = <22>;
clocks = <&osc>;
......
Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt → Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt
View file @ a7726350
Allwinner sunXi Watchdog timer
Allwinner sun4i Watchdog timer
Required properties:
- compatible : should be "allwinner,sunxi-wdt"
- compatible : should be "allwinner,sun4i-wdt"
- reg : Specifies base physical address and size of the registers.
Example:
wdt: watchdog@01c20c90 {
compatible = "allwinner,sunxi-wdt";
compatible = "allwinner,sun4i-wdt";
reg = <0x01c20c90 0x10>;
};
arch/arm/Kconfig
View file @ a7726350
......@@ -411,6 +411,7 @@ config ARCH_GEMINI
bool "Cortina Systems Gemini"
select ARCH_REQUIRE_GPIOLIB
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_GPIO_H
select CPU_FA526
help
Support for the Cortina Systems Gemini family SoCs
......@@ -474,12 +475,14 @@ config ARCH_MXS
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK_PREPARE
select MULTI_IRQ_HANDLER
select PINCTRL
select SPARSE_IRQ
select STMP_DEVICE
select USE_OF
help
Support for Freescale MXS-based family of processors
......@@ -493,14 +496,6 @@ config ARCH_NETX
help
This enables support for systems based on the Hilscher NetX Soc
config ARCH_H720X
bool "Hynix HMS720x-based"
select ARCH_USES_GETTIMEOFFSET
select CPU_ARM720T
select ISA_DMA_API
help
This enables support for systems based on the Hynix HMS720x
config ARCH_IOP13XX
bool "IOP13xx-based"
depends on MMU
......@@ -1054,8 +1049,6 @@ source "arch/arm/mach-footbridge/Kconfig"
source "arch/arm/mach-gemini/Kconfig"
source "arch/arm/mach-h720x/Kconfig"
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
......@@ -1176,7 +1169,6 @@ config PLAT_VERSATILE
config ARM_TIMER_SP804
bool
select CLKSRC_MMIO
select HAVE_SCHED_CLOCK
source arch/arm/mm/Kconfig
......@@ -1606,6 +1598,7 @@ config HAVE_ARM_ARCH_TIMER
config HAVE_ARM_TWD
bool
depends on SMP
select CLKSRC_OF if OF
help
This options enables support for the ARM timer and watchdog unit
......@@ -2165,13 +2158,6 @@ menu "CPU Power Management"
if ARCH_HAS_CPUFREQ
source "drivers/cpufreq/Kconfig"
config CPU_FREQ_IMX
tristate "CPUfreq driver for i.MX CPUs"
depends on ARCH_MXC && CPU_FREQ
select CPU_FREQ_TABLE
help
This enables the CPUfreq driver for i.MX CPUs.
config CPU_FREQ_S3C
bool
help
......
arch/arm/Makefile
View file @ a7726350
......@@ -147,7 +147,6 @@ machine-$(CONFIG_ARCH_DOVE) += dove
machine-$(CONFIG_ARCH_EBSA110) += ebsa110
machine-$(CONFIG_ARCH_EP93XX) += ep93xx
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_H720X) += h720x
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
......
arch/arm/boot/dts/imx23.dtsi
View file @ a7726350
......@@ -295,6 +295,7 @@ spi2_pins_a: spi2@0 {
};
digctl@8001c000 {
compatible = "fsl,imx23-digctl";
reg = <0x8001c000 2000>;
status = "disabled";
};
......@@ -321,6 +322,7 @@ pxp@8002a000 {
};
ocotp@8002c000 {
compatible = "fsl,ocotp";
reg = <0x8002c000 0x2000>;
status = "disabled";
};
......@@ -360,7 +362,7 @@ apbx@80040000 {
ranges;
clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl";
compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
......@@ -426,6 +428,7 @@ timrot@80068000 {
compatible = "fsl,imx23-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
interrupts = <28 29 30 31>;
clocks = <&clks 28>;
};
auart0: serial@8006c000 {
......
arch/arm/boot/dts/imx28.dtsi
View file @ a7726350
......@@ -647,6 +647,7 @@ usbphy1_pins_a: usbphy1@0 {
};
digctl@8001c000 {
compatible = "fsl,imx28-digctl";
reg = <0x8001c000 0x2000>;
interrupts = <89>;
status = "disabled";
......@@ -676,6 +677,7 @@ pxp@8002a000 {
};
ocotp@8002c000 {
compatible = "fsl,ocotp";
reg = <0x8002c000 0x2000>;
status = "disabled";
};
......@@ -755,7 +757,7 @@ apbx@80040000 {
ranges;
clks: clkctrl@80040000 {
compatible = "fsl,imx28-clkctrl";
compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
......@@ -838,6 +840,7 @@ timrot@80068000 {
compatible = "fsl,imx28-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
interrupts = <48 49 50 51>;
clocks = <&clks 26>;
};
auart0: serial@8006a000 {
......
arch/arm/boot/dts/tegra114.dtsi
View file @ a7726350
......@@ -99,7 +99,7 @@ rtc {
};
pmc {
compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
};
......
arch/arm/boot/dts/tegra20.dtsi
View file @ a7726350
......@@ -145,6 +145,7 @@ timer@60005000 {
0 1 0x04
0 41 0x04
0 42 0x04>;
clocks = <&tegra_car 5>;
};
tegra_car: clock {
......@@ -304,6 +305,7 @@ rtc {
compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>;
clocks = <&tegra_car 4>;
};
i2c@7000c000 {
......
arch/arm/boot/dts/tegra30.dtsi
View file @ a7726350
......@@ -148,6 +148,7 @@ timer@60005000 {
0 42 0x04
0 121 0x04
0 122 0x04>;
clocks = <&tegra_car 5>;
};
tegra_car: clock {
......@@ -291,6 +292,7 @@ rtc {
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>;
clocks = <&tegra_car 4>;
};
i2c@7000c000 {
......@@ -423,7 +425,7 @@ kbc {
};
pmc {
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
compatible = "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
};
......
arch/arm/configs/at91_dt_defconfig
View file @ a7726350
......@@ -20,7 +20,7 @@ CONFIG_SOC_AT91SAM9263=y
CONFIG_SOC_AT91SAM9G45=y
CONFIG_SOC_AT91SAM9X5=y
CONFIG_SOC_AT91SAM9N12=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_MACH_AT91SAM9_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_TIMER_HZ=128
CONFIG_AEABI=y
......
arch/arm/configs/at91sam9260_defconfig
View file @ a7726350
......@@ -22,7 +22,7 @@ CONFIG_MACH_QIL_A9260=y
CONFIG_MACH_CPU9260=y
CONFIG_MACH_FLEXIBITY=y
CONFIG_MACH_SNAPPER_9260=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_MACH_AT91SAM9_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
......
arch/arm/configs/at91sam9g20_defconfig
View file @ a7726350
......@@ -22,7 +22,7 @@ CONFIG_MACH_PCONTROL_G20=y
CONFIG_MACH_GSIA18S=y
CONFIG_MACH_USB_A9G20=y
CONFIG_MACH_SNAPPER_9260=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_MACH_AT91SAM9_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_AEABI=y
......
arch/arm/configs/at91sam9g45_defconfig
View file @ a7726350
......@@ -18,7 +18,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91SAM9G45=y
CONFIG_MACH_AT91SAM9M10G45EK=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_MACH_AT91SAM9_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_SLOW_CLOCK=y
CONFIG_AEABI=y
......
arch/arm/configs/h7201_defconfig deleted 100644 → 0
View file @ 4d26aa30
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_ARCH_H720X=y
CONFIG_ARCH_H7201=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_MTD=y
CONFIG_MTD_DEBUG=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_SOUND=m
CONFIG_EXT2_FS=y
CONFIG_JFFS2_FS=y
CONFIG_DEBUG_USER=y
arch/arm/configs/h7202_defconfig deleted 100644 → 0
View file @ 4d26aa30
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_MODULES=y
CONFIG_ARCH_H720X=y
CONFIG_ARCH_H7202=y
# CONFIG_ARM_THUMB is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,19200"
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_H720X=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB_GADGET=m
CONFIG_USB_ZERO=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_EXT2_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_USER=y
arch/arm/include/asm/irq.h
View file @ a7726350
......@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);
void handle_IRQ(unsigned int, struct pt_regs *);
void init_IRQ(void);
#ifdef CONFIG_MULTI_IRQ_HANDLER
extern void (*handle_arch_irq)(struct pt_regs *);
extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
#endif
#endif
#endif
......
arch/arm/include/asm/mach/irq.h
View file @ a7726350
......@@ -20,11 +20,6 @@ struct seq_file;
extern void init_FIQ(int);
extern int show_fiq_list(struct seq_file *, int);
#ifdef CONFIG_MULTI_IRQ_HANDLER
extern void (*handle_arch_irq)(struct pt_regs *);
extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
#endif
/*
* This is for easy migration, but should be changed in the source
*/
......@@ -35,35 +30,4 @@ do { \
raw_spin_unlock(&desc->lock); \
} while(0)
#ifndef __ASSEMBLY__
/*
* Entry/exit functions for chained handlers where the primary IRQ chip
* may implement either fasteoi or level-trigger flow control.
*/
static inline void chained_irq_enter(struct irq_chip *chip,
struct irq_desc *desc)
{
/* FastEOI controllers require no action on entry. */
if (chip->irq_eoi)
return;
if (chip->irq_mask_ack) {
chip->irq_mask_ack(&desc->irq_data);
} else {
chip->irq_mask(&desc->irq_data);
if (chip->irq_ack)
chip->irq_ack(&desc->irq_data);
}
}
static inline void chained_irq_exit(struct irq_chip *chip,
struct irq_desc *desc)
{
if (chip->irq_eoi)
chip->irq_eoi(&desc->irq_data);
else
chip->irq_unmask(&desc->irq_data);
}
#endif
#endif
arch/arm/include/asm/smp_twd.h
View file @ a7726350
......@@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = { \
int twd_local_timer_register(struct twd_local_timer *);
#ifdef CONFIG_HAVE_ARM_TWD
void twd_local_timer_of_register(void);
#else
static inline void twd_local_timer_of_register(void)
{
}
#endif
#endif
arch/arm/kernel/irq.c
View file @ a7726350
......@@ -26,6 +26,7 @@
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/random.h>
#include <linux/smp.h>
#include <linux/init.h>
......@@ -114,7 +115,10 @@ EXPORT_SYMBOL_GPL(set_irq_flags);
void __init init_IRQ(void)
{
machine_desc->init_irq();
if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
irqchip_init();
else
machine_desc->init_irq();
}
#ifdef CONFIG_MULTI_IRQ_HANDLER
......
arch/arm/kernel/smp_twd.c
View file @ a7726350
......@@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
}
#ifdef CONFIG_OF
const static struct of_device_id twd_of_match[] __initconst = {
{ .compatible = "arm,cortex-a9-twd-timer", },
{ .compatible = "arm,cortex-a5-twd-timer", },
{ .compatible = "arm,arm11mp-twd-timer", },
{ },
};
void __init twd_local_timer_of_register(void)
static void __init twd_local_timer_of_register(struct device_node *np)
{
struct device_node *np;
int err;
if (!is_smp() || !setup_max_cpus)
return;
np = of_find_matching_node(NULL, twd_of_match);
if (!np)
return;
twd_ppi = irq_of_parse_and_map(np, 0);
if (!twd_ppi) {
err = -EINVAL;
......@@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void)
out:
WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
}
CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
#endif
arch/arm/mach-at91/Kconfig
View file @ a7726350
This diff is collapsed.
arch/arm/mach-at91/Kconfig.non_dt 0 → 100644
View file @ a7726350
This diff is collapsed.
arch/arm/mach-at91/Makefile
View file @ a7726350
......@@ -87,8 +87,8 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
# AT91SAM board with device-tree
obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o
obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
# AT91X40 board-specific support
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
......
arch/arm/mach-at91/at91_rstc.h
View file @ a7726350
......@@ -23,7 +23,7 @@ extern void __iomem *at91_rstc_base;
__raw_readl(at91_rstc_base + field)
#define at91_rstc_write(field, value) \
__raw_writel(value, at91_rstc_base + field);
__raw_writel(value, at91_rstc_base + field)
#else
.extern at91_rstc_base
#endif
......
arch/arm/mach-at91/at91_shdwc.h
View file @ a7726350
......@@ -23,7 +23,7 @@ extern void __iomem *at91_shdwc_base;
__raw_readl(at91_shdwc_base + field)
#define at91_shdwc_write(field, value) \
__raw_writel(value, at91_shdwc_base + field);
__raw_writel(value, at91_shdwc_base + field)
#endif
#define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
......
arch/arm/mach-at91/at91x40_time.c
View file @ a7726350
......@@ -33,7 +33,7 @@
__raw_readl(AT91_IO_P2V(AT91_TC) + field)
#define at91_tc_write(field, value) \
__raw_writel(value, AT91_IO_P2V(AT91_TC) + field);
__raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
/*
* 3 counter/timer units present.
......
arch/arm/mach-at91/gpio.c
View file @ a7726350
......@@ -22,10 +22,9 @@
#include <linux/module.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of_address.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/at91_pio.h>
......
arch/arm/mach-at91/include/mach/at91_dbgu.h
View file @ a7726350
......@@ -16,9 +16,6 @@
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
#define dbgu_readl(dbgu, field) \
__raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
#if !defined(CONFIG_ARCH_AT91X40)
#define AT91_DBGU_CR (0x00) /* Control Register */
#define AT91_DBGU_MR (0x04) /* Mode Register */
......
arch/arm/mach-at91/include/mach/at91_matrix.h
View file @ a7726350
......@@ -14,7 +14,7 @@ extern void __iomem *at91_matrix_base;
__raw_readl(at91_matrix_base + field)
#define at91_matrix_write(field, value) \
__raw_writel(value, at91_matrix_base + field);
__raw_writel(value, at91_matrix_base + field)
#else
.extern at91_matrix_base
......
arch/arm/mach-at91/include/mach/at91_st.h
View file @ a7726350
......@@ -23,7 +23,7 @@ extern void __iomem *at91_st_base;
__raw_readl(at91_st_base + field)
#define at91_st_write(field, value) \
__raw_writel(value, at91_st_base + field);
__raw_writel(value, at91_st_base + field)
#else
.extern at91_st_base
#endif
......
arch/arm/mach-at91/setup.c
View file @ a7726350
......@@ -333,7 +333,7 @@ static void at91_dt_rstc(void)
of_id = of_match_node(rstc_ids, np);
if (!of_id)
panic("AT91: rtsc no restart function availlable\n");
panic("AT91: rtsc no restart function available\n");
arm_pm_restart = of_id->data;
......@@ -353,7 +353,7 @@ static void at91_dt_ramc(void)
np = of_find_matching_node(NULL, ramc_ids);
if (!np)
panic("unable to find compatible ram conroller node in dtb\n");
panic("unable to find compatible ram controller node in dtb\n");
at91_ramc_base[0] = of_iomap(np, 0);
if (!at91_ramc_base[0])
......@@ -403,7 +403,7 @@ static void at91_dt_shdwc(void)
np = of_find_matching_node(NULL, shdwc_ids);
if (!np) {
pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
return;
}
......@@ -419,7 +419,7 @@ static void at91_dt_shdwc(void)
if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
if (reg > AT91_SHDW_CPTWK0_MAX) {
pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
reg = AT91_SHDW_CPTWK0_MAX;
}
......
arch/arm/mach-exynos/Kconfig
View file @ a7726350
......@@ -97,11 +97,6 @@ config EXYNOS4_DEV_AHCI
help
Compile in platform device definitions for AHCI
config EXYNOS_DEV_DRM
bool
help
Compile in platform device definitions for core DRM device
config EXYNOS4_SETUP_FIMD0
bool
help
......@@ -201,7 +196,6 @@ config MACH_SMDKV310
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
select EXYNOS_DEV_DRM
select EXYNOS_DEV_SYSMMU
select S3C24XX_PWM
select S3C_DEV_HSMMC
......@@ -255,9 +249,7 @@ config MACH_UNIVERSAL_C210
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
select EXYNOS_DEV_DRM
select EXYNOS_DEV_SYSMMU
select HAVE_SCHED_CLOCK
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
......@@ -296,7 +288,6 @@ config MACH_NURI
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
select EXYNOS_DEV_DRM
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
......@@ -332,7 +323,6 @@ config MACH_ORIGEN
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
select EXYNOS_DEV_DRM
select EXYNOS_DEV_SYSMMU
select S3C24XX_PWM
select S3C_DEV_HSMMC
......@@ -368,7 +358,6 @@ config MACH_SMDK4212
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select EXYNOS_DEV_DMA
select EXYNOS_DEV_DRM
select EXYNOS_DEV_SYSMMU
select S3C24XX_PWM
select S3C_DEV_HSMMC2
......@@ -409,7 +398,7 @@ config MACH_EXYNOS4_DT
depends on ARCH_EXYNOS4
select ARM_AMBA
select CPU_EXYNOS4210
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
select PINCTRL
select PINCTRL_EXYNOS
select USE_OF
......
arch/arm/mach-exynos/common.c
View file @ a7726350
......@@ -23,9 +23,9 @@
#include <linux/of_irq.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/chained_irq.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
......
arch/arm/mach-exynos/dev-ohci.c
View file @ a7726350
......@@ -12,7 +12,7 @@
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/platform_data/usb-exynos.h>
#include <linux/platform_data/usb-ohci-exynos.h>
#include <mach/irqs.h>
#include <mach/map.h>
......
arch/arm/mach-exynos/mach-origen.c
View file @ a7726350
......@@ -26,7 +26,7 @@
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <linux/platform_data/usb-ehci-s5p.h>
#include <linux/platform_data/usb-exynos.h>
#include <linux/platform_data/usb-ohci-exynos.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
......
arch/arm/mach-exynos/mach-smdkv310.c
View file @ a7726350
......@@ -23,7 +23,7 @@
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <linux/platform_data/usb-ehci-s5p.h>
#include <linux/platform_data/usb-exynos.h>
#include <linux/platform_data/usb-ohci-exynos.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
......
arch/arm/mach-exynos/platsmp.c
View file @ a7726350
......@@ -20,7 +20,6 @@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
......@@ -75,13 +74,6 @@ static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos_secondary_init(unsigned int cpu)
{
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
......
arch/arm/mach-gemini/Makefile
View file @ a7726350
......@@ -4,7 +4,7 @@
# Object file lists.
obj-y := irq.o mm.o time.o devices.o gpio.o idle.o
obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
# Board-specific support
obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
......
arch/arm/mach-gemini/board-nas4220b.c
View file @ a7726350
......@@ -103,4 +103,5 @@ MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
.init_irq = gemini_init_irq,
.init_time = gemini_timer_init,
.init_machine = ib4220b_init,
.restart = gemini_restart,
MACHINE_END
arch/arm/mach-gemini/board-rut1xx.c
View file @ a7726350
......@@ -14,6 +14,7 @@
#include <linux/leds.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -87,4 +88,5 @@ MACHINE_START(RUT100, "Teltonika RUT100")
.init_irq = gemini_init_irq,
.init_time = gemini_timer_init,
.init_machine = rut1xx_init,
.restart = gemini_restart,
MACHINE_END
arch/arm/mach-gemini/board-wbd111.c
View file @ a7726350
......@@ -130,4 +130,5 @@ MACHINE_START(WBD111, "Wiliboard WBD-111")
.init_irq = gemini_init_irq,
.init_time = gemini_timer_init,
.init_machine = wbd111_init,
.restart = gemini_restart,
MACHINE_END
arch/arm/mach-gemini/board-wbd222.c
View file @ a7726350
......@@ -130,4 +130,5 @@ MACHINE_START(WBD222, "Wiliboard WBD-222")
.init_irq = gemini_init_irq,
.init_time = gemini_timer_init,
.init_machine = wbd222_init,
.restart = gemini_restart,
MACHINE_END
arch/arm/mach-gemini/common.h
View file @ a7726350
......@@ -26,4 +26,6 @@ extern int platform_register_pflash(unsigned int size,
struct mtd_partition *parts,
unsigned int nr_parts);
extern void gemini_restart(char mode, const char *cmd);
#endif /* __GEMINI_COMMON_H__ */
arch/arm/mach-gemini/gpio.c
View file @ a7726350
......@@ -21,6 +21,7 @@
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/gpio.h>
#define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x))
......@@ -44,7 +45,7 @@
#define GPIO_PORT_NUM 3
static void _set_gpio_irqenable(unsigned int base, unsigned int index,
static void _set_gpio_irqenable(void __iomem *base, unsigned int index,
int enable)
{
unsigned int reg;
......@@ -57,7 +58,7 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index,
static void gpio_ack_irq(struct irq_data *d)
{
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int base = GPIO_BASE(gpio / 32);
void __iomem *base = GPIO_BASE(gpio / 32);
__raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
}
......@@ -65,7 +66,7 @@ static void gpio_ack_irq(struct irq_data *d)
static void gpio_mask_irq(struct irq_data *d)
{
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int base = GPIO_BASE(gpio / 32);
void __iomem *base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 0);
}
......@@ -73,7 +74,7 @@ static void gpio_mask_irq(struct irq_data *d)
static void gpio_unmask_irq(struct irq_data *d)
{
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int base = GPIO_BASE(gpio / 32);
void __iomem *base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 1);
}
......@@ -82,7 +83,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int gpio_mask = 1 << (gpio % 32);
unsigned int base = GPIO_BASE(gpio / 32);
void __iomem *base = GPIO_BASE(gpio / 32);
unsigned int reg_both, reg_level, reg_type;
reg_type = __raw_readl(base + GPIO_INT_TYPE);
......@@ -120,7 +121,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
__raw_writel(reg_level, base + GPIO_INT_LEVEL);
__raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
gpio_ack_irq(d->irq);
gpio_ack_irq(d);
return 0;
}
......@@ -153,7 +154,7 @@ static struct irq_chip gpio_irq_chip = {
static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
int dir)
{
unsigned int base = GPIO_BASE(offset / 32);
void __iomem *base = GPIO_BASE(offset / 32);
unsigned int reg;
reg = __raw_readl(base + GPIO_DIR);
......@@ -166,7 +167,7 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
unsigned int base = GPIO_BASE(offset / 32);
void __iomem *base = GPIO_BASE(offset / 32);
if (value)
__raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
......@@ -176,7 +177,7 @@ static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
{
unsigned int base = GPIO_BASE(offset / 32);
void __iomem *base = GPIO_BASE(offset / 32);
return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
}
......
arch/arm/mach-gemini/include/mach/hardware.h
View file @ a7726350
......@@ -69,6 +69,6 @@
/*
* macro to get at IO space when running virtually
*/
#define IO_ADDRESS(x) ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
#define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
#endif
arch/arm/mach-gemini/irq.c
View file @ a7726350
......@@ -67,8 +67,8 @@ static struct irq_chip gemini_irq_chip = {
static struct resource irq_resource = {
.name = "irq_handler",
.start = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
.end = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4,
.start = GEMINI_INTERRUPT_BASE,
.end = FIQ_STATUS(GEMINI_INTERRUPT_BASE) + 4,
};
void __init gemini_init_irq(void)
......
arch/arm/mach-gemini/mm.c
View file @ a7726350
......@@ -19,57 +19,57 @@
/* Page table mapping for I/O region */
static struct map_desc gemini_io_desc[] __initdata = {
{
.virtual = IO_ADDRESS(GEMINI_GLOBAL_BASE),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_GLOBAL_BASE),
.pfn =__phys_to_pfn(GEMINI_GLOBAL_BASE),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_UART_BASE),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE),
.pfn = __phys_to_pfn(GEMINI_UART_BASE),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_TIMER_BASE),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_TIMER_BASE),
.pfn = __phys_to_pfn(GEMINI_TIMER_BASE),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_INTERRUPT_BASE),
.pfn = __phys_to_pfn(GEMINI_INTERRUPT_BASE),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
.pfn = __phys_to_pfn(GEMINI_POWER_CTRL_BASE),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_GPIO_BASE(0)),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(0)),
.pfn = __phys_to_pfn(GEMINI_GPIO_BASE(0)),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_GPIO_BASE(1)),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(1)),
.pfn = __phys_to_pfn(GEMINI_GPIO_BASE(1)),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_GPIO_BASE(2)),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(2)),
.pfn = __phys_to_pfn(GEMINI_GPIO_BASE(2)),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
.pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
.pfn = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
.virtual = (unsigned long)IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
.pfn = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE),
.length = SZ_512K,
.type = MT_DEVICE,
......
arch/arm/mach-gemini/include/mach/system.h → arch/arm/mach-gemini/reset.c
View file @ a7726350
......@@ -14,7 +14,7 @@
#include <mach/hardware.h>
#include <mach/global_reg.h>
static inline void arch_reset(char mode, const char *cmd)
void gemini_restart(char mode, const char *cmd)
{
__raw_writel(RESET_GLOBAL | RESET_CPU1,
IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
......
arch/arm/mach-h720x/Kconfig deleted 100644 → 0
View file @ 4d26aa30
if ARCH_H720X
menu "h720x Implementations"
config ARCH_H7201
bool "gms30c7201"
depends on ARCH_H720X
select CPU_H7201
select ZONE_DMA
help
Say Y here if you are using the Hynix GMS30C7201 Reference Board
config ARCH_H7202
bool "hms30c7202"
depends on ARCH_H720X
select CPU_H7202
select ZONE_DMA
help
Say Y here if you are using the Hynix HMS30C7202 Reference Board
endmenu
config CPU_H7201
bool
help
Select code specific to h7201 variants
config CPU_H7202
bool
help
Select code specific to h7202 variants
config H7202_SERIAL23
depends on CPU_H7202
bool "Use serial ports 2+3"
help
Say Y here if you wish to use serial ports 2+3. They share their
pins with the keyboard matrix controller, so you have to decide.
endif
arch/arm/mach-h720x/Makefile deleted 100644 → 0
View file @ 4d26aa30
#
# Makefile for the linux kernel.
#
# Common support
obj-y := common.o
obj-m :=
obj-n :=
obj- :=
# Specific board support
obj-$(CONFIG_ARCH_H7201) += h7201-eval.o
obj-$(CONFIG_ARCH_H7202) += h7202-eval.o
obj-$(CONFIG_CPU_H7201) += cpu-h7201.o
obj-$(CONFIG_CPU_H7202) += cpu-h7202.o
arch/arm/mach-h720x/Makefile.boot deleted 100644 → 0
View file @ 4d26aa30
zreladdr-$(CONFIG_ARCH_H720X) += 0x40008000
arch/arm/mach-h720x/common.c deleted 100644 → 0
View file @ 4d26aa30
/*
* linux/arch/arm/mach-h720x/common.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* common stuff for Hynix h720x processors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/sched.h>
#include <linux/mman.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/dma.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/system_misc.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>
#include <asm/mach/dma.h>
#if 0
#define IRQDBG(args...) printk(args)
#else
#define IRQDBG(args...) do {} while(0)
#endif
void __init arch_dma_init(dma_t *dma)
{
}
/*
* Return nsecs since last timer reload
* (timercount * (usecs perjiffie)) / (ticks per jiffie)
*/
u32 h720x_gettimeoffset(void)
{
return ((CPU_REG(TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH) * 1000;
}
/*
* mask Global irq's
*/
static void mask_global_irq(struct irq_data *d)
{
CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq);
}
/*
* unmask Global irq's
*/
static void unmask_global_irq(struct irq_data *d)
{
CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq);
}
/*
* ack GPIO irq's
* Ack only for edge triggered int's valid
*/
static void inline ack_gpio_irq(struct irq_data *d)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
u32 bit = IRQ_TO_BIT(d->irq);
if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
CPU_REG (reg_base, GPIO_CLR) = bit;
}
/*
* mask GPIO irq's
*/
static void inline mask_gpio_irq(struct irq_data *d)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
u32 bit = IRQ_TO_BIT(d->irq);
CPU_REG (reg_base, GPIO_MASK) &= ~bit;
}
/*
* unmask GPIO irq's
*/
static void inline unmask_gpio_irq(struct irq_data *d)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
u32 bit = IRQ_TO_BIT(d->irq);
CPU_REG (reg_base, GPIO_MASK) |= bit;
}
static void
h720x_gpio_handler(unsigned int mask, unsigned int irq,
struct irq_desc *desc)
{
IRQDBG("%s irq: %d\n", __func__, irq);
while (mask) {
if (mask & 1) {
IRQDBG("handling irq %d\n", irq);
generic_handle_irq(irq);
}
irq++;
mask >>= 1;
}
}
static void
h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOA(0);
IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
static void
h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOB(0);
IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
static void
h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOC(0);
IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
static void
h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOD(0);
IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
#ifdef CONFIG_CPU_H7202
static void
h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOE(0);
IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
#endif
static struct irq_chip h720x_global_chip = {
.irq_ack = mask_global_irq,
.irq_mask = mask_global_irq,
.irq_unmask = unmask_global_irq,
};
static struct irq_chip h720x_gpio_chip = {
.irq_ack = ack_gpio_irq,
.irq_mask = mask_gpio_irq,
.irq_unmask = unmask_gpio_irq,
};
/*
* Initialize IRQ's, mask all, enable multiplexed irq's
*/
void __init h720x_init_irq (void)
{
int irq;
/* Mask global irq's */
CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
/* Mask all multiplexed irq's */
CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
/* Initialize global IRQ's, fast path */
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
irq_set_chip_and_handler(irq, &h720x_global_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* Initialize multiplexed IRQ's, slow path */
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
#ifdef CONFIG_CPU_H7202
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
#endif
/* Enable multiplexed irq's */
CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
}
static struct map_desc h720x_io_desc[] __initdata = {
{
.virtual = IO_VIRT,
.pfn = __phys_to_pfn(IO_PHYS),
.length = IO_SIZE,
.type = MT_DEVICE
},
};
/* Initialize io tables */
void __init h720x_map_io(void)
{
iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
}
void h720x_restart(char mode, const char *cmd)
{
CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
}
static void h720x__idle(void)
{
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
nop();
nop();
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
nop();
nop();
}
static int __init h720x_idle_init(void)
{
arm_pm_idle = h720x__idle;
return 0;
}
arch_initcall(h720x_idle_init);
arch/arm/mach-h720x/common.h deleted 100644 → 0
View file @ 4d26aa30
/*
* linux/arch/arm/mach-h720x/common.h
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* Architecture specific stuff for Hynix GMS30C7201 development board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
extern u32 h720x_gettimeoffset(void);
extern void __init h720x_init_irq(void);
extern void __init h720x_map_io(void);
extern void h720x_restart(char, const char *);
#ifdef CONFIG_ARCH_H7202
extern void h7202_timer_init(void);
extern void __init init_hw_h7202(void);
extern void __init h7202_init_irq(void);
extern void __init h7202_init_time(void);
#endif
#ifdef CONFIG_ARCH_H7201
extern void h7201_timer_init(void);
#endif
arch/arm/mach-h720x/cpu-h7201.c deleted 100644 → 0
View file @ 4d26aa30
/*
* linux/arch/arm/mach-h720x/cpu-h7201.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* processor specific stuff for the Hynix h7201
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/irqs.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include "common.h"
/*
* Timer interrupt handler
*/
static irqreturn_t
h7201_timer_interrupt(int irq, void *dev_id)
{
CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
timer_tick();
return IRQ_HANDLED;
}
static struct irqaction h7201_timer_irq = {
.name = "h7201 Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = h7201_timer_interrupt,
};
/*
* Setup TIMER0 as system timer
*/
void __init h7201_timer_init(void)
{
arch_gettimeoffset = h720x_gettimeoffset;
CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
setup_irq(IRQ_TIMER0, &h7201_timer_irq);
}
arch/arm/mach-h720x/cpu-h7202.c deleted 100644 → 0
View file @ 4d26aa30
/*
* linux/arch/arm/mach-h720x/cpu-h7202.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* processor specific stuff for the Hynix h7202
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/irqs.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <linux/device.h>
#include <linux/serial_8250.h>
#include "common.h"
static struct resource h7202ps2_resources[] = {
[0] = {
.start = 0x8002c000,
.end = 0x8002c040,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PS2,
.end = IRQ_PS2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device h7202ps2_device = {
.name = "h7202ps2",
.id = -1,
.num_resources = ARRAY_SIZE(h7202ps2_resources),
.resource = h7202ps2_resources,
};
static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = (void*)SERIAL0_VIRT,
.mapbase = SERIAL0_BASE,
.irq = IRQ_UART0,
.uartclk = 2*1843200,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
{
.membase = (void*)SERIAL1_VIRT,
.mapbase = SERIAL1_BASE,
.irq = IRQ_UART1,
.uartclk = 2*1843200,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
#ifdef CONFIG_H7202_SERIAL23
{
.membase = (void*)SERIAL2_VIRT,
.mapbase = SERIAL2_BASE,
.irq = IRQ_UART2,
.uartclk = 2*1843200,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
{
.membase = (void*)SERIAL3_VIRT,
.mapbase = SERIAL3_BASE,
.irq = IRQ_UART3,
.uartclk = 2*1843200,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
#endif
{ },
};
static struct platform_device serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
},
};
static struct platform_device *devices[] __initdata = {
&h7202ps2_device,
&serial_device,
};
/* Although we have two interrupt lines for the timers, we only have one
* status register which clears all pending timer interrupts on reading. So
* we have to handle all timer interrupts in one place.
*/
static void
h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
if ( mask & TSTAT_T0INT ) {
timer_tick();
if( mask == TSTAT_T0INT )
return;
}
mask >>= 1;
irq = IRQ_TIMER1;
while (mask) {
if (mask & 1)
generic_handle_irq(irq);
irq++;
mask >>= 1;
}
}
/*
* Timer interrupt handler
*/
static irqreturn_t
h7202_timer_interrupt(int irq, void *dev_id)
{
h7202_timerx_demux_handler(0, NULL);
return IRQ_HANDLED;
}
/*
* mask multiplexed timer IRQs
*/
static void inline __mask_timerx_irq(unsigned int irq)
{
unsigned int bit;
bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
}
static void inline mask_timerx_irq(struct irq_data *d)
{
__mask_timerx_irq(d->irq);
}
/*
* unmask multiplexed timer IRQs
*/
static void inline unmask_timerx_irq(struct irq_data *d)
{
unsigned int bit;
bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
}
static struct irq_chip h7202_timerx_chip = {
.irq_ack = mask_timerx_irq,
.irq_mask = mask_timerx_irq,
.irq_unmask = unmask_timerx_irq,
};
static struct irqaction h7202_timer_irq = {
.name = "h7202 Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = h7202_timer_interrupt,
};
/*
* Setup TIMER0 as system timer
*/
void __init h7202_timer_init(void)
{
arch_gettimeoffset = h720x_gettimeoffset;
CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
setup_irq(IRQ_TIMER0, &h7202_timer_irq);
}
void __init h7202_init_irq (void)
{
int irq;
CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
for (irq = IRQ_TIMER1;
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
__mask_timerx_irq(irq);
irq_set_chip_and_handler(irq, &h7202_timerx_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
h720x_init_irq();
}
void __init init_hw_h7202(void)
{
/* Enable clocks */
CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
#ifdef CONFIG_H7202_SERIAL23
CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
AMULSEL_USIN3 | AMULSEL_USOUT3;
#endif
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
arch/arm/mach-h720x/h7201-eval.c deleted 100644 → 0
View file @ 4d26aa30
/*
* linux/arch/arm/mach-h720x/h7201-eval.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* Architecture specific stuff for Hynix GMS30C7201 development board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/device.h>
#include <asm/setup.h>
#include <asm/types.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/mach/arch.h>
#include <mach/hardware.h>
#include "common.h"
MACHINE_START(H7201, "Hynix GMS30C7201")
/* Maintainer: Robert Schwebel, Pengutronix */
.atag_offset = 0x1000,
.map_io = h720x_map_io,
.init_irq = h720x_init_irq,
.init_time = h7201_timer_init,
.dma_zone_size = SZ_256M,
.restart = h720x_restart,
MACHINE_END
arch/arm/mach-h720x/h7202-eval.c deleted 100644 → 0
View file @ 4d26aa30
/*
* linux/arch/arm/mach-h720x/h7202-eval.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* Architecture specific stuff for Hynix HMS30C7202 development board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <asm/setup.h>
#include <asm/types.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/mach/arch.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
#include "common.h"
static struct resource cirrus_resources[] = {
[0] = {
.start = ETH0_PHYS + 0x300,
.end = ETH0_PHYS + 0x300 + 0x10,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_CHAINED_GPIOB(8),
.end = IRQ_CHAINED_GPIOB(8),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cirrus_device = {
.name = "cirrus-cs89x0",
.id = -1,
.num_resources = ARRAY_SIZE(cirrus_resources),
.resource = cirrus_resources,
};
static struct platform_device *devices[] __initdata = {
&cirrus_device,
};
/*
* Hardware init. This is called early in initcalls
* Place pin inits here. So you avoid adding ugly
* #ifdef stuff to common drivers.
* Use this only, if your bootloader is not able
* to initialize the pins proper.
*/
static void __init init_eval_h7202(void)
{
init_hw_h7202();
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
/* Enable interrupt on portb bit 8 (ethernet) */
CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8);
CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
}
MACHINE_START(H7202, "Hynix HMS30C7202")
/* Maintainer: Robert Schwebel, Pengutronix */
.atag_offset = 0x100,
.map_io = h720x_map_io,
.init_irq = h7202_init_irq,
.init_time = h7202_timer_init,
.init_machine = init_eval_h7202,
.dma_zone_size = SZ_256M,
.restart = h720x_restart,
MACHINE_END
arch/arm/mach-h720x/include/mach/boards.h deleted 100644 → 0
View file @ 4d26aa30
/*
* arch/arm/mach-h720x/include/mach/boards.h
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
*
* This file contains the board specific defines for various devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
#error Do not include this file directly. Include asm/hardware.h instead !
#endif
/* Hynix H7202 developer board specific device defines */
#ifdef CONFIG_ARCH_H7202
/* FLASH */
#define H720X_FLASH_VIRT 0xd0000000
#define H720X_FLASH_PHYS 0x00000000
#define H720X_FLASH_SIZE 0x02000000
/* onboard LAN controller */
# define ETH0_PHYS 0x08000000
/* Touch screen defines */
/* GPIO Port */
#define PEN_GPIO GPIO_B_VIRT
/* Bitmask for pen down interrupt */
#define PEN_INT_BIT (1<<7)
/* Bitmask for pen up interrupt */
#define PEN_ENA_BIT (1<<6)
/* pen up interrupt */
#define IRQ_PEN IRQ_MUX_GPIOB(7)
#endif
/* Hynix H7201 developer board specific device defines */
#if defined (CONFIG_ARCH_H7201)
/* ROM DISK SPACE */
#define ROM_DISK_BASE 0xc1800000
#define ROM_DISK_START 0x41800000
#define ROM_DISK_SIZE 0x00700000
/* SRAM DISK SPACE */
#define SRAM_DISK_BASE 0xf1000000
#define SRAM_DISK_START 0x04000000
#define SRAM_DISK_SIZE 0x00400000
#endif
arch/arm/mach-h720x/include/mach/debug-macro.S deleted 100644 → 0
View file @ 4d26aa30
/* arch/arm/mach-h720x/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/hardware.h>
.equ io_virt, IO_VIRT
.equ io_phys, IO_PHYS
.macro addruart, rp, rv, tmp
mov \rp, #0x00020000 @ UART1
add \rv, \rp, #io_virt @ virtual address
add \rp, \rp, #io_phys @ physical base address
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x0] @ UARTDR
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
bne 1001b
.endm
arch/arm/mach-h720x/include/mach/entry-macro.S deleted 100644 → 0
View file @ 4d26aa30
/*
* arch/arm/mach-h720x/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for Hynix HMS720x based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro get_irqnr_preamble, base, tmp
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
@ we could use the id register on H7202, but this is not
@ properly updated when we come back from asm_do_irq
@ without a previous return from interrupt
@ (see loops below in irq_svc, irq_usr)
@ We see unmasked pending ints only, as the masked pending ints
@ are not visible here
mov \base, #0xf0000000 @ base register
orr \base, \base, #0x24000 @ irqbase
ldr \irqstat, [\base, #0x04] @ get interrupt status
#if defined (CONFIG_CPU_H7201)
ldr \tmp, =0x001fffff
#else
mvn \tmp, #0xc0000000
#endif
and \irqstat, \irqstat, \tmp @ mask out unused ints
mov \irqnr, #0
mov \tmp, #0xff00
orr \tmp, \tmp, #0xff
tst \irqstat, \tmp
addeq \irqnr, \irqnr, #16
moveq \irqstat, \irqstat, lsr #16
tst \irqstat, #255
addeq \irqnr, \irqnr, #8
moveq \irqstat, \irqstat, lsr #8
tst \irqstat, #15
addeq \irqnr, \irqnr, #4
moveq \irqstat, \irqstat, lsr #4
tst \irqstat, #3
addeq \irqnr, \irqnr, #2
moveq \irqstat, \irqstat, lsr #2
tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tst \irqstat, #1 @ bit 0 should be set
.endm
#else
#error hynix processor selection missmatch
#endif
arch/arm/mach-h720x/include/mach/h7201-regs.h deleted 100644 → 0
View file @ 4d26aa30
/*
* arch/arm/mach-h720x/include/mach/h7201-regs.h
*
* Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* This file contains the hardware definitions of the h720x processors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Do not add implementations specific defines here. This files contains
* only defines of the onchip peripherals. Add those defines to boards.h,
* which is included by this file.
*/
#define SERIAL2_VIRT (IO_VIRT + 0x50100)
#define SERIAL3_VIRT (IO_VIRT + 0x50200)
/*
* PCMCIA
*/
#define PCMCIA0_ATT_BASE 0xe5000000
#define PCMCIA0_ATT_SIZE 0x00200000
#define PCMCIA0_ATT_START 0x20000000
#define PCMCIA0_MEM_BASE 0xe5200000
#define PCMCIA0_MEM_SIZE 0x00200000
#define PCMCIA0_MEM_START 0x24000000
#define PCMCIA0_IO_BASE 0xe5400000
#define PCMCIA0_IO_SIZE 0x00200000
#define PCMCIA0_IO_START 0x28000000
#define PCMCIA1_ATT_BASE 0xe5600000
#define PCMCIA1_ATT_SIZE 0x00200000
#define PCMCIA1_ATT_START 0x30000000
#define PCMCIA1_MEM_BASE 0xe5800000
#define PCMCIA1_MEM_SIZE 0x00200000
#define PCMCIA1_MEM_START 0x34000000
#define PCMCIA1_IO_BASE 0xe5a00000
#define PCMCIA1_IO_SIZE 0x00200000
#define PCMCIA1_IO_START 0x38000000
#define PRIME3C_BASE 0xf0050000
#define PRIME3C_SIZE 0x00001000
#define PRIME3C_START 0x10000000
/* VGA Controller */
#define VGA_RAMBASE 0x50
#define VGA_TIMING0 0x60
#define VGA_TIMING1 0x64
#define VGA_TIMING2 0x68
#define VGA_TIMING3 0x6c
#define LCD_CTRL_VGA_ENABLE 0x00000100
#define LCD_CTRL_VGA_BPP_MASK 0x00000600
#define LCD_CTRL_VGA_4BPP 0x00000000
#define LCD_CTRL_VGA_8BPP 0x00000200
#define LCD_CTRL_VGA_16BPP 0x00000300
#define LCD_CTRL_SHARE_DMA 0x00000800
#define LCD_CTRL_VDE 0x00100000
#define LCD_CTRL_LPE 0x00400000 /* LCD Power enable */
#define LCD_CTRL_BLE 0x00800000 /* LCD backlight enable */
#define VGA_PALETTE_BASE (IO_VIRT + 0x10800)
arch/arm/mach-h720x/include/mach/h7202-regs.h deleted 100644 → 0
View file @ 4d26aa30
/*
* arch/arm/mach-h720x/include/mach/h7202-regs.h
*
* Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* This file contains the hardware definitions of the h720x processors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Do not add implementations specific defines here. This files contains
* only defines of the onchip peripherals. Add those defines to boards.h,
* which is included by this file.
*/
#define SERIAL2_OFS 0x2d000
#define SERIAL2_BASE (IO_PHYS + SERIAL2_OFS)
#define SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS)
#define SERIAL3_OFS 0x2e000
#define SERIAL3_BASE (IO_PHYS + SERIAL3_OFS)
#define SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS)
/* Matrix Keyboard Controller */
#define KBD_VIRT (IO_VIRT + 0x22000)
#define KBD_KBCR 0x00
#define KBD_KBSC 0x04
#define KBD_KBTR 0x08
#define KBD_KBVR0 0x0C
#define KBD_KBVR1 0x10
#define KBD_KBSR 0x18
#define KBD_KBCR_SCANENABLE (1 << 7)
#define KBD_KBCR_NPOWERDOWN (1 << 2)
#define KBD_KBCR_CLKSEL_MASK (3)
#define KBD_KBCR_CLKSEL_PCLK2 0x0
#define KBD_KBCR_CLKSEL_PCLK128 0x1
#define KBD_KBCR_CLKSEL_PCLK256 0x2
#define KBD_KBCR_CLKSEL_PCLK512 0x3
#define KBD_KBSR_INTR (1 << 0)
#define KBD_KBSR_WAKEUP (1 << 1)
/* USB device controller */
#define USBD_BASE (IO_VIRT + 0x12000)
#define USBD_LENGTH 0x3C
#define USBD_GCTRL 0x00
#define USBD_EPCTRL 0x04
#define USBD_INTMASK 0x08
#define USBD_INTSTAT 0x0C
#define USBD_PWR 0x10
#define USBD_DMARXTX 0x14
#define USBD_DEVID 0x18
#define USBD_DEVCLASS 0x1C
#define USBD_INTCLASS 0x20
#define USBD_SETUP0 0x24
#define USBD_SETUP1 0x28
#define USBD_ENDP0RD 0x2C
#define USBD_ENDP0WT 0x30
#define USBD_ENDP1RD 0x34
#define USBD_ENDP2WT 0x38
/* PS/2 port */
#define PSDATA 0x00
#define PSSTAT 0x04
#define PSSTAT_TXEMPTY (1<<0)
#define PSSTAT_TXBUSY (1<<1)
#define PSSTAT_RXFULL (1<<2)
#define PSSTAT_RXBUSY (1<<3)
#define PSSTAT_CLKIN (1<<4)
#define PSSTAT_DATAIN (1<<5)
#define PSSTAT_PARITY (1<<6)
#define PSCONF 0x08
#define PSCONF_ENABLE (1<<0)
#define PSCONF_TXINTEN (1<<2)
#define PSCONF_RXINTEN (1<<3)
#define PSCONF_FORCECLKLOW (1<<4)
#define PSCONF_FORCEDATLOW (1<<5)
#define PSCONF_LCE (1<<6)
#define PSINTR 0x0C
#define PSINTR_TXINT (1<<0)
#define PSINTR_RXINT (1<<1)
#define PSINTR_PAR (1<<2)
#define PSINTR_RXTO (1<<3)
#define PSINTR_TXTO (1<<4)
#define PSTDLO 0x10 /* clk low before start transmission */
#define PSTPRI 0x14 /* PRI clock */
#define PSTXMT 0x18 /* maximum transmission time */
#define PSTREC 0x20 /* maximum receive time */
#define PSPWDN 0x3c
/* ADC converter */
#define ADC_BASE (IO_VIRT + 0x29000)
#define ADC_CR 0x00
#define ADC_TSCTRL 0x04
#define ADC_BT_CTRL 0x08
#define ADC_MC_CTRL 0x0C
#define ADC_STATUS 0x10
/* ADC control register bits */
#define ADC_CR_PW_CTRL 0x80
#define ADC_CR_DIRECTC 0x04
#define ADC_CR_CONTIME_NO 0x00
#define ADC_CR_CONTIME_2 0x04
#define ADC_CR_CONTIME_4 0x08
#define ADC_CR_CONTIME_ADE 0x0c
#define ADC_CR_LONGCALTIME 0x01
/* ADC touch panel register bits */
#define ADC_TSCTRL_ENABLE 0x80
#define ADC_TSCTRL_INTR 0x40
#define ADC_TSCTRL_SWBYPSS 0x20
#define ADC_TSCTRL_SWINVT 0x10
#define ADC_TSCTRL_S400 0x03
#define ADC_TSCTRL_S200 0x02
#define ADC_TSCTRL_S100 0x01
#define ADC_TSCTRL_S50 0x00
/* ADC Interrupt Status Register bits */
#define ADC_STATUS_TS_BIT 0x80
#define ADC_STATUS_MBT_BIT 0x40
#define ADC_STATUS_BBT_BIT 0x20
#define ADC_STATUS_MIC_BIT 0x10
/* Touch data registers */
#define ADC_TS_X0X1 0x30
#define ADC_TS_X2X3 0x34
#define ADC_TS_Y0Y1 0x38
#define ADC_TS_Y2Y3 0x3c
#define ADC_TS_X4X5 0x40
#define ADC_TS_X6X7 0x44
#define ADC_TS_Y4Y5 0x48
#define ADC_TS_Y6Y7 0x50
/* battery data */
#define ADC_MB_DATA 0x54
#define ADC_BB_DATA 0x58
/* Sound data register */
#define ADC_SD_DAT0 0x60
#define ADC_SD_DAT1 0x64
#define ADC_SD_DAT2 0x68
#define ADC_SD_DAT3 0x6c
#define ADC_SD_DAT4 0x70
#define ADC_SD_DAT5 0x74
#define ADC_SD_DAT6 0x78
#define ADC_SD_DAT7 0x7c
arch/arm/mach-h720x/include/mach/hardware.h deleted 100644 → 0
View file @ 4d26aa30
/*
* arch/arm/mach-h720x/include/mach/hardware.h
*
* Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
*
* This file contains the hardware definitions of the h720x processors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Do not add implementations specific defines here. This files contains
* only defines of the onchip peripherals. Add those defines to boards.h,
* which is included by this file.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#define IOCLK (3686400L)
/* Onchip peripherals */
#define IO_VIRT 0xf0000000 /* IO peripherals */
#define IO_PHYS 0x80000000
#define IO_SIZE 0x00050000
#ifdef CONFIG_CPU_H7202
#include "h7202-regs.h"
#elif defined CONFIG_CPU_H7201
#include "h7201-regs.h"
#else
#error machine definition mismatch
#endif
/* Macro to access the CPU IO */
#define CPU_IO(x) (*(volatile u32*)(x))
/* Macro to access general purpose regs (base, offset) */
#define CPU_REG(x,y) CPU_IO(x+y)
/* Macro to access irq related regs */
#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
/* CPU registers */
/* general purpose I/O */
#define GPIO_VIRT(x) (IO_VIRT + 0x23000 + ((x)<<5))
#define GPIO_A_VIRT (GPIO_VIRT(0))
#define GPIO_B_VIRT (GPIO_VIRT(1))
#define GPIO_C_VIRT (GPIO_VIRT(2))
#define GPIO_D_VIRT (GPIO_VIRT(3))
#define GPIO_E_VIRT (GPIO_VIRT(4))
#define GPIO_AMULSEL (GPIO_VIRT(0) + 0xA4)
#define AMULSEL_USIN2 (1<<5)
#define AMULSEL_USOUT2 (1<<6)
#define AMULSEL_USIN3 (1<<13)
#define AMULSEL_USOUT3 (1<<14)
#define AMULSEL_IRDIN (1<<15)
#define AMULSEL_IRDOUT (1<<7)
/* Register offsets general purpose I/O */
#define GPIO_DATA 0x00
#define GPIO_DIR 0x04
#define GPIO_MASK 0x08
#define GPIO_STAT 0x0C
#define GPIO_EDGE 0x10
#define GPIO_CLR 0x14
#define GPIO_POL 0x18
#define GPIO_EN 0x1C
/*interrupt controller */
#define IRQC_VIRT (IO_VIRT + 0x24000)
/* register offset interrupt controller */
#define IRQC_IER 0x00
#define IRQC_ISR 0x04
/* timer unit */
#define TIMER_VIRT (IO_VIRT + 0x25000)
/* Register offsets timer unit */
#define TM0_PERIOD 0x00
#define TM0_COUNT 0x08
#define TM0_CTRL 0x10
#define TM1_PERIOD 0x20
#define TM1_COUNT 0x28
#define TM1_CTRL 0x30
#define TM2_PERIOD 0x40
#define TM2_COUNT 0x48
#define TM2_CTRL 0x50
#define TIMER_TOPCTRL 0x60
#define TIMER_TOPSTAT 0x64
#define T64_COUNTL 0x80
#define T64_COUNTH 0x84
#define T64_CTRL 0x88
#define T64_BASEL 0x94
#define T64_BASEH 0x98
/* Bitmaks timer unit TOPSTAT reg */
#define TSTAT_T0INT 0x1
#define TSTAT_T1INT 0x2
#define TSTAT_T2INT 0x4
#define TSTAT_T3INT 0x8
/* Bit description of TMx_CTRL register */
#define TM_START 0x1
#define TM_REPEAT 0x2
#define TM_RESET 0x4
/* Bit description of TIMER_CTRL register */
#define ENABLE_TM0_INTR 0x1
#define ENABLE_TM1_INTR 0x2
#define ENABLE_TM2_INTR 0x4
#define TIMER_ENABLE_BIT 0x8
#define ENABLE_TIMER64 0x10
#define ENABLE_TIMER64_INT 0x20
/* PMU & PLL */
#define PMU_BASE (IO_VIRT + 0x1000)
#define PMU_MODE 0x00
#define PMU_STAT 0x20
#define PMU_PLL_CTRL 0x28
/* PMU Mode bits */
#define PMU_MODE_SLOW 0x00
#define PMU_MODE_RUN 0x01
#define PMU_MODE_IDLE 0x02
#define PMU_MODE_SLEEP 0x03
#define PMU_MODE_INIT 0x04
#define PMU_MODE_DEEPSLEEP 0x07
#define PMU_MODE_WAKEUP 0x08
/* PMU ... */
#define PLL_2_EN 0x8000
#define PLL_1_EN 0x4000
#define PLL_3_MUTE 0x0080
/* Control bits for PMU/ PLL */
#define PMU_WARMRESET 0x00010000
#define PLL_CTRL_MASK23 0x000080ff
/* LCD Controller */
#define LCD_BASE (IO_VIRT + 0x10000)
#define LCD_CTRL 0x00
#define LCD_STATUS 0x04
#define LCD_STATUS_M 0x08
#define LCD_INTERRUPT 0x0C
#define LCD_DBAR 0x10
#define LCD_DCAR 0x14
#define LCD_TIMING0 0x20
#define LCD_TIMING1 0x24
#define LCD_TIMING2 0x28
#define LCD_TEST 0x40
/* LCD Control Bits */
#define LCD_CTRL_LCD_ENABLE 0x00000001
/* Bits per pixel */
#define LCD_CTRL_LCD_BPP_MASK 0x00000006
#define LCD_CTRL_LCD_4BPP 0x00000000
#define LCD_CTRL_LCD_8BPP 0x00000002
#define LCD_CTRL_LCD_16BPP 0x00000004
#define LCD_CTRL_LCD_BW 0x00000008
#define LCD_CTRL_LCD_TFT 0x00000010
#define LCD_CTRL_BGR 0x00001000
#define LCD_CTRL_LCD_VCOMP 0x00080000
#define LCD_CTRL_LCD_MONO8 0x00200000
#define LCD_CTRL_LCD_PWR 0x00400000
#define LCD_CTRL_LCD_BLE 0x00800000
#define LCD_CTRL_LDBUSEN 0x01000000
/* Palette */
#define LCD_PALETTE_BASE (IO_VIRT + 0x10400)
/* Serial ports */
#define SERIAL0_OFS 0x20000
#define SERIAL0_VIRT (IO_VIRT + SERIAL0_OFS)
#define SERIAL0_BASE (IO_PHYS + SERIAL0_OFS)
#define SERIAL1_OFS 0x21000
#define SERIAL1_VIRT (IO_VIRT + SERIAL1_OFS)
#define SERIAL1_BASE (IO_PHYS + SERIAL1_OFS)
#define SERIAL_ENABLE 0x30
#define SERIAL_ENABLE_EN (1<<0)
/* General defines to pacify gcc */
#define __ASM_ARCH_HARDWARE_INCMACH_H
#include "boards.h"
#undef __ASM_ARCH_HARDWARE_INCMACH_H
#endif /* __ASM_ARCH_HARDWARE_H */
arch/arm/mach-h720x/include/mach/irqs.h deleted 100644 → 0
View file @ 4d26aa30
/*
* arch/arm/mach-h720x/include/mach/irqs.h
*
* Copyright (C) 2000 Jungjun Kim
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
*
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#if defined (CONFIG_CPU_H7201)
#define IRQ_PMU 0 /* 0x000001 */
#define IRQ_DMA 1 /* 0x000002 */
#define IRQ_LCD 2 /* 0x000004 */
#define IRQ_VGA 3 /* 0x000008 */
#define IRQ_PCMCIA1 4 /* 0x000010 */
#define IRQ_PCMCIA2 5 /* 0x000020 */
#define IRQ_AFE 6 /* 0x000040 */
#define IRQ_AIC 7 /* 0x000080 */
#define IRQ_KEYBOARD 8 /* 0x000100 */
#define IRQ_TIMER0 9 /* 0x000200 */
#define IRQ_RTC 10 /* 0x000400 */
#define IRQ_SOUND 11 /* 0x000800 */
#define IRQ_USB 12 /* 0x001000 */
#define IRQ_IrDA 13 /* 0x002000 */
#define IRQ_UART0 14 /* 0x004000 */
#define IRQ_UART1 15 /* 0x008000 */
#define IRQ_SPI 16 /* 0x010000 */
#define IRQ_GPIOA 17 /* 0x020000 */
#define IRQ_GPIOB 18 /* 0x040000 */
#define IRQ_GPIOC 19 /* 0x080000 */
#define IRQ_GPIOD 20 /* 0x100000 */
#define IRQ_CommRX 21 /* 0x200000 */
#define IRQ_CommTX 22 /* 0x400000 */
#define IRQ_Soft 23 /* 0x800000 */
#define NR_GLBL_IRQS 24
#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
#define NR_IRQS IRQ_CHAINED_GPIOD(32)
/* Enable mask for multiplexed interrupts */
#define IRQ_ENA_MUX (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
| (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
#elif defined (CONFIG_CPU_H7202)
#define IRQ_PMU 0 /* 0x00000001 */
#define IRQ_DMA 1 /* 0x00000002 */
#define IRQ_LCD 2 /* 0x00000004 */
#define IRQ_SOUND 3 /* 0x00000008 */
#define IRQ_I2S 4 /* 0x00000010 */
#define IRQ_USB 5 /* 0x00000020 */
#define IRQ_MMC 6 /* 0x00000040 */
#define IRQ_RTC 7 /* 0x00000080 */
#define IRQ_UART0 8 /* 0x00000100 */
#define IRQ_UART1 9 /* 0x00000200 */
#define IRQ_UART2 10 /* 0x00000400 */
#define IRQ_UART3 11 /* 0x00000800 */
#define IRQ_KBD 12 /* 0x00001000 */
#define IRQ_PS2 13 /* 0x00002000 */
#define IRQ_AIC 14 /* 0x00004000 */
#define IRQ_TIMER0 15 /* 0x00008000 */
#define IRQ_TIMERX 16 /* 0x00010000 */
#define IRQ_WDT 17 /* 0x00020000 */
#define IRQ_CAN0 18 /* 0x00040000 */
#define IRQ_CAN1 19 /* 0x00080000 */
#define IRQ_EXT0 20 /* 0x00100000 */
#define IRQ_EXT1 21 /* 0x00200000 */
#define IRQ_GPIOA 22 /* 0x00400000 */
#define IRQ_GPIOB 23 /* 0x00800000 */
#define IRQ_GPIOC 24 /* 0x01000000 */
#define IRQ_GPIOD 25 /* 0x02000000 */
#define IRQ_GPIOE 26 /* 0x04000000 */
#define IRQ_COMMRX 27 /* 0x08000000 */
#define IRQ_COMMTX 28 /* 0x10000000 */
#define IRQ_SMC 29 /* 0x20000000 */
#define IRQ_Soft 30 /* 0x40000000 */
#define IRQ_RESERVED1 31 /* 0x80000000 */
#define NR_GLBL_IRQS 32
#define NR_TIMERX_IRQS 3
#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
#define IRQ_CHAINED_GPIOE(x) (IRQ_CHAINED_GPIOD(32) + x)
#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
#define IRQ_TIMER1 (IRQ_CHAINED_TIMERX(0))
#define IRQ_TIMER2 (IRQ_CHAINED_TIMERX(1))
#define IRQ_TIMER64B (IRQ_CHAINED_TIMERX(2))
#define NR_IRQS (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
/* Enable mask for multiplexed interrupts */
#define IRQ_ENA_MUX (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
(1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
(1<<IRQ_TIMERX)
#else
#error cpu definition mismatch
#endif
/* decode irq number to register number */
#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
#endif
arch/arm/mach-h720x/include/mach/isa-dma.h deleted 100644 → 0
View file @ 4d26aa30
/*
* arch/arm/mach-h720x/include/mach/isa-dma.h
*
* Architecture DMA routes
*
* Copyright (C) 1997.1998 Russell King
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#if defined (CONFIG_CPU_H7201)
#define MAX_DMA_CHANNELS 3
#elif defined (CONFIG_CPU_H7202)
#define MAX_DMA_CHANNELS 4
#else
#error processor definition missmatch
#endif
#endif /* __ASM_ARCH_DMA_H */
arch/arm/mach-h720x/include/mach/uncompress.h deleted 100644 → 0
View file @ 4d26aa30
/*
* arch/arm/mach-h720x/include/mach/uncompress.h
*
* Copyright (C) 2001-2002 Jungjun Kim
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/hardware.h>
#define LSR 0x14
#define TEMPTY 0x40
static inline void putc(int c)
{
volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
/* wait until transmit buffer is empty */
while((p[LSR] & TEMPTY) == 0x0)
barrier();
/* write next character */
*p = c;
}
static inline void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#endif
arch/arm/mach-highbank/highbank.c
View file @ a7726350
......@@ -32,7 +32,6 @@
#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/smp_plat.h>
#include <asm/smp_twd.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
#include <asm/hardware/cache-l2x0.h>
......@@ -119,10 +118,10 @@ static void __init highbank_timer_init(void)
sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
sp804_clockevents_init(timer_base, irq, "timer0");
twd_local_timer_of_register();
arch_timer_of_register();
arch_timer_sched_clock_init();
clocksource_of_init();
}
static void highbank_power_off(void)
......
arch/arm/mach-highbank/platsmp.c
View file @ a7726350
......@@ -17,7 +17,6 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/smp_scu.h>
......@@ -25,11 +24,6 @@
extern void secondary_startup(void);
static void __cpuinit highbank_secondary_init(unsigned int cpu)
{
gic_secondary_init(0);
}
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
highbank_set_cpu_jump(cpu, secondary_startup);
......@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
struct smp_operations highbank_smp_ops __initdata = {
.smp_init_cpus = highbank_smp_init_cpus,
.smp_prepare_cpus = highbank_smp_prepare_cpus,
.smp_secondary_init = highbank_secondary_init,
.smp_boot_secondary = highbank_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = highbank_cpu_die,
......
arch/arm/mach-imx/Kconfig
View file @ a7726350
......@@ -83,24 +83,12 @@ config ARCH_MXC_IOMUX_V3
config ARCH_MX1
bool
config MACH_MX21
bool
config ARCH_MX25
bool
config MACH_MX27
bool
config ARCH_MX5
bool
config ARCH_MX51
bool
config ARCH_MX53
bool
config SOC_IMX1
bool
select ARCH_MX1
......@@ -114,7 +102,6 @@ config SOC_IMX21
select COMMON_CLK
select CPU_ARM926T
select IMX_HAVE_IOMUX_V1
select MACH_MX21
select MXC_AVIC
config SOC_IMX25
......@@ -155,7 +142,6 @@ config SOC_IMX35
config SOC_IMX5
bool
select ARCH_HAS_CPUFREQ
select ARCH_MX5
select ARCH_MXC_IOMUX_V3
select COMMON_CLK
select CPU_V7
......@@ -163,8 +149,6 @@ config SOC_IMX5
config SOC_IMX51
bool
select ARCH_MX5
select ARCH_MX51
select PINCTRL
select PINCTRL_IMX51
select SOC_IMX5
......@@ -789,8 +773,6 @@ comment "Device tree only"
config SOC_IMX53
bool "i.MX53 support"
select ARCH_MX5
select ARCH_MX53
select HAVE_CAN_FLEXCAN if CAN
select IMX_HAVE_PLATFORM_IMX2_WDT
select PINCTRL
......
arch/arm/mach-imx/Makefile
View file @ a7726350
......@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
imx5-pm-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
clk-pfd.o clk-busy.o clk.o
......@@ -27,7 +27,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
obj-$(CONFIG_MXC_ULPI) += ulpi.o
obj-$(CONFIG_MXC_USE_EPIT) += epit.o
obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
......
arch/arm/mach-imx/Makefile.boot deleted 100644 → 0
View file @ 4d26aa30
zreladdr-$(CONFIG_SOC_IMX1) += 0x08008000
params_phys-$(CONFIG_SOC_IMX1) := 0x08000100
initrd_phys-$(CONFIG_SOC_IMX1) := 0x08800000
zreladdr-$(CONFIG_SOC_IMX21) += 0xC0008000
params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100
initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000
zreladdr-$(CONFIG_SOC_IMX25) += 0x80008000
params_phys-$(CONFIG_SOC_IMX25) := 0x80000100
initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000
zreladdr-$(CONFIG_SOC_IMX27) += 0xA0008000
params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100
initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000
zreladdr-$(CONFIG_SOC_IMX31) += 0x80008000
params_phys-$(CONFIG_SOC_IMX31) := 0x80000100
initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000
zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000
params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
arch/arm/mach-imx/avic.c
View file @ a7726350
......@@ -54,8 +54,6 @@
static void __iomem *avic_base;
static struct irq_domain *domain;
static u32 avic_saved_mask_reg[2];
#ifdef CONFIG_MXC_IRQ_PRIOR
static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
{
......@@ -113,6 +111,8 @@ static struct mxc_extra_irq avic_extra_irq = {
};
#ifdef CONFIG_PM
static u32 avic_saved_mask_reg[2];
static void avic_irq_suspend(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
......
arch/arm/mach-imx/clk-imx27.c
View file @ a7726350
......@@ -278,8 +278,6 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
clk_register_clkdev(clk[cpu_div], "cpu", NULL);
clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
......
arch/arm/mach-imx/common.h
View file @ a7726350
......@@ -113,7 +113,6 @@ extern void imx_set_cpu_jump(int cpu, void *jump_addr);
extern u32 imx_get_cpu_arg(int cpu);
extern void imx_set_cpu_arg(int cpu, u32 arg);
extern void v7_cpu_resume(void);
extern u32 *pl310_get_save_ptr(void);
#ifdef CONFIG_SMP
extern void v7_secondary_startup(void);
extern void imx_scu_map_io(void);
......@@ -124,8 +123,6 @@ static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
static inline void imx_scu_standby_enable(void) {}
#endif
extern void imx_enable_cpu(int cpu, bool enable);
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
extern void imx_src_init(void);
extern void imx_src_prepare_restart(void);
extern void imx_gpc_init(void);
......
arch/arm/mach-imx/cpu_op-mx51.c deleted 100644 → 0
View file @ 4d26aa30
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/bug.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include "hardware.h"
static struct cpu_op mx51_cpu_op[] = {
{
.cpu_rate = 160000000,},
{
.cpu_rate = 800000000,},
};
struct cpu_op *mx51_get_cpu_op(int *op)
{
*op = ARRAY_SIZE(mx51_cpu_op);
return mx51_cpu_op;
}
arch/arm/mach-imx/cpu_op-mx51.h deleted 100644 → 0
View file @ 4d26aa30
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
extern struct cpu_op *mx51_get_cpu_op(int *op);
arch/arm/mach-imx/cpufreq.c deleted 100644 → 0
View file @ 4d26aa30
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*
* A driver for the Freescale Semiconductor i.MXC CPUfreq module.
* The CPUFREQ driver is for controlling CPU frequency. It allows you to change
* the CPU clock speed on the fly.
*/
#include <linux/module.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/slab.h>
#include "hardware.h"
#define CLK32_FREQ 32768
#define NANOSECOND (1000 * 1000 * 1000)
struct cpu_op *(*get_cpu_op)(int *op);
static int cpu_freq_khz_min;
static int cpu_freq_khz_max;
static struct clk *cpu_clk;
static struct cpufreq_frequency_table *imx_freq_table;
static int cpu_op_nr;
static struct cpu_op *cpu_op_tbl;
static int set_cpu_freq(int freq)
{
int ret = 0;
int org_cpu_rate;
org_cpu_rate = clk_get_rate(cpu_clk);
if (org_cpu_rate == freq)
return ret;
ret = clk_set_rate(cpu_clk, freq);
if (ret != 0) {
printk(KERN_DEBUG "cannot set CPU clock rate\n");
return ret;
}
return ret;
}
static int mxc_verify_speed(struct cpufreq_policy *policy)
{
if (policy->cpu != 0)
return -EINVAL;
return cpufreq_frequency_table_verify(policy, imx_freq_table);
}
static unsigned int mxc_get_speed(unsigned int cpu)
{
if (cpu)
return 0;
return clk_get_rate(cpu_clk) / 1000;
}
static int mxc_set_target(struct cpufreq_policy *policy,
unsigned int target_freq, unsigned int relation)
{
struct cpufreq_freqs freqs;
int freq_Hz;
int ret = 0;
unsigned int index;
cpufreq_frequency_table_target(policy, imx_freq_table,
target_freq, relation, &index);
freq_Hz = imx_freq_table[index].frequency * 1000;
freqs.old = clk_get_rate(cpu_clk) / 1000;
freqs.new = freq_Hz / 1000;
freqs.flags = 0;
cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
ret = set_cpu_freq(freq_Hz);
cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
return ret;
}
static int mxc_cpufreq_init(struct cpufreq_policy *policy)
{
int ret;
int i;
printk(KERN_INFO "i.MXC CPU frequency driver\n");
if (policy->cpu != 0)
return -EINVAL;
if (!get_cpu_op)
return -EINVAL;
cpu_clk = clk_get(NULL, "cpu_clk");
if (IS_ERR(cpu_clk)) {
printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
return PTR_ERR(cpu_clk);
}
cpu_op_tbl = get_cpu_op(&cpu_op_nr);
cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
imx_freq_table = kmalloc(
sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
GFP_KERNEL);
if (!imx_freq_table) {
ret = -ENOMEM;
goto err1;
}
for (i = 0; i < cpu_op_nr; i++) {
imx_freq_table[i].index = i;
imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
}
imx_freq_table[i].index = i;
imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
policy->cur = clk_get_rate(cpu_clk) / 1000;
/* Manual states, that PLL stabilizes in two CLK32 periods */
policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
if (ret < 0) {
printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n",
__func__, ret);
goto err;
}
cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
return 0;
err:
kfree(imx_freq_table);
err1:
clk_put(cpu_clk);
return ret;
}
static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
{
cpufreq_frequency_table_put_attr(policy->cpu);
set_cpu_freq(cpu_freq_khz_max * 1000);
clk_put(cpu_clk);
kfree(imx_freq_table);
return 0;
}
static struct cpufreq_driver mxc_driver = {
.flags = CPUFREQ_STICKY,
.verify = mxc_verify_speed,
.target = mxc_set_target,
.get = mxc_get_speed,
.init = mxc_cpufreq_init,
.exit = mxc_cpufreq_exit,
.name = "imx",
};
static int mxc_cpufreq_driver_init(void)
{
return cpufreq_register_driver(&mxc_driver);
}
static void mxc_cpufreq_driver_exit(void)
{
cpufreq_unregister_driver(&mxc_driver);
}
module_init(mxc_cpufreq_driver_init);
module_exit(mxc_cpufreq_driver_exit);
MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
MODULE_DESCRIPTION("CPUfreq driver for i.MX");
MODULE_LICENSE("GPL");
arch/arm/mach-imx/devices/Kconfig
View file @ a7726350
......@@ -86,7 +86,3 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
config IMX_HAVE_PLATFORM_SPI_IMX
bool
config IMX_HAVE_PLATFORM_AHCI
bool
default y if ARCH_MX53
arch/arm/mach-imx/devices/Makefile
View file @ a7726350
......@@ -29,5 +29,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
arch/arm/mach-imx/devices/devices-common.h
View file @ a7726350
......@@ -344,13 +344,3 @@ struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
int irq, int irq_err);
struct platform_device *imx_add_imx_sdma(char *name,
resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
#include <linux/ahci_platform.h>
struct imx_ahci_imx_data {
const char *devid;
resource_size_t iobase;
resource_size_t irq;
};
struct platform_device *__init imx_add_ahci_imx(
const struct imx_ahci_imx_data *data,
const struct ahci_platform_data *pdata);
arch/arm/mach-imx/devices/platform-ahci-imx.c deleted 100644 → 0
View file @ 4d26aa30
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <asm/sizes.h>
#include "../hardware.h"
#include "devices-common.h"
#define imx_ahci_imx_data_entry_single(soc, _devid) \
{ \
.devid = _devid, \
.iobase = soc ## _SATA_BASE_ADDR, \
.irq = soc ## _INT_SATA, \
}
#ifdef CONFIG_SOC_IMX53
const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
#endif
enum {
HOST_CAP = 0x00,
HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
HOST_PORTS_IMPL = 0x0c,
HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
};
static struct clk *sata_clk, *sata_ref_clk;
/* AHCI module Initialization, if return 0, initialization is successful. */
static int imx_sata_init(struct device *dev, void __iomem *addr)
{
u32 tmpdata;
int ret = 0;
struct clk *clk;
sata_clk = clk_get(dev, "ahci");
if (IS_ERR(sata_clk)) {
dev_err(dev, "no sata clock.\n");
return PTR_ERR(sata_clk);
}
ret = clk_prepare_enable(sata_clk);
if (ret) {
dev_err(dev, "can't prepare/enable sata clock.\n");
goto put_sata_clk;
}
/* Get the AHCI SATA PHY CLK */
sata_ref_clk = clk_get(dev, "ahci_phy");
if (IS_ERR(sata_ref_clk)) {
dev_err(dev, "no sata ref clock.\n");
ret = PTR_ERR(sata_ref_clk);
goto release_sata_clk;
}
ret = clk_prepare_enable(sata_ref_clk);
if (ret) {
dev_err(dev, "can't prepare/enable sata ref clock.\n");
goto put_sata_ref_clk;
}
/* Get the AHB clock rate, and configure the TIMER1MS reg later */
clk = clk_get(dev, "ahci_dma");
if (IS_ERR(clk)) {
dev_err(dev, "no dma clock.\n");
ret = PTR_ERR(clk);
goto release_sata_ref_clk;
}
tmpdata = clk_get_rate(clk) / 1000;
clk_put(clk);
writel(tmpdata, addr + HOST_TIMER1MS);
tmpdata = readl(addr + HOST_CAP);
if (!(tmpdata & HOST_CAP_SSS)) {
tmpdata |= HOST_CAP_SSS;
writel(tmpdata, addr + HOST_CAP);
}
if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
addr + HOST_PORTS_IMPL);
return 0;
release_sata_ref_clk:
clk_disable_unprepare(sata_ref_clk);
put_sata_ref_clk:
clk_put(sata_ref_clk);
release_sata_clk:
clk_disable_unprepare(sata_clk);
put_sata_clk:
clk_put(sata_clk);
return ret;
}
static void imx_sata_exit(struct device *dev)
{
clk_disable_unprepare(sata_ref_clk);
clk_put(sata_ref_clk);
clk_disable_unprepare(sata_clk);
clk_put(sata_clk);
}
struct platform_device *__init imx_add_ahci_imx(
const struct imx_ahci_imx_data *data,
const struct ahci_platform_data *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask(data->devid, 0,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
struct platform_device *__init imx53_add_ahci_imx(void)
{
struct ahci_platform_data pdata = {
.init = imx_sata_init,
.exit = imx_sata_exit,
};
return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
}
arch/arm/mach-imx/hardware.h
View file @ a7726350
......@@ -102,7 +102,6 @@
#include "mxc.h"
#include "mx6q.h"
#include "mx51.h"
#include "mx53.h"
#include "mx3x.h"
......
arch/arm/mach-imx/mach-cpuimx51sd.c
View file @ a7726350
......@@ -33,7 +33,6 @@
#include "common.h"
#include "devices-imx51.h"
#include "cpu_op-mx51.h"
#include "eukrea-baseboards.h"
#include "hardware.h"
#include "iomux-mx51.h"
......@@ -285,10 +284,6 @@ static void __init eukrea_cpuimx51sd_init(void)
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
ARRAY_SIZE(eukrea_cpuimx51sd_pads));
#if defined(CONFIG_CPU_FREQ_IMX)
get_cpu_op = mx51_get_cpu_op;
#endif
imx51_add_imx_uart(0, &uart_pdata);
imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
imx51_add_imx2_wdt(0);
......
arch/arm/mach-imx/mach-imx6q.c
View file @ a7726350
......@@ -12,6 +12,7 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
......@@ -28,11 +29,9 @@
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <asm/smp_twd.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
#include "common.h"
......@@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void)
static void __init imx6q_timer_init(void)
{
mx6q_clocks_init();
twd_local_timer_of_register();
clocksource_of_init();
imx_print_silicon_rev("i.MX6Q", imx6q_revision());
}
......
arch/arm/mach-imx/mach-mx51_babbage.c
View file @ a7726350
......@@ -27,7 +27,6 @@
#include "common.h"
#include "devices-imx51.h"
#include "cpu_op-mx51.h"
#include "hardware.h"
#include "iomux-mx51.h"
......@@ -371,9 +370,6 @@ static void __init mx51_babbage_init(void)
imx51_soc_init();
#if defined(CONFIG_CPU_FREQ_IMX)
get_cpu_op = mx51_get_cpu_op;
#endif
imx51_babbage_common_init();
imx51_add_imx_uart(0, &uart_pdata);
......
arch/arm/mach-imx/mx6q.h deleted 100644 → 0
View file @ 4d26aa30
/*
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_MX6Q_H__
#define __MACH_MX6Q_H__
#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
/*
* The following are the blocks that need to be statically mapped.
* For other blocks, the base address really should be retrieved from
* device tree.
*/
#define MX6Q_SCU_BASE_ADDR 0x00a00000
#define MX6Q_SCU_SIZE 0x1000
#define MX6Q_CCM_BASE_ADDR 0x020c4000
#define MX6Q_CCM_SIZE 0x4000
#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
#define MX6Q_ANATOP_SIZE 0x1000
#endif /* __MACH_MX6Q_H__ */
arch/arm/mach-imx/platsmp.c
View file @ a7726350
......@@ -12,7 +12,6 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/page.h>
#include <asm/smp_scu.h>
#include <asm/mach/map.h>
......@@ -52,16 +51,6 @@ void imx_scu_standby_enable(void)
writel_relaxed(val, scu_base);
}
static void __cpuinit imx_secondary_init(unsigned int cpu)
{
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
}
static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
imx_set_cpu_jump(cpu, v7_secondary_startup);
......@@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
struct smp_operations imx_smp_ops __initdata = {
.smp_init_cpus = imx_smp_init_cpus,
.smp_prepare_cpus = imx_smp_prepare_cpus,
.smp_secondary_init = imx_secondary_init,
.smp_boot_secondary = imx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = imx_cpu_die,
......
arch/arm/mach-l7200/include/mach/debug-macro.S deleted 100644 → 0
View file @ 4d26aa30
/* arch/arm/mach-l7200/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
.equ io_virt, IO_BASE
.equ io_phys, IO_START
.macro addruart, rp, rv, tmp
mov \rp, #0x00044000 @ UART1
@ mov \rp, #0x00045000 @ UART2
add \rv, \rp, #io_virt @ virtual address
add \rp, \rp, #io_phys @ physical base address
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x0] @ UARTDR
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
bne 1001b
.endm
arch/arm/mach-msm/board-halibut.c
View file @ a7726350
......@@ -59,6 +59,7 @@ static struct platform_device smc91x_device = {
};
static struct platform_device *devices[] __initdata = {
&msm_device_gpio_7201,
&msm_device_uart3,
&msm_device_smd,
&msm_device_nand,
......
arch/arm/mach-msm/board-msm7x30.c
View file @ a7726350
......@@ -89,6 +89,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
};
static struct platform_device *devices[] __initdata = {
&msm_device_gpio_7x30,
#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
&msm_device_uart2,
#endif
......
arch/arm/mach-msm/board-qsd8x50.c
View file @ a7726350
......@@ -89,6 +89,7 @@ static struct msm_otg_platform_data msm_otg_pdata = {
};
static struct platform_device *devices[] __initdata = {
&msm_device_gpio_8x50,
&msm_device_uart3,
&msm_device_smd,
&msm_device_otg,
......
arch/arm/mach-msm/board-trout.c
View file @ a7726350
......@@ -36,6 +36,7 @@
extern int trout_init_mmc(unsigned int);
static struct platform_device *devices[] __initdata = {
&msm_device_gpio_7201,
&msm_device_uart3,
&msm_device_smd,
&msm_device_nand,
......
arch/arm/mach-msm/devices-msm7x00.c
View file @ a7726350
......@@ -29,6 +29,37 @@
#include "clock-pcom.h"
#include <linux/platform_data/mmc-msm_sdcc.h>
static struct resource msm_gpio_resources[] = {
{
.start = 32 + 0,
.end = 32 + 0,
.flags = IORESOURCE_IRQ,
},
{
.start = 32 + 1,
.end = 32 + 1,
.flags = IORESOURCE_IRQ,
},
{
.start = 0xa9200800,
.end = 0xa9200800 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio1"
},
{
.start = 0xa9300C00,
.end = 0xa9300C00 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio2"
},
};
struct platform_device msm_device_gpio_7201 = {
.name = "gpio-msm-7201",
.num_resources = ARRAY_SIZE(msm_gpio_resources),
.resource = msm_gpio_resources,
};
static struct resource resources_uart1[] = {
{
.start = INT_UART1,
......
arch/arm/mach-msm/devices-msm7x30.c
View file @ a7726350
......@@ -33,6 +33,37 @@
#include <linux/platform_data/mmc-msm_sdcc.h>
static struct resource msm_gpio_resources[] = {
{
.start = 32 + 18,
.end = 32 + 18,
.flags = IORESOURCE_IRQ,
},
{
.start = 32 + 19,
.end = 32 + 19,
.flags = IORESOURCE_IRQ,
},
{
.start = 0xac001000,
.end = 0xac001000 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio1"
},
{
.start = 0xac101400,
.end = 0xac101400 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio2"
},
};
struct platform_device msm_device_gpio_7x30 = {
.name = "gpio-msm-7x30",
.num_resources = ARRAY_SIZE(msm_gpio_resources),
.resource = msm_gpio_resources,
};
static struct resource resources_uart2[] = {
{
.start = INT_UART2,
......
arch/arm/mach-msm/devices-qsd8x50.c
View file @ a7726350
......@@ -30,6 +30,37 @@
#include <linux/platform_data/mmc-msm_sdcc.h>
#include "clock-pcom.h"
static struct resource msm_gpio_resources[] = {
{
.start = 64 + 165 + 9,
.end = 64 + 165 + 9,
.flags = IORESOURCE_IRQ,
},
{
.start = 64 + 165 + 10,
.end = 64 + 165 + 10,
.flags = IORESOURCE_IRQ,
},
{
.start = 0xa9000800,
.end = 0xa9000800 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio1"
},
{
.start = 0xa9100C00,
.end = 0xa9100C00 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio2"
},
};
struct platform_device msm_device_gpio_8x50 = {
.name = "gpio-msm-8x50",
.num_resources = ARRAY_SIZE(msm_gpio_resources),
.resource = msm_gpio_resources,
};
static struct resource resources_uart3[] = {
{
.start = INT_UART3,
......
arch/arm/mach-msm/devices.h
View file @ a7726350
......@@ -20,6 +20,10 @@
#include "clock.h"
extern struct platform_device msm_device_gpio_7201;
extern struct platform_device msm_device_gpio_7x30;
extern struct platform_device msm_device_gpio_8x50;
extern struct platform_device msm_device_uart1;
extern struct platform_device msm_device_uart2;
extern struct platform_device msm_device_uart3;
......
arch/arm/mach-msm/dma.c
View file @ a7726350
......@@ -19,9 +19,35 @@
#include <linux/interrupt.h>
#include <linux/completion.h>
#include <mach/dma.h>
#include <mach/msm_iomap.h>
#define MSM_DMOV_CHANNEL_COUNT 16
#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
#if defined(CONFIG_ARCH_MSM7X30)
#define DMOV_SD_AARM DMOV_SD2
#else
#define DMOV_SD_AARM DMOV_SD3
#endif
#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch)
#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch)
#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch)
#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch)
#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch)
#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch)
#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch)
#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch)
#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch)
#define DMOV_ISR DMOV_SD_AARM(0x380, 0)
#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch)
enum {
MSM_DMOV_PRINT_ERRORS = 1,
MSM_DMOV_PRINT_IO = 2,
......
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