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Commit a9533e7e authored by Henry Ptasinski's avatar Henry Ptasinski Committed by Greg Kroah-Hartman
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Staging: Add initial release of brcm80211 - Broadcom 802.11n wireless LAN driver. 

Signed-off-by: default avatarHenry Ptasinski <henryp@broadcom.com>
Cc: Brett Rudley <brudley@broadcom.com>
Cc: Nohee Ko <noheek@broadcom.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent baa5251e
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MAINTAINERS
View file @ a9533e7e
......@@ -1392,6 +1392,14 @@ L: netdev@vger.kernel.org
S: Supported
F: drivers/net/tg3.*
BROADCOM BRCM80211 IEEE802.11n WIRELESS DRIVER
M: Brett Rudley <brudley@broadcom.com>
M: Henry Ptasinski <henryp@broadcom.com>
M: Nohee Ko <noheek@broadcom.com>
L: linux-wireless@vger.kernel.org
S: Supported
F: drivers/staging/brcm80211/
BROCADE BFA FC SCSI DRIVER
M: Jing Huang <huangj@brocade.com>
L: linux-scsi@vger.kernel.org
......
drivers/staging/Kconfig
View file @ a9533e7e
......@@ -61,6 +61,8 @@ source "drivers/staging/echo/Kconfig"
source "drivers/staging/otus/Kconfig"
source "drivers/staging/brcm80211/Kconfig"
source "drivers/staging/rt2860/Kconfig"
source "drivers/staging/rt2870/Kconfig"
......
drivers/staging/Makefile
View file @ a9533e7e
......@@ -14,6 +14,7 @@ obj-$(CONFIG_W35UND) += winbond/
obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_OTUS) += otus/
obj-$(CONFIG_BRCM80211)) += brcm80211/
obj-$(CONFIG_RT2860) += rt2860/
obj-$(CONFIG_RT2870) += rt2870/
obj-$(CONFIG_COMEDI) += comedi/
......
drivers/staging/brcm80211/Kconfig 0 → 100644
View file @ a9533e7e
menuconfig BRCM80211
tristate "Broadcom 802.11 WLAN driver for bcm43xx chips"
depends on PCI && WLAN
select WIRELESS_EXT
select WEXT_PRIV
default N
help
If built as a module, it will be called brcm80211.ko.
config BRCM80211_PCI
bool "Broadcom 802.11 WLAN NIC driver"
depends on BRCM80211
default y
drivers/staging/brcm80211/Makefile 0 → 100644
View file @ a9533e7e
#
# Makefile fragment for Broadcom 802.11n Networking Device Driver
#
# Copyright (c) 2010 Broadcom Corporation
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
EXTRA_CFLAGS := -DBCMDBG -DWLC_HIGH -DSTA -DWME -DWL11N -DDBAND -DBCMDMA32 -DBCMNVRAMR -Idrivers/staging/brcm80211/sys -Idrivers/staging/brcm80211/phy -Idrivers/staging/brcm80211/util -Idrivers/staging/brcm80211/include -Wall -Wstrict-prototypes -Werror -Wmissing-prototypes
PCI_CFLAGS := -DWLC_LOW
BRCM80211_OFILES := \
util/siutils.o \
util/aiutils.o \
util/bcmotp.o \
util/bcmsrom.o \
util/bcmutils.o \
util/bcmwifi.o \
util/bcmwpa.o \
util/hndpmu.o \
util/linux_osl.o \
sys/wlc_alloc.o \
sys/wlc_antsel.o \
sys/wlc_channel.o \
sys/wlc_event.o \
sys/wlc_mac80211.o \
sys/wlc_rate.o \
sys/wlc_stf.o \
sys/wl_mac80211.o \
sys/wlc_ampdu.o
PCIFILES := \
phy/wlc_phy_cmn.o \
phy/wlc_phy_lcn.o \
phy/wlc_phy_n.o \
phy/wlc_phytbl_lcn.o \
phy/wlc_phytbl_n.o \
sys/wlc_bmac.o \
sys/wlc_phy_shim.o \
sys/wl_ucode_loader.o \
util/hnddma.o \
util/nicpci.o \
util/nvram/nvram_ro.o \
util/qmath.o
MODULEPFX := brcm80211
obj-m += $(MODULEPFX).o
# PCI driver
ifeq ($(CONFIG_BRCM80211_PCI),y)
EXTRA_CFLAGS += $(PCI_CFLAGS)
$(MODULEPFX)-objs = $(BRCM80211_OFILES) $(PCIFILES)
endif
drivers/staging/brcm80211/README 0 → 100644
View file @ a9533e7e
Broadcom Mac80211 driver
This is a driver in progress. It has features still to be implemented well as
bugs in current code.
What's here and not here
=======================
- Completely open source host driver, no binary object files
- Features Broadcom's OneDriver architecture (single source base for
supported chips and architectures)
- On-chip firmware loaded using standard request_firmware()
- Support for BCM43224, BCM43225, BCM4313 (PCIe NIC)
- Framework for supporting new chips, including mac80211-aware embedded chips
- Does not support older PCI/PCIe chips with SSB backplane
- Driver includes BMAC interface for transparent dongle support
- Uses minstrel_ht rate algorithm
- HW based encryption not enabled yet
What's done
==========
- Integration with mac80211 stack
- A-MPDU single & dual stream rates
- BCM43224: Dualband, Dual stream, 20MHz channels
Throughput (in chamber): ~85-90 Mbits/sec (in both 2.4 & 5 GHz bands)
- BCM43225: 2.4 GHz, Dual Stream, 20MHz channels
Throughput (in chamber): ~85-90 Mbits/sec
- BCM4313: 2.4 GHz, Single Stream
Throughput (in chamber): ~40 Mbits/sec
Things To Be Done
=================
See the TODO file
Firmware installation
======================
Firmware is available from the Linux firmware repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
http://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
https://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
For all chips, copy brcm/bcm43xx-0-610-809-0.fw and
brcm/bcm43xx_hdr-0-610-809-0.fw to /lib/firmware/brcm (or wherever firmware is
normally installed on the system). In the /lib/firmware/brcm directory, then
create the following symlinks:
ln -s bcm43xx-0-610-809-0.fw bcm43xx-0.fw
ln -s bcm43xx_hdr-0-610-809-0.fw bcm43xx_hdr-0.fw
Currently supported chips
==============
PCI
Name Device ID
BCM4313 0x4727
BCM43224 0x4353
BCM43225 0x4357
Bugs/Problems
==============
- Driver can get confused while scanning during high throughput, can cause
burping, hanging, and possible crashing.
- Occasional hangs & burps with BCM43224 on 2.4 GHz with dual stream rates.
- Occasional crashes with BCM43224 on multicore machines.
Note on Regulatory Implementation
================================
This generation of chips contain additional regulatory support independent of
the driver. The devices use a single worldwide regulatory domain, with channels
12-14 (2.4 GHz band) and channels 52-64 and 100-140 (5 GHz band) restricted to
passive operation. Transmission on those channels is suppressed until
appropriate other traffic is observed on those channels.
Within the driver, we use the ficticious country code "X2" to represent this
worldwide regulatory domain. There is currently no interface to configure a
different domain.
The driver reads the SROM country code from the chip and hands it up to
mac80211 as the regulatory hint, however this information is otherwise unused
with the driver.
Contact Info:
=============
Brett Rudley brudley@broadcom.com
Henry Ptasinski henryp@broadcom.com
Nohee Ko noheek@broadcom.com
drivers/staging/brcm80211/TODO 0 → 100644
View file @ a9533e7e
To Do List for Broadcom Mac80211 driver
Features to be added
=====================
- 40 MHz channels
- Power Save
- AP
- IBSS
- HW-based encryption
- LED support
- RFKILL
- Debugfs and debugability
Code cleanup
============
- Use proper kernel coding standards
- Remove overlap with system header files. (ie much of include/proto/*.h should
be removed)
- Purge unused variables/data structs/functions BUT keep code related to
features that are being added (ie AP mode, 40 Mhz channels, IBSS etc).
- Replace proprietary utility functions with public kernel versions.
Bugs
====
- Various occasional asserts/hangs
- Scanning during data transfer sometimes causes major slowdowns. Sometimes
revcovers when scan is done, other times not.
- Driver does not handle missing firmware gracefully.
- Mac80211 API not completely implemented (ie ops_bss_info_changed,
ops_get_stats, etc)
Other
=====
- wlc_mac80211.[ch], wl_mac80211.[ch] and linux_osl.c all need to be refactored
and combined.
- Replace driver's proprietary ssb interface with generic kernel ssb module
(only used when compiling for SDIO).
- PCI and SDIO support are currently #ifdef'ed exclusive of each other, which
leads to a separate wl.ko for each. This should be changed to runtime
handling of different interfaces so that a single binary driver can be built.
- Add support for new chips (obviously an ongoing item).
drivers/staging/brcm80211/include/aidmp.h 0 → 100644
View file @ a9533e7e
This diff is collapsed.
drivers/staging/brcm80211/include/bcm_rpc.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCM_RPC_H_
#define _BCM_RPC_H_
#include <typedefs.h>
#include <rpc_osl.h>
typedef struct rpc_info rpc_info_t;
typedef struct rpc_buf rpc_buf_t;
struct rpc_transport_info;
typedef void (*rpc_dispatch_cb_t) (void *ctx, struct rpc_buf * buf);
typedef void (*rpc_resync_cb_t) (void *ctx);
typedef void (*rpc_down_cb_t) (void *ctx);
typedef void (*rpc_txdone_cb_t) (void *ctx, struct rpc_buf * buf);
extern struct rpc_info *bcm_rpc_attach(void *pdev, osl_t * osh,
struct rpc_transport_info *rpc_th);
extern void bcm_rpc_detach(struct rpc_info *rpc);
extern void bcm_rpc_down(struct rpc_info *rpc);
extern void bcm_rpc_watchdog(struct rpc_info *rpc);
extern struct rpc_buf *bcm_rpc_buf_alloc(struct rpc_info *rpc, int len);
extern void bcm_rpc_buf_free(struct rpc_info *rpc, struct rpc_buf *b);
/* get rpc transport handle */
extern struct rpc_transport_info *bcm_rpc_tp_get(struct rpc_info *rpc);
/* callback for: data_rx, down, resync */
extern void bcm_rpc_rxcb_init(struct rpc_info *rpc, void *ctx,
rpc_dispatch_cb_t cb, void *dnctx,
rpc_down_cb_t dncb, rpc_resync_cb_t resync_cb,
rpc_txdone_cb_t);
extern void bcm_rpc_rxcb_deinit(struct rpc_info *rpci);
/* HOST or CLIENT rpc call, requiring no return value */
extern int bcm_rpc_call(struct rpc_info *rpc, struct rpc_buf *b);
/* HOST rpc call, demanding return.
* The thread may be suspended and control returns back to OS
* The thread will resume(waked up) on either the return signal received or timeout
* The implementation details depend on OS
*/
extern struct rpc_buf *bcm_rpc_call_with_return(struct rpc_info *rpc,
struct rpc_buf *b);
/* CLIENT rpc call to respond to bcm_rpc_call_with_return, requiring no return value */
extern int bcm_rpc_call_return(struct rpc_info *rpc, struct rpc_buf *retb);
extern uint bcm_rpc_buf_header_len(struct rpc_info *rpci);
#define RPC_PKTLOG_SIZE 50 /* Depth of the history */
#define RPC_PKTLOG_RD_LEN 3
#define RPC_PKTLOG_DUMP_SIZE 150 /* dump size should be more than the product of above two */
extern int bcm_rpc_pktlog_get(struct rpc_info *rpci, uint32 * buf,
uint buf_size, bool send);
extern int bcm_rpc_dump(rpc_info_t * rpci, struct bcmstrbuf *b);
/* HIGH/BMAC: bit 15-8: RPC module, bit 7-0: TP module */
#define RPC_ERROR_VAL 0x0001
#define RPC_TRACE_VAL 0x0002
#define RPC_PKTTRACE_VAL 0x0004
#define RPC_PKTLOG_VAL 0x0008
extern void bcm_rpc_msglevel_set(struct rpc_info *rpci, uint16 msglevel,
bool high_low);
#endif /* _BCM_RPC_H_ */
drivers/staging/brcm80211/include/bcm_rpc_tp.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcm_rpc_tp_h_
#define _bcm_rpc_tp_h_
#include <bcm_rpc.h>
#define DBUS_RX_BUFFER_SIZE_RPC (2100) /* rxbufsize for dbus_attach, linux only for now */
#define BCM_RPC_TP_ENCAP_LEN 4 /* TP header is 4 bytes */
#define BCM_RPC_TP_HOST_AGG_MASK 0xffff0000
#define BCM_RPC_TP_HOST_AGG_SHIFT 16
#define BCM_RPC_TP_HOST_AGG_AMPDU 0x00010000 /* HOST->DNGL ampdu aggregation */
#define BCM_RPC_TP_HOST_AGG_TEST 0x00100000 /* HOST->DNGL test aggregation */
#define BCM_RPC_TP_DNGL_AGG_MASK 0x0000ffff
#define BCM_RPC_TP_DNGL_AGG_DPC 0x00000001 /* DNGL->HOST data aggregation */
#define BCM_RPC_TP_DNGL_AGG_FLOWCTL 0x00000002 /* DNGL->HOST tx flowcontrol agg */
#define BCM_RPC_TP_DNGL_AGG_TEST 0x00000010 /* DNGL->HOST test agg */
#define BCM_RPC_TP_DNGL_AGG_MAX_SFRAME 3 /* max agg subframes, must be <= USB_NTXD */
#define BCM_RPC_TP_DNGL_AGG_MAX_BYTE 4000 /* max agg bytes */
#define BCM_RPC_TP_HOST_AGG_MAX_SFRAME 3 /* max agg subframes, AMPDU only, 3 is enough */
#define BCM_RPC_TP_HOST_AGG_MAX_BYTE 3400 /* max agg bytes; to fit 2+ tcp/udp pkts. Each one:
* 802.3pkt + 802.11 hdr + rpc hdr + tp hdr < 1700B
* Need to be in sync with dongle usb rx dma
* rxbufsize(USBBULK_RXBUF_GIANT in usbdev_sb.c)
*/
/* TP-DBUS pkts flowcontrol */
#define BCM_RPC_TP_DBUS_NTXQ 50 /* queue size for TX on bulk OUT, aggregation possible */
#define BCM_RPC_TP_DBUS_NRXQ 50 /* queue size for RX on bulk IN, aggregation possible */
#define BCM_RPC_TP_DBUS_NRXQ_CTRL 1 /* queue size for RX on ctl EP0 */
#define BCM_RPC_TP_DBUS_NRXQ_PKT (BCM_RPC_TP_DBUS_NRXQ * BCM_RPC_TP_DNGL_AGG_MAX_SFRAME)
#define BCM_RPC_TP_DBUS_NTXQ_PKT (BCM_RPC_TP_DBUS_NTXQ * BCM_RPC_TP_HOST_AGG_MAX_SFRAME)
typedef struct rpc_transport_info rpc_tp_info_t;
typedef void (*rpc_tx_complete_fn_t) (void *, rpc_buf_t *, int status);
typedef void (*rpc_rx_fn_t) (void *, rpc_buf_t *);
#ifdef WLC_LOW
typedef void (*rpc_txflowctl_cb_t) (void *ctx, bool on);
#endif
extern rpc_tp_info_t *bcm_rpc_tp_attach(osl_t * osh, void *bus);
extern void bcm_rpc_tp_detach(rpc_tp_info_t * rpcb);
extern void bcm_rpc_tp_down(rpc_tp_info_t * rpcb);
extern void bcm_rpc_tp_watchdog(rpc_tp_info_t * rpcb);
extern int bcm_rpc_tp_buf_send(rpc_tp_info_t * rpcb, rpc_buf_t * buf);
/* callback for tx_complete, rx_pkt */
extern void bcm_rpc_tp_register_cb(rpc_tp_info_t * rpcb,
rpc_tx_complete_fn_t txcmplt,
void *tx_context, rpc_rx_fn_t rxpkt,
void *rx_context, rpc_osl_t * rpc_osh);
extern void bcm_rpc_tp_deregister_cb(rpc_tp_info_t * rpcb);
/* Buffer manipulation */
extern uint bcm_rpc_buf_tp_header_len(rpc_tp_info_t * rpcb);
extern rpc_buf_t *bcm_rpc_tp_buf_alloc(rpc_tp_info_t * rpcb, int len);
extern void bcm_rpc_tp_buf_free(rpc_tp_info_t * rpcb, rpc_buf_t * buf);
extern int bcm_rpc_buf_len_get(rpc_tp_info_t * rpcb, rpc_buf_t * b);
extern int bcm_rpc_buf_len_set(rpc_tp_info_t * rpcb, rpc_buf_t * b, uint len);
extern rpc_buf_t *bcm_rpc_buf_next_get(rpc_tp_info_t * rpcb, rpc_buf_t * b);
extern void bcm_rpc_buf_next_set(rpc_tp_info_t * rpcb, rpc_buf_t * b,
rpc_buf_t * nextb);
extern unsigned char *bcm_rpc_buf_data(rpc_tp_info_t * rpcb, rpc_buf_t * b);
extern unsigned char *bcm_rpc_buf_push(rpc_tp_info_t * rpcb, rpc_buf_t * b,
uint delta);
extern unsigned char *bcm_rpc_buf_pull(rpc_tp_info_t * rpcb, rpc_buf_t * b,
uint delta);
extern void bcm_rpc_tp_buf_release(rpc_tp_info_t * rpcb, rpc_buf_t * buf);
extern void bcm_rpc_tp_buf_cnt_adjust(rpc_tp_info_t * rpcb, int adjust);
/* RPC call_with_return */
extern int bcm_rpc_tp_recv_rtn(rpc_tp_info_t * rpcb);
extern int bcm_rpc_tp_get_device_speed(rpc_tp_info_t * rpc_th);
#ifdef BCMDBG
extern int bcm_rpc_tp_dump(rpc_tp_info_t * rpcb, struct bcmstrbuf *b);
#endif
#ifdef WLC_LOW
/* intercept USB pkt to parse RPC header: USB driver rx-> wl_send -> this -> wl driver */
extern void bcm_rpc_tp_rx_from_dnglbus(rpc_tp_info_t * rpc_th, struct lbuf *lb);
/* RPC callreturn pkt, go to USB driver tx */
extern int bcm_rpc_tp_send_callreturn(rpc_tp_info_t * rpc_th, rpc_buf_t * b);
extern void bcm_rpc_tp_dump(rpc_tp_info_t * rpcb);
extern void bcm_rpc_tp_txflowctl(rpc_tp_info_t * rpcb, bool state, int prio);
extern void bcm_rpc_tp_txflowctlcb_init(rpc_tp_info_t * rpc_th, void *ctx,
rpc_txflowctl_cb_t cb);
extern void bcm_rpc_tp_txflowctlcb_deinit(rpc_tp_info_t * rpc_th);
extern void bcm_rpc_tp_txq_wm_set(rpc_tp_info_t * rpc_th, uint8 hiwm,
uint8 lowm);
extern void bcm_rpc_tp_txq_wm_get(rpc_tp_info_t * rpc_th, uint8 * hiwm,
uint8 * lowm);
#endif /* WLC_LOW */
extern void bcm_rpc_tp_agg_set(rpc_tp_info_t * rpcb, uint32 reason, bool set);
extern void bcm_rpc_tp_agg_limit_set(rpc_tp_info_t * rpc_th, uint8 sf,
uint16 bytes);
extern void bcm_rpc_tp_agg_limit_get(rpc_tp_info_t * rpc_th, uint8 * sf,
uint16 * bytes);
#define BCM_RPC_TP_MSG_LEVEL_MASK 0x00ff
/* dongle msg level */
#define RPC_TP_MSG_DNGL_ERR_VAL 0x0001 /* DNGL TP error msg */
#define RPC_TP_MSG_DNGL_DBG_VAL 0x0002 /* DNGL TP dbg msg */
#define RPC_TP_MSG_DNGL_AGG_VAL 0x0004 /* DNGL TP agg msg */
#define RPC_TP_MSG_DNGL_DEA_VAL 0x0008 /* DNGL TP deag msg */
/* host msg level */
#define RPC_TP_MSG_HOST_ERR_VAL 0x0001 /* DNGL TP error msg */
#define RPC_TP_MSG_HOST_DBG_VAL 0x0002 /* DNGL TP dbg msg */
#define RPC_TP_MSG_HOST_AGG_VAL 0x0004 /* DNGL TP agg msg */
#define RPC_TP_MSG_HOST_DEA_VAL 0x0008 /* DNGL TP deag msg */
extern void bcm_rpc_tp_msglevel_set(rpc_tp_info_t * rpc_th, uint8 msglevel,
bool high_low);
#endif /* _bcm_rpc_tp_h_ */
drivers/staging/brcm80211/include/bcm_xdr.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCM_XDR_H
#define _BCM_XDR_H
/*
* bcm_xdr_buf_t
* Structure used for bookkeeping of a buffer being packed or unpacked.
* Keeps a current read/write pointer and size as well as
* the original buffer pointer and size.
*
*/
typedef struct {
uint8 *buf; /* pointer to current position in origbuf */
uint size; /* current (residual) size in bytes */
uint8 *origbuf; /* unmodified pointer to orignal buffer */
uint origsize; /* unmodified orignal buffer size in bytes */
} bcm_xdr_buf_t;
void bcm_xdr_buf_init(bcm_xdr_buf_t * b, void *buf, size_t len);
int bcm_xdr_pack_uint32(bcm_xdr_buf_t * b, uint32 val);
int bcm_xdr_unpack_uint32(bcm_xdr_buf_t * b, uint32 * pval);
int bcm_xdr_pack_int32(bcm_xdr_buf_t * b, int32 val);
int bcm_xdr_unpack_int32(bcm_xdr_buf_t * b, int32 * pval);
int bcm_xdr_pack_int8(bcm_xdr_buf_t * b, int8 val);
int bcm_xdr_unpack_int8(bcm_xdr_buf_t * b, int8 * pval);
int bcm_xdr_pack_opaque(bcm_xdr_buf_t * b, uint len, void *data);
int bcm_xdr_unpack_opaque(bcm_xdr_buf_t * b, uint len, void **pdata);
int bcm_xdr_unpack_opaque_cpy(bcm_xdr_buf_t * b, uint len, void *data);
int bcm_xdr_pack_opaque_varlen(bcm_xdr_buf_t * b, uint len, void *data);
int bcm_xdr_unpack_opaque_varlen(bcm_xdr_buf_t * b, uint * plen, void **pdata);
int bcm_xdr_pack_string(bcm_xdr_buf_t * b, char *str);
int bcm_xdr_unpack_string(bcm_xdr_buf_t * b, uint * plen, char **pstr);
int bcm_xdr_pack_uint8_vec(bcm_xdr_buf_t *, uint8 * vec, uint32 elems);
int bcm_xdr_unpack_uint8_vec(bcm_xdr_buf_t *, uint8 * vec, uint32 elems);
int bcm_xdr_pack_uint16_vec(bcm_xdr_buf_t * b, uint len, void *vec);
int bcm_xdr_unpack_uint16_vec(bcm_xdr_buf_t * b, uint len, void *vec);
int bcm_xdr_pack_uint32_vec(bcm_xdr_buf_t * b, uint len, void *vec);
int bcm_xdr_unpack_uint32_vec(bcm_xdr_buf_t * b, uint len, void *vec);
int bcm_xdr_pack_opaque_raw(bcm_xdr_buf_t * b, uint len, void *data);
int bcm_xdr_pack_opaque_pad(bcm_xdr_buf_t * b);
#endif /* _BCM_XDR_H */
drivers/staging/brcm80211/include/bcmdefs.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmdefs_h_
#define _bcmdefs_h_
/*
* One doesn't need to include this file explicitly, gets included automatically if
* typedefs.h is included.
*/
/* Use BCM_REFERENCE to suppress warnings about intentionally-unused function
* arguments or local variables.
*/
#define BCM_REFERENCE(data) ((void)data)
/* Reclaiming text and data :
* The following macros specify special linker sections that can be reclaimed
* after a system is considered 'up'.
* BCMATTACHFN is also used for detach functions (it's not worth having a BCMDETACHFN,
* as in most cases, the attach function calls the detach function to clean up on error).
*/
#define bcmreclaimed 0
#define BCMATTACHDATA(_data) _data
#define BCMATTACHFN(_fn) _fn
#define BCMPREATTACHDATA(_data) _data
#define BCMPREATTACHFN(_fn) _fn
#define BCMINITDATA(_data) _data
#define BCMINITFN(_fn) _fn
#define BCMUNINITFN(_fn) _fn
#define BCMNMIATTACHFN(_fn) _fn
#define BCMNMIATTACHDATA(_data) _data
#define BCMOVERLAY0DATA(_sym) _sym
#define BCMOVERLAY0FN(_fn) _fn
#define BCMOVERLAY1DATA(_sym) _sym
#define BCMOVERLAY1FN(_fn) _fn
#define BCMOVERLAYERRFN(_fn) _fn
#define CONST const
#ifdef mips
#define BCMFASTPATH __attribute__ ((__section__(".text.fastpath")))
#else
#define BCMFASTPATH
#endif
/* Put some library data/code into ROM to reduce RAM requirements */
#define BCMROMDATA(_data) _data
#define BCMROMDAT_NAME(_data) _data
#define BCMROMFN(_fn) _fn
#define BCMROMFN_NAME(_fn) _fn
#define STATIC static
#define BCMROMDAT_ARYSIZ(data) ARRAYSIZE(data)
#define BCMROMDAT_SIZEOF(data) sizeof(data)
#define BCMROMDAT_APATCH(data)
#define BCMROMDAT_SPATCH(data)
/* Bus types */
#define SI_BUS 0 /* SOC Interconnect */
#define PCI_BUS 1 /* PCI target */
#define SDIO_BUS 3 /* SDIO target */
#define JTAG_BUS 4 /* JTAG */
#define USB_BUS 5 /* USB (does not support R/W REG) */
#define SPI_BUS 6 /* gSPI target */
#define RPC_BUS 7 /* RPC target */
/* Allows size optimization for single-bus image */
#ifdef BCMBUSTYPE
#define BUSTYPE(bus) (BCMBUSTYPE)
#else
#define BUSTYPE(bus) (bus)
#endif
/* Allows size optimization for single-backplane image */
#ifdef BCMCHIPTYPE
#define CHIPTYPE(bus) (BCMCHIPTYPE)
#else
#define CHIPTYPE(bus) (bus)
#endif
/* Allows size optimization for SPROM support */
#define SPROMBUS (PCI_BUS)
/* Allows size optimization for single-chip image */
#ifdef BCMCHIPID
#define CHIPID(chip) (BCMCHIPID)
#else
#define CHIPID(chip) (chip)
#endif
#ifdef BCMCHIPREV
#define CHIPREV(rev) (BCMCHIPREV)
#else
#define CHIPREV(rev) (rev)
#endif
/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
#ifdef BCMDMA64OSL
typedef struct {
uint32 loaddr;
uint32 hiaddr;
} dma64addr_t;
typedef dma64addr_t dmaaddr_t;
#define PHYSADDRHI(_pa) ((_pa).hiaddr)
#define PHYSADDRHISET(_pa, _val) \
do { \
(_pa).hiaddr = (_val); \
} while (0)
#define PHYSADDRLO(_pa) ((_pa).loaddr)
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa).loaddr = (_val); \
} while (0)
#else
typedef unsigned long dmaaddr_t;
#define PHYSADDRHI(_pa) (0)
#define PHYSADDRHISET(_pa, _val)
#define PHYSADDRLO(_pa) ((_pa))
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa) = (_val); \
} while (0)
#endif /* BCMDMA64OSL */
/* One physical DMA segment */
typedef struct {
dmaaddr_t addr;
uint32 length;
} hnddma_seg_t;
#define MAX_DMA_SEGS 4
typedef struct {
void *oshdmah; /* Opaque handle for OSL to store its information */
uint origsize; /* Size of the virtual packet */
uint nsegs;
hnddma_seg_t segs[MAX_DMA_SEGS];
} hnddma_seg_map_t;
/* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
* By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
* There is a compile time check in wlc.c which ensure that this value is at least as big
* as TXOFF. This value is used in dma_rxfill (hnddma.c).
*/
#define BCMEXTRAHDROOM 172
/* Headroom required for dongle-to-host communication. Packets allocated
* locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
* leave this much room in front for low-level message headers which may
* be needed to get across the dongle bus to the host. (These messages
* don't go over the network, so room for the full WL header above would
* be a waste.).
*/
#define BCMDONGLEHDRSZ 12
#define BCMDONGLEPADSZ 16
#define BCMDONGLEOVERHEAD (BCMDONGLEHDRSZ + BCMDONGLEPADSZ)
#ifdef BCMDBG
#define BCMDBG_ERR
#ifndef BCMDBG_ASSERT
#define BCMDBG_ASSERT
#endif /* BCMDBG_ASSERT */
#endif /* BCMDBG */
#if defined(BCMDBG_ASSERT)
#define BCMASSERT_SUPPORT
#endif
/* Macros for doing definition and get/set of bitfields
* Usage example, e.g. a three-bit field (bits 4-6):
* #define <NAME>_M BITFIELD_MASK(3)
* #define <NAME>_S 4
* ...
* regval = R_REG(osh, &regs->regfoo);
* field = GFIELD(regval, <NAME>);
* regval = SFIELD(regval, <NAME>, 1);
* W_REG(osh, &regs->regfoo, regval);
*/
#define BITFIELD_MASK(width) \
(((unsigned)1 << (width)) - 1)
#define GFIELD(val, field) \
(((val) >> field ## _S) & field ## _M)
#define SFIELD(val, field, bits) \
(((val) & (~(field ## _M << field ## _S))) | \
((unsigned)(bits) << field ## _S))
/* define BCMSMALL to remove misc features for memory-constrained environments */
#define BCMSPACE
#define bcmspace TRUE /* if (bcmspace) code is retained */
/* Max. nvram variable table size */
#define MAXSZ_NVRAM_VARS 4096
#define LOCATOR_EXTERN static
#endif /* _bcmdefs_h_ */
drivers/staging/brcm80211/include/bcmdevs.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCMDEVS_H
#define _BCMDEVS_H
/* PCI vendor IDs */
#define VENDOR_BROADCOM 0x14e4
/* DONGLE VID/PIDs */
#define BCM_DNGL_VID 0x0a5c
#define BCM_DNGL_BDC_PID 0x0bdc
#define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */
#define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
#define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
#define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
#define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
#define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
#define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
#define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
#define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
#define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */
#define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */
#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
#define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */
#define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */
#define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */
#define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */
#define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */
#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
#define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */
#define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */
/* Chip IDs */
#define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
#define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
#define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
#define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
#define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */
#define BCM43421_CHIP_ID 43421 /* 43421 chipcommon chipid */
#define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
#define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
#define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
#define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
#define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
#define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
#define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
#define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
/* these are router chips */
#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
#define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
#define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
/* Package IDs */
#define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
#define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
#define BCM4716_PKG_ID 8 /* 4716 package id */
#define BCM4717_PKG_ID 9 /* 4717 package id */
#define BCM4718_PKG_ID 10 /* 4718 package id */
#define BCM5356_PKG_NONMODE 1 /* 5356 package without nmode suppport */
#define BCM5358U_PKG_ID 8 /* 5358U package id */
#define BCM5358_PKG_ID 9 /* 5358 package id */
#define BCM47186_PKG_ID 10 /* 47186 package id */
#define BCM5357_PKG_ID 11 /* 5357 package id */
#define BCM5356U_PKG_ID 12 /* 5356U package id */
#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
#define BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */
#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
#define BCM4336_WLBGA_PKG_ID 0x8
/* boardflags */
#define BFL_RESERVED1 0x00000001
#define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
#define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication */
#define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */
#define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */
#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
#define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
#define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */
#define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */
#define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
#define BFL_FEM 0x00000800 /* Board supports the Front End Module */
#define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
#define BFL_HGPA 0x00002000 /* Board has a high gain PA */
#define BFL_RESERVED2 0x00004000
#define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
#define BFL_NOPA 0x00010000 /* Board has no PA */
#define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */
#define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */
#define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */
#define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */
#define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
#define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
#define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
#define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */
#define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
#define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */
#define BFL_FASTPWR 0x08000000
#define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */
#define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
#define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */
#define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */
#define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field
* when this flag is set
*/
/* boardflags2 */
#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
#define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
#define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
#define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
#define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
#define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
#define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */
#define BFL2_LEGACY 0x00000080
#define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
#define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
#define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
#define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
#define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
#define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
#define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */
#define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* using 40Mhz LPF for 20Mhz bandedge channels */
#define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
#define BFL2_IPALVLSHIFT_3P3 0x00020000
#define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
#define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio "ON"
* Most drivers will turn it off without this flag
* to save power.
*/
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
#define BOARD_GPIO_RESERVED1 0x010
#define BOARD_GPIO_RESERVED2 0x020
#define BOARD_GPIO_RESERVED3 0x080
#define BOARD_GPIO_RESERVED4 0x100
#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
#define BOARD_GPIO_12 0x1000 /* gpio 12 */
#define BOARD_GPIO_13 0x2000 /* gpio 13 */
#define BOARD_GPIO_RESERVED5 0x0800
#define BOARD_GPIO_RESERVED6 0x2000
#define BOARD_GPIO_RESERVED7 0x4000
#define BOARD_GPIO_RESERVED8 0x8000
#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
/* power control defines */
#define PLL_DELAY 150 /* us pll on delay */
#define FREF_DELAY 200 /* us fref change delay */
#define MIN_SLOW_CLK 32 /* us Slow clock period */
#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
/* # of GPIO pins */
#define GPIO_NUMPINS 16
/* Reference board types */
#define SPI_BOARD 0x0402
#endif /* _BCMDEVS_H */
drivers/staging/brcm80211/include/bcmendian.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCMENDIAN_H_
#define _BCMENDIAN_H_
#include <typedefs.h>
/* Reverse the bytes in a 16-bit value */
#define BCMSWAP16(val) \
((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \
(((uint16)(val) & (uint16)0xff00U) >> 8)))
/* Reverse the bytes in a 32-bit value */
#define BCMSWAP32(val) \
((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
(((uint32)(val) & (uint32)0x0000ff00U) << 8) | \
(((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \
(((uint32)(val) & (uint32)0xff000000U) >> 24)))
/* Reverse the two 16-bit halves of a 32-bit value */
#define BCMSWAP32BY16(val) \
((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \
(((uint32)(val) & (uint32)0xffff0000U) >> 16)))
/* Byte swapping macros
* Host <=> Network (Big Endian) for 16- and 32-bit values
* Host <=> Little-Endian for 16- and 32-bit values
*/
#ifndef hton16
#ifndef IL_BIGENDIAN
#define HTON16(i) BCMSWAP16(i)
#define hton16(i) bcmswap16(i)
#define HTON32(i) BCMSWAP32(i)
#define hton32(i) bcmswap32(i)
#define NTOH16(i) BCMSWAP16(i)
#define ntoh16(i) bcmswap16(i)
#define NTOH32(i) BCMSWAP32(i)
#define ntoh32(i) bcmswap32(i)
#define LTOH16(i) (i)
#define ltoh16(i) (i)
#define LTOH32(i) (i)
#define ltoh32(i) (i)
#define HTOL16(i) (i)
#define htol16(i) (i)
#define HTOL32(i) (i)
#define htol32(i) (i)
#else /* IL_BIGENDIAN */
#define HTON16(i) (i)
#define hton16(i) (i)
#define HTON32(i) (i)
#define hton32(i) (i)
#define NTOH16(i) (i)
#define ntoh16(i) (i)
#define NTOH32(i) (i)
#define ntoh32(i) (i)
#define LTOH16(i) BCMSWAP16(i)
#define ltoh16(i) bcmswap16(i)
#define LTOH32(i) BCMSWAP32(i)
#define ltoh32(i) bcmswap32(i)
#define HTOL16(i) BCMSWAP16(i)
#define htol16(i) bcmswap16(i)
#define HTOL32(i) BCMSWAP32(i)
#define htol32(i) bcmswap32(i)
#endif /* IL_BIGENDIAN */
#endif /* hton16 */
#ifndef IL_BIGENDIAN
#define ltoh16_buf(buf, i)
#define htol16_buf(buf, i)
#else
#define ltoh16_buf(buf, i) bcmswap16_buf((uint16 *)(buf), (i))
#define htol16_buf(buf, i) bcmswap16_buf((uint16 *)(buf), (i))
#endif /* IL_BIGENDIAN */
/* Unaligned loads and stores in host byte order */
#ifndef IL_BIGENDIAN
#define load32_ua(a) ltoh32_ua(a)
#define store32_ua(a, v) htol32_ua_store(v, a)
#define load16_ua(a) ltoh16_ua(a)
#define store16_ua(a, v) htol16_ua_store(v, a)
#else
#define load32_ua(a) ntoh32_ua(a)
#define store32_ua(a, v) hton32_ua_store(v, a)
#define load16_ua(a) ntoh16_ua(a)
#define store16_ua(a, v) hton16_ua_store(v, a)
#endif /* IL_BIGENDIAN */
#define _LTOH16_UA(cp) ((cp)[0] | ((cp)[1] << 8))
#define _LTOH32_UA(cp) ((cp)[0] | ((cp)[1] << 8) | ((cp)[2] << 16) | ((cp)[3] << 24))
#define _NTOH16_UA(cp) (((cp)[0] << 8) | (cp)[1])
#define _NTOH32_UA(cp) (((cp)[0] << 24) | ((cp)[1] << 16) | ((cp)[2] << 8) | (cp)[3])
#define ltoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \
sizeof(*(ptr)) == sizeof(uint16) ? _LTOH16_UA((const uint8 *)(ptr)) : \
sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const uint8 *)(ptr)) : \
*(uint8 *)0)
#define ntoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \
sizeof(*(ptr)) == sizeof(uint16) ? _NTOH16_UA((const uint8 *)(ptr)) : \
sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const uint8 *)(ptr)) : \
*(uint8 *)0)
#ifdef __GNUC__
/* GNU macro versions avoid referencing the argument multiple times, while also
* avoiding the -fno-inline used in ROM builds.
*/
#define bcmswap16(val) ({ \
uint16 _val = (val); \
BCMSWAP16(_val); \
})
#define bcmswap32(val) ({ \
uint32 _val = (val); \
BCMSWAP32(_val); \
})
#define bcmswap32by16(val) ({ \
uint32 _val = (val); \
BCMSWAP32BY16(_val); \
})
#define bcmswap16_buf(buf, len) ({ \
uint16 *_buf = (uint16 *)(buf); \
uint _wds = (len) / 2; \
while (_wds--) { \
*_buf = bcmswap16(*_buf); \
_buf++; \
} \
})
#define htol16_ua_store(val, bytes) ({ \
uint16 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val & 0xff; \
_bytes[1] = _val >> 8; \
})
#define htol32_ua_store(val, bytes) ({ \
uint32 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val & 0xff; \
_bytes[1] = (_val >> 8) & 0xff; \
_bytes[2] = (_val >> 16) & 0xff; \
_bytes[3] = _val >> 24; \
})
#define hton16_ua_store(val, bytes) ({ \
uint16 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val >> 8; \
_bytes[1] = _val & 0xff; \
})
#define hton32_ua_store(val, bytes) ({ \
uint32 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val >> 24; \
_bytes[1] = (_val >> 16) & 0xff; \
_bytes[2] = (_val >> 8) & 0xff; \
_bytes[3] = _val & 0xff; \
})
#define ltoh16_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_LTOH16_UA(_bytes); \
})
#define ltoh32_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_LTOH32_UA(_bytes); \
})
#define ntoh16_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_NTOH16_UA(_bytes); \
})
#define ntoh32_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_NTOH32_UA(_bytes); \
})
#else /* !__GNUC__ */
/* Inline versions avoid referencing the argument multiple times */
static INLINE uint16 bcmswap16(uint16 val)
{
return BCMSWAP16(val);
}
static INLINE uint32 bcmswap32(uint32 val)
{
return BCMSWAP32(val);
}
static INLINE uint32 bcmswap32by16(uint32 val)
{
return BCMSWAP32BY16(val);
}
/* Reverse pairs of bytes in a buffer (not for high-performance use) */
/* buf - start of buffer of shorts to swap */
/* len - byte length of buffer */
static INLINE void bcmswap16_buf(uint16 * buf, uint len)
{
len = len / 2;
while (len--) {
*buf = bcmswap16(*buf);
buf++;
}
}
/*
* Store 16-bit value to unaligned little-endian byte array.
*/
static INLINE void htol16_ua_store(uint16 val, uint8 * bytes)
{
bytes[0] = val & 0xff;
bytes[1] = val >> 8;
}
/*
* Store 32-bit value to unaligned little-endian byte array.
*/
static INLINE void htol32_ua_store(uint32 val, uint8 * bytes)
{
bytes[0] = val & 0xff;
bytes[1] = (val >> 8) & 0xff;
bytes[2] = (val >> 16) & 0xff;
bytes[3] = val >> 24;
}
/*
* Store 16-bit value to unaligned network-(big-)endian byte array.
*/
static INLINE void hton16_ua_store(uint16 val, uint8 * bytes)
{
bytes[0] = val >> 8;
bytes[1] = val & 0xff;
}
/*
* Store 32-bit value to unaligned network-(big-)endian byte array.
*/
static INLINE void hton32_ua_store(uint32 val, uint8 * bytes)
{
bytes[0] = val >> 24;
bytes[1] = (val >> 16) & 0xff;
bytes[2] = (val >> 8) & 0xff;
bytes[3] = val & 0xff;
}
/*
* Load 16-bit value from unaligned little-endian byte array.
*/
static INLINE uint16 ltoh16_ua(const void *bytes)
{
return _LTOH16_UA((const uint8 *)bytes);
}
/*
* Load 32-bit value from unaligned little-endian byte array.
*/
static INLINE uint32 ltoh32_ua(const void *bytes)
{
return _LTOH32_UA((const uint8 *)bytes);
}
/*
* Load 16-bit value from unaligned big-(network-)endian byte array.
*/
static INLINE uint16 ntoh16_ua(const void *bytes)
{
return _NTOH16_UA((const uint8 *)bytes);
}
/*
* Load 32-bit value from unaligned big-(network-)endian byte array.
*/
static INLINE uint32 ntoh32_ua(const void *bytes)
{
return _NTOH32_UA((const uint8 *)bytes);
}
#endif /* !__GNUC__ */
#endif /* !_BCMENDIAN_H_ */
drivers/staging/brcm80211/include/bcmnvram.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmnvram_h_
#define _bcmnvram_h_
#ifndef _LANGUAGE_ASSEMBLY
#include <typedefs.h>
#include <bcmdefs.h>
struct nvram_header {
uint32 magic;
uint32 len;
uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
uint32 config_ncdl; /* ncdl values for memc */
};
struct nvram_tuple {
char *name;
char *value;
struct nvram_tuple *next;
};
/*
* Get default value for an NVRAM variable
*/
extern char *nvram_default_get(const char *name);
/*
* Initialize NVRAM access. May be unnecessary or undefined on certain
* platforms.
*/
extern int nvram_init(void *sih);
/*
* Append a chunk of nvram variables to the global list
*/
extern int nvram_append(void *si, char *vars, uint varsz);
/*
* Check for reset button press for restoring factory defaults.
*/
extern int nvram_reset(void *sih);
/*
* Disable NVRAM access. May be unnecessary or undefined on certain
* platforms.
*/
extern void nvram_exit(void *sih);
/*
* Get the value of an NVRAM variable. The pointer returned may be
* invalid after a set.
* @param name name of variable to get
* @return value of variable or NULL if undefined
*/
extern char *nvram_get(const char *name);
/*
* Read the reset GPIO value from the nvram and set the GPIO
* as input
*/
extern int BCMINITFN(nvram_resetgpio_init) (void *sih);
/*
* Get the value of an NVRAM variable.
* @param name name of variable to get
* @return value of variable or NUL if undefined
*/
#define nvram_safe_get(name) (nvram_get(name) ? : "")
/*
* Match an NVRAM variable.
* @param name name of variable to match
* @param match value to compare against value of variable
* @return TRUE if variable is defined and its value is string equal
* to match or FALSE otherwise
*/
static INLINE int nvram_match(char *name, char *match)
{
const char *value = nvram_get(name);
return (value && !strcmp(value, match));
}
/*
* Inversely match an NVRAM variable.
* @param name name of variable to match
* @param match value to compare against value of variable
* @return TRUE if variable is defined and its value is not string
* equal to invmatch or FALSE otherwise
*/
static INLINE int nvram_invmatch(char *name, char *invmatch)
{
const char *value = nvram_get(name);
return (value && strcmp(value, invmatch));
}
/*
* Set the value of an NVRAM variable. The name and value strings are
* copied into private storage. Pointers to previously set values
* may become invalid. The new value may be immediately
* retrieved but will not be permanently stored until a commit.
* @param name name of variable to set
* @param value value of variable
* @return 0 on success and errno on failure
*/
extern int nvram_set(const char *name, const char *value);
/*
* Unset an NVRAM variable. Pointers to previously set values
* remain valid until a set.
* @param name name of variable to unset
* @return 0 on success and errno on failure
* NOTE: use nvram_commit to commit this change to flash.
*/
extern int nvram_unset(const char *name);
/*
* Commit NVRAM variables to permanent storage. All pointers to values
* may be invalid after a commit.
* NVRAM values are undefined after a commit.
* @return 0 on success and errno on failure
*/
extern int nvram_commit(void);
/*
* Get all NVRAM variables (format name=value\0 ... \0\0).
* @param buf buffer to store variables
* @param count size of buffer in bytes
* @return 0 on success and errno on failure
*/
extern int nvram_getall(char *nvram_buf, int count);
/*
* returns the crc value of the nvram
* @param nvh nvram header pointer
*/
uint8 nvram_calc_crc(struct nvram_header *nvh);
#endif /* _LANGUAGE_ASSEMBLY */
/* The NVRAM version number stored as an NVRAM variable */
#define NVRAM_SOFTWARE_VERSION "1"
#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
#define NVRAM_CLEAR_MAGIC 0x0
#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
#define NVRAM_VERSION 1
#define NVRAM_HEADER_SIZE 20
#define NVRAM_SPACE 0x8000
#define NVRAM_MAX_VALUE_LEN 255
#define NVRAM_MAX_PARAM_LEN 64
#define NVRAM_CRC_START_POSITION 9 /* magic, len, crc8 to be skipped */
#define NVRAM_CRC_VER_MASK 0xffffff00 /* for crc_ver_init */
#endif /* _bcmnvram_h_ */
drivers/staging/brcm80211/include/bcmotp.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmotp_h_
#define _bcmotp_h_
/* OTP regions */
#define OTP_HW_RGN 1
#define OTP_SW_RGN 2
#define OTP_CI_RGN 4
#define OTP_FUSE_RGN 8
#define OTP_ALL_RGN 0xf /* From h/w region to end of OTP including checksum */
/* OTP Size */
#define OTP_SZ_MAX (6144/8) /* maximum bytes in one CIS */
/* Fixed size subregions sizes in words */
#define OTPGU_CI_SZ 2
/* OTP usage */
#define OTP4325_FM_DISABLED_OFFSET 188
/* Exported functions */
extern int otp_status(void *oh);
extern int otp_size(void *oh);
extern uint16 otp_read_bit(void *oh, uint offset);
extern void *otp_init(si_t * sih);
extern int otp_read_region(si_t * sih, int region, uint16 * data, uint * wlen);
extern int otp_nvread(void *oh, char *data, uint * len);
#endif /* _bcmotp_h_ */
drivers/staging/brcm80211/include/bcmsdbus.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _sdio_api_h_
#define _sdio_api_h_
#define SDIOH_API_RC_SUCCESS (0x00)
#define SDIOH_API_RC_FAIL (0x01)
#define SDIOH_API_SUCCESS(status) (status == 0)
#define SDIOH_READ 0 /* Read request */
#define SDIOH_WRITE 1 /* Write request */
#define SDIOH_DATA_FIX 0 /* Fixed addressing */
#define SDIOH_DATA_INC 1 /* Incremental addressing */
#define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */
#define SDIOH_CMD_TYPE_APPEND 1 /* Append command */
#define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */
#define SDIOH_DATA_PIO 0 /* PIO mode */
#define SDIOH_DATA_DMA 1 /* DMA mode */
typedef int SDIOH_API_RC;
/* SDio Host structure */
typedef struct sdioh_info sdioh_info_t;
/* callback function, taking one arg */
typedef void (*sdioh_cb_fn_t) (void *);
/* attach, return handler on success, NULL if failed.
* The handler shall be provided by all subsequent calls. No local cache
* cfghdl points to the starting address of pci device mapped memory
*/
extern sdioh_info_t *sdioh_attach(osl_t * osh, void *cfghdl, uint irq);
extern SDIOH_API_RC sdioh_detach(osl_t * osh, sdioh_info_t * si);
extern SDIOH_API_RC sdioh_interrupt_register(sdioh_info_t * si,
sdioh_cb_fn_t fn, void *argh);
extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t * si);
/* query whether SD interrupt is enabled or not */
extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t * si, bool * onoff);
/* enable or disable SD interrupt */
extern SDIOH_API_RC sdioh_interrupt_set(sdioh_info_t * si, bool enable_disable);
#if defined(BCMDBG)
extern bool sdioh_interrupt_pending(sdioh_info_t * si);
#endif
extern int sdioh_claim_host_and_lock(sdioh_info_t * si);
extern int sdioh_release_host_and_unlock(sdioh_info_t * si);
/* read or write one byte using cmd52 */
extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t * si, uint rw, uint fnc,
uint addr, uint8 * byte);
/* read or write 2/4 bytes using cmd53 */
extern SDIOH_API_RC sdioh_request_word(sdioh_info_t * si, uint cmd_type,
uint rw, uint fnc, uint addr,
uint32 * word, uint nbyte);
/* read or write any buffer using cmd53 */
extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t * si, uint pio_dma,
uint fix_inc, uint rw, uint fnc_num,
uint32 addr, uint regwidth,
uint32 buflen, uint8 * buffer,
void *pkt);
/* get cis data */
extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t * si, uint fuc, uint8 * cis,
uint32 length);
extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t * si, uint fuc, uint32 addr,
uint8 * data);
extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t * si, uint fuc, uint32 addr,
uint8 * data);
/* query number of io functions */
extern uint sdioh_query_iofnum(sdioh_info_t * si);
/* handle iovars */
extern int sdioh_iovar_op(sdioh_info_t * si, const char *name,
void *params, int plen, void *arg, int len, bool set);
/* Issue abort to the specified function and clear controller as needed */
extern int sdioh_abort(sdioh_info_t * si, uint fnc);
/* Start and Stop SDIO without re-enumerating the SD card. */
extern int sdioh_start(sdioh_info_t * si, int stage);
extern int sdioh_stop(sdioh_info_t * si);
/* Reset and re-initialize the device */
extern int sdioh_sdio_reset(sdioh_info_t * si);
/* Helper function */
void *bcmsdh_get_sdioh(bcmsdh_info_t * sdh);
#endif /* _sdio_api_h_ */
drivers/staging/brcm80211/include/bcmsdh.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsdh_h_
#define _bcmsdh_h_
#define BCMSDH_ERROR_VAL 0x0001 /* Error */
#define BCMSDH_INFO_VAL 0x0002 /* Info */
extern const uint bcmsdh_msglevel;
#ifdef BCMDBG
#define BCMSDH_ERROR(x) do { if ((bcmsdh_msglevel & BCMSDH_ERROR_VAL) && net_ratelimit()) printf x; } while (0)
#define BCMSDH_INFO(x) do { if ((bcmsdh_msglevel & BCMSDH_INFO_VAL) && net_ratelimit()) printf x; } while (0)
#else /* BCMDBG */
#define BCMSDH_ERROR(x)
#define BCMSDH_INFO(x)
#endif /* BCMDBG */
/* forward declarations */
typedef struct bcmsdh_info bcmsdh_info_t;
typedef void (*bcmsdh_cb_fn_t) (void *);
/* Attach and build an interface to the underlying SD host driver.
* - Allocates resources (structs, arrays, mem, OS handles, etc) needed by bcmsdh.
* - Returns the bcmsdh handle and virtual address base for register access.
* The returned handle should be used in all subsequent calls, but the bcmsh
* implementation may maintain a single "default" handle (e.g. the first or
* most recent one) to enable single-instance implementations to pass NULL.
*/
extern bcmsdh_info_t *bcmsdh_attach(osl_t * osh, void *cfghdl, void **regsva,
uint irq);
/* Detach - freeup resources allocated in attach */
extern int bcmsdh_detach(osl_t * osh, void *sdh);
/* Query if SD device interrupts are enabled */
extern bool bcmsdh_intr_query(void *sdh);
/* Enable/disable SD interrupt */
extern int bcmsdh_intr_enable(void *sdh);
extern int bcmsdh_intr_disable(void *sdh);
/* Register/deregister device interrupt handler. */
extern int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
extern int bcmsdh_intr_dereg(void *sdh);
#if defined(BCMDBG)
/* Query pending interrupt status from the host controller */
extern bool bcmsdh_intr_pending(void *sdh);
#endif
extern int bcmsdh_claim_host_and_lock(void *sdh);
extern int bcmsdh_release_host_and_unlock(void *sdh);
/* Register a callback to be called if and when bcmsdh detects
* device removal. No-op in the case of non-removable/hardwired devices.
*/
extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
* fn: function number
* addr: unmodified SDIO-space address
* data: data byte to write
* err: pointer to error code (or NULL)
*/
extern uint8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err);
extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, uint8 data,
int *err);
/* Read/Write 4bytes from/to cfg space */
extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr,
int *err);
extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr,
uint32 data, int *err);
/* Read CIS content for specified function.
* fn: function whose CIS is being requested (0 is common CIS)
* cis: pointer to memory location to place results
* length: number of bytes to read
* Internally, this routine uses the values from the cis base regs (0x9-0xB)
* to form an SDIO-space address to read the data from.
*/
extern int bcmsdh_cis_read(void *sdh, uint func, uint8 * cis, uint length);
/* Synchronous access to device (client) core registers via CMD53 to F1.
* addr: backplane address (i.e. >= regsva from attach)
* size: register width in bytes (2 or 4)
* data: data for register write
*/
extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size);
extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data);
/* Indicate if last reg read/write failed */
extern bool bcmsdh_regfail(void *sdh);
/* Buffer transfer to/from device (client) core via cmd53.
* fn: function number
* addr: backplane address (i.e. >= regsva from attach)
* flags: backplane width, address increment, sync/async
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* pkt: pointer to packet associated with buf (if any)
* complete: callback function for command completion (async only)
* handle: handle for completion callback (first arg in callback)
* Returns 0 or error code.
* NOTE: Async operation is not currently supported.
*/
typedef void (*bcmsdh_cmplt_fn_t) (void *handle, int status, bool sync_waiting);
extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 * buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle);
extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 * buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle);
/* Flags bits */
#define SDIO_REQ_4BYTE 0x1 /* Four-byte target (backplane) width (vs. two-byte) */
#define SDIO_REQ_FIXED 0x2 /* Fixed address (FIFO) (vs. incrementing address) */
#define SDIO_REQ_ASYNC 0x4 /* Async request (vs. sync request) */
/* Pending (non-error) return code */
#define BCME_PENDING 1
/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
* rw: read or write (0/1)
* addr: direct SDIO address
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* Returns 0 or error code.
*/
extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 * buf,
uint nbytes);
/* Issue an abort to the specified function */
extern int bcmsdh_abort(void *sdh, uint fn);
/* Start SDIO Host Controller communication */
extern int bcmsdh_start(void *sdh, int stage);
/* Stop SDIO Host Controller communication */
extern int bcmsdh_stop(void *sdh);
/* Returns the "Device ID" of target device on the SDIO bus. */
extern int bcmsdh_query_device(void *sdh);
/* Returns the number of IO functions reported by the device */
extern uint bcmsdh_query_iofnum(void *sdh);
/* Miscellaneous knob tweaker. */
extern int bcmsdh_iovar_op(void *sdh, const char *name,
void *params, int plen, void *arg, int len,
bool set);
/* Reset and reinitialize the device */
extern int bcmsdh_reset(bcmsdh_info_t * sdh);
/* helper functions */
extern void *bcmsdh_get_sdioh(bcmsdh_info_t * sdh);
/* callback functions */
typedef struct {
/* attach to device */
void *(*attach) (uint16 vend_id, uint16 dev_id, uint16 bus, uint16 slot,
uint16 func, uint bustype, void *regsva, osl_t * osh,
void *param);
/* detach from device */
void (*detach) (void *ch);
} bcmsdh_driver_t;
/* platform specific/high level functions */
extern int bcmsdh_register(bcmsdh_driver_t * driver);
extern void bcmsdh_unregister(void);
extern bool bcmsdh_chipmatch(uint16 vendor, uint16 device);
extern void bcmsdh_device_remove(void *sdh);
/* Function to pass device-status bits to DHD. */
extern uint32 bcmsdh_get_dstatus(void *sdh);
/* Function to return current window addr */
extern uint32 bcmsdh_cur_sbwad(void *sdh);
/* Function to pass chipid and rev to lower layers for controlling pr's */
extern void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev);
#endif /* _bcmsdh_h_ */
drivers/staging/brcm80211/include/bcmsdh_sdmmc.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __BCMSDH_SDMMC_H__
#define __BCMSDH_SDMMC_H__
#ifdef BCMDBG
#define sd_err(x) do { if ((sd_msglevel & SDH_ERROR_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_trace(x) do { if ((sd_msglevel & SDH_TRACE_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_info(x) do { if ((sd_msglevel & SDH_INFO_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_debug(x) do { if ((sd_msglevel & SDH_DEBUG_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_data(x) do { if ((sd_msglevel & SDH_DATA_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_ctrl(x) do { if ((sd_msglevel & SDH_CTRL_VAL) && net_ratelimit()) printf x; } while (0)
#else
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#endif
/* Allocate/init/free per-OS private data */
extern int sdioh_sdmmc_osinit(sdioh_info_t * sd);
extern void sdioh_sdmmc_osfree(sdioh_info_t * sd);
#define BLOCK_SIZE_64 64
#define BLOCK_SIZE_512 512
/* internal return code */
#define SUCCESS 0
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SD4 2
#define CLIENT_INTR 0x100 /* Get rid of this! */
struct sdioh_info {
osl_t *osh; /* osh handler */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
uint16 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint irq; /* Client irq */
int intrcount; /* Client interrupts */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
uint max_dma_len;
uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */
/* SDDMA_DESCRIPTOR SGList[32]; *//* Scatter/Gather DMA List */
};
/************************************************************
* Internal interfaces: per-port references into bcmsdh_sdmmc.c
*/
/* Global message bits */
extern uint sd_msglevel;
/* OS-independent interrupt handler */
extern bool check_client_intr(sdioh_info_t * sd);
/* Core interrupt enable/disable of device interrupts */
extern void sdioh_sdmmc_devintr_on(sdioh_info_t * sd);
extern void sdioh_sdmmc_devintr_off(sdioh_info_t * sd);
/**************************************************************
* Internal interfaces: bcmsdh_sdmmc.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *sdioh_sdmmc_reg_map(osl_t * osh, int32 addr, int size);
extern void sdioh_sdmmc_reg_unmap(osl_t * osh, int32 addr, int size);
/* Interrupt (de)registration routines */
extern int sdioh_sdmmc_register_irq(sdioh_info_t * sd, uint irq);
extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t * sd);
typedef struct _BCMSDH_SDMMC_INSTANCE {
sdioh_info_t *sd;
struct sdio_func *func[SDIOD_MAX_IOFUNCS];
uint32 host_claimed;
} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE;
#endif /* __BCMSDH_SDMMC_H__ */
drivers/staging/brcm80211/include/bcmsdpcm.h 0 → 100644
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drivers/staging/brcm80211/include/bcmsrom.h 0 → 100644
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsrom_h_
#define _bcmsrom_h_
#include <bcmsrom_fmt.h>
/* Prototypes */
extern int srom_var_init(si_t * sih, uint bus, void *curmap, osl_t * osh,
char **vars, uint * count);
extern int srom_read(si_t * sih, uint bus, void *curmap, osl_t * osh,
uint byteoff, uint nbytes, uint16 * buf, bool check_crc);
/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
* and extract from it into name=value pairs
*/
extern int srom_parsecis(osl_t * osh, uint8 ** pcis, uint ciscnt,
char **vars, uint * count);
#endif /* _bcmsrom_h_ */
drivers/staging/brcm80211/include/bcmsrom_fmt.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsrom_fmt_h_
#define _bcmsrom_fmt_h_
/* Maximum srom: 6 Kilobits == 768 bytes */
#define SROM_MAX 768
#define SROM_MAXW 384
#define VARS_MAX 4096
/* PCI fields */
#define PCI_F0DEVID 48
#define SROM_WORDS 64
#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */
#define SROM_SSID 2
#define SROM_WL1LHMAXP 29
#define SROM_WL1LPAB0 30
#define SROM_WL1LPAB1 31
#define SROM_WL1LPAB2 32
#define SROM_WL1HPAB0 33
#define SROM_WL1HPAB1 34
#define SROM_WL1HPAB2 35
#define SROM_MACHI_IL0 36
#define SROM_MACMID_IL0 37
#define SROM_MACLO_IL0 38
#define SROM_MACHI_ET0 39
#define SROM_MACMID_ET0 40
#define SROM_MACLO_ET0 41
#define SROM_MACHI_ET1 42
#define SROM_MACMID_ET1 43
#define SROM_MACLO_ET1 44
#define SROM3_MACHI 37
#define SROM3_MACMID 38
#define SROM3_MACLO 39
#define SROM_BXARSSI2G 40
#define SROM_BXARSSI5G 41
#define SROM_TRI52G 42
#define SROM_TRI5GHL 43
#define SROM_RXPO52G 45
#define SROM2_ENETPHY 45
#define SROM_AABREV 46
/* Fields in AABREV */
#define SROM_BR_MASK 0x00ff
#define SROM_CC_MASK 0x0f00
#define SROM_CC_SHIFT 8
#define SROM_AA0_MASK 0x3000
#define SROM_AA0_SHIFT 12
#define SROM_AA1_MASK 0xc000
#define SROM_AA1_SHIFT 14
#define SROM_WL0PAB0 47
#define SROM_WL0PAB1 48
#define SROM_WL0PAB2 49
#define SROM_LEDBH10 50
#define SROM_LEDBH32 51
#define SROM_WL10MAXP 52
#define SROM_WL1PAB0 53
#define SROM_WL1PAB1 54
#define SROM_WL1PAB2 55
#define SROM_ITT 56
#define SROM_BFL 57
#define SROM_BFL2 28
#define SROM3_BFL2 61
#define SROM_AG10 58
#define SROM_CCODE 59
#define SROM_OPO 60
#define SROM3_LEDDC 62
#define SROM_CRCREV 63
/* SROM Rev 4: Reallocate the software part of the srom to accomodate
* MIMO features. It assumes up to two PCIE functions and 440 bytes
* of useable srom i.e. the useable storage in chips with OTP that
* implements hardware redundancy.
*/
#define SROM4_WORDS 220
#define SROM4_SIGN 32
#define SROM4_SIGNATURE 0x5372
#define SROM4_BREV 33
#define SROM4_BFL0 34
#define SROM4_BFL1 35
#define SROM4_BFL2 36
#define SROM4_BFL3 37
#define SROM5_BFL0 37
#define SROM5_BFL1 38
#define SROM5_BFL2 39
#define SROM5_BFL3 40
#define SROM4_MACHI 38
#define SROM4_MACMID 39
#define SROM4_MACLO 40
#define SROM5_MACHI 41
#define SROM5_MACMID 42
#define SROM5_MACLO 43
#define SROM4_CCODE 41
#define SROM4_REGREV 42
#define SROM5_CCODE 34
#define SROM5_REGREV 35
#define SROM4_LEDBH10 43
#define SROM4_LEDBH32 44
#define SROM5_LEDBH10 59
#define SROM5_LEDBH32 60
#define SROM4_LEDDC 45
#define SROM5_LEDDC 45
#define SROM4_AA 46
#define SROM4_AA2G_MASK 0x00ff
#define SROM4_AA2G_SHIFT 0
#define SROM4_AA5G_MASK 0xff00
#define SROM4_AA5G_SHIFT 8
#define SROM4_AG10 47
#define SROM4_AG32 48
#define SROM4_TXPID2G 49
#define SROM4_TXPID5G 51
#define SROM4_TXPID5GL 53
#define SROM4_TXPID5GH 55
#define SROM4_TXRXC 61
#define SROM4_TXCHAIN_MASK 0x000f
#define SROM4_TXCHAIN_SHIFT 0
#define SROM4_RXCHAIN_MASK 0x00f0
#define SROM4_RXCHAIN_SHIFT 4
#define SROM4_SWITCH_MASK 0xff00
#define SROM4_SWITCH_SHIFT 8
/* Per-path fields */
#define MAX_PATH_SROM 4
#define SROM4_PATH0 64
#define SROM4_PATH1 87
#define SROM4_PATH2 110
#define SROM4_PATH3 133
#define SROM4_2G_ITT_MAXP 0
#define SROM4_2G_PA 1
#define SROM4_5G_ITT_MAXP 5
#define SROM4_5GLH_MAXP 6
#define SROM4_5G_PA 7
#define SROM4_5GL_PA 11
#define SROM4_5GH_PA 15
/* Fields in the ITT_MAXP and 5GLH_MAXP words */
#define B2G_MAXP_MASK 0xff
#define B2G_ITT_SHIFT 8
#define B5G_MAXP_MASK 0xff
#define B5G_ITT_SHIFT 8
#define B5GH_MAXP_MASK 0xff
#define B5GL_MAXP_SHIFT 8
/* All the miriad power offsets */
#define SROM4_2G_CCKPO 156
#define SROM4_2G_OFDMPO 157
#define SROM4_5G_OFDMPO 159
#define SROM4_5GL_OFDMPO 161
#define SROM4_5GH_OFDMPO 163
#define SROM4_2G_MCSPO 165
#define SROM4_5G_MCSPO 173
#define SROM4_5GL_MCSPO 181
#define SROM4_5GH_MCSPO 189
#define SROM4_CDDPO 197
#define SROM4_STBCPO 198
#define SROM4_BW40PO 199
#define SROM4_BWDUPPO 200
#define SROM4_CRCREV 219
/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
* This is acombined srom for both MIMO and SISO boards, usable in
* the .130 4Kilobit OTP with hardware redundancy.
*/
#define SROM8_SIGN 64
#define SROM8_BREV 65
#define SROM8_BFL0 66
#define SROM8_BFL1 67
#define SROM8_BFL2 68
#define SROM8_BFL3 69
#define SROM8_MACHI 70
#define SROM8_MACMID 71
#define SROM8_MACLO 72
#define SROM8_CCODE 73
#define SROM8_REGREV 74
#define SROM8_LEDBH10 75
#define SROM8_LEDBH32 76
#define SROM8_LEDDC 77
#define SROM8_AA 78
#define SROM8_AG10 79
#define SROM8_AG32 80
#define SROM8_TXRXC 81
#define SROM8_BXARSSI2G 82
#define SROM8_BXARSSI5G 83
#define SROM8_TRI52G 84
#define SROM8_TRI5GHL 85
#define SROM8_RXPO52G 86
#define SROM8_FEM2G 87
#define SROM8_FEM5G 88
#define SROM8_FEM_ANTSWLUT_MASK 0xf800
#define SROM8_FEM_ANTSWLUT_SHIFT 11
#define SROM8_FEM_TR_ISO_MASK 0x0700
#define SROM8_FEM_TR_ISO_SHIFT 8
#define SROM8_FEM_PDET_RANGE_MASK 0x00f8
#define SROM8_FEM_PDET_RANGE_SHIFT 3
#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
#define SROM8_FEM_EXTPA_GAIN_SHIFT 1
#define SROM8_FEM_TSSIPOS_MASK 0x0001
#define SROM8_FEM_TSSIPOS_SHIFT 0
#define SROM8_THERMAL 89
/* Temp sense related entries */
#define SROM8_MPWR_RAWTS 90
#define SROM8_TS_SLP_OPT_CORRX 91
/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
#define SROM8_FOC_HWIQ_IQSWP 92
/* Temperature delta for PHY calibration */
#define SROM8_PHYCAL_TEMPDELTA 93
/* Per-path offsets & fields */
#define SROM8_PATH0 96
#define SROM8_PATH1 112
#define SROM8_PATH2 128
#define SROM8_PATH3 144
#define SROM8_2G_ITT_MAXP 0
#define SROM8_2G_PA 1
#define SROM8_5G_ITT_MAXP 4
#define SROM8_5GLH_MAXP 5
#define SROM8_5G_PA 6
#define SROM8_5GL_PA 9
#define SROM8_5GH_PA 12
/* All the miriad power offsets */
#define SROM8_2G_CCKPO 160
#define SROM8_2G_OFDMPO 161
#define SROM8_5G_OFDMPO 163
#define SROM8_5GL_OFDMPO 165
#define SROM8_5GH_OFDMPO 167
#define SROM8_2G_MCSPO 169
#define SROM8_5G_MCSPO 177
#define SROM8_5GL_MCSPO 185
#define SROM8_5GH_MCSPO 193
#define SROM8_CDDPO 201
#define SROM8_STBCPO 202
#define SROM8_BW40PO 203
#define SROM8_BWDUPPO 204
/* SISO PA parameters are in the path0 spaces */
#define SROM8_SISO 96
/* Legacy names for SISO PA paramters */
#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
#define SROM8_CRCREV 219
/* SROM REV 9 */
#define SROM9_2GPO_CCKBW20 160
#define SROM9_2GPO_CCKBW20UL 161
#define SROM9_2GPO_LOFDMBW20 162
#define SROM9_2GPO_LOFDMBW20UL 164
#define SROM9_5GLPO_LOFDMBW20 166
#define SROM9_5GLPO_LOFDMBW20UL 168
#define SROM9_5GMPO_LOFDMBW20 170
#define SROM9_5GMPO_LOFDMBW20UL 172
#define SROM9_5GHPO_LOFDMBW20 174
#define SROM9_5GHPO_LOFDMBW20UL 176
#define SROM9_2GPO_MCSBW20 178
#define SROM9_2GPO_MCSBW20UL 180
#define SROM9_2GPO_MCSBW40 182
#define SROM9_5GLPO_MCSBW20 184
#define SROM9_5GLPO_MCSBW20UL 186
#define SROM9_5GLPO_MCSBW40 188
#define SROM9_5GMPO_MCSBW20 190
#define SROM9_5GMPO_MCSBW20UL 192
#define SROM9_5GMPO_MCSBW40 194
#define SROM9_5GHPO_MCSBW20 196
#define SROM9_5GHPO_MCSBW20UL 198
#define SROM9_5GHPO_MCSBW40 200
#define SROM9_PO_MCS32 202
#define SROM9_PO_LOFDM40DUP 203
#define SROM9_REV_CRC 219
typedef struct {
uint8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */
uint8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
uint8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */
uint8 triso; /* TR switch isolation */
uint8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */
} srom_fem_t;
#endif /* _bcmsrom_fmt_h_ */
drivers/staging/brcm80211/include/bcmsrom_tbl.h 0 → 100644
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drivers/staging/brcm80211/include/bcmutils.h 0 → 100644
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drivers/staging/brcm80211/include/bcmwifi.h 0 → 100644
View file @ a9533e7e
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmwifi_h_
#define _bcmwifi_h_
/* A chanspec holds the channel number, band, bandwidth and control sideband */
typedef uint16 chanspec_t;
/* channel defines */
#define CH_UPPER_SB 0x01
#define CH_LOWER_SB 0x02
#define CH_EWA_VALID 0x04
#define CH_20MHZ_APART 4
#define CH_10MHZ_APART 2
#define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
#define CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */
#define WLC_MAX_2G_CHANNEL CH_MAX_2G_CHANNEL /* legacy define */
#define MAXCHANNEL 224 /* max # supported channels. The max channel no is 216,
* this is that + 1 rounded up to a multiple of NBBY (8).
* DO NOT MAKE it > 255: channels are uint8's all over
*/
#define WL_CHANSPEC_CHAN_MASK 0x00ff
#define WL_CHANSPEC_CHAN_SHIFT 0
#define WL_CHANSPEC_CTL_SB_MASK 0x0300
#define WL_CHANSPEC_CTL_SB_SHIFT 8
#define WL_CHANSPEC_CTL_SB_LOWER 0x0100
#define WL_CHANSPEC_CTL_SB_UPPER 0x0200
#define WL_CHANSPEC_CTL_SB_NONE 0x0300
#define WL_CHANSPEC_BW_MASK 0x0C00
#define WL_CHANSPEC_BW_SHIFT 10
#define WL_CHANSPEC_BW_10 0x0400
#define WL_CHANSPEC_BW_20 0x0800
#define WL_CHANSPEC_BW_40 0x0C00
#define WL_CHANSPEC_BAND_MASK 0xf000
#define WL_CHANSPEC_BAND_SHIFT 12
#define WL_CHANSPEC_BAND_5G 0x1000
#define WL_CHANSPEC_BAND_2G 0x2000
#define INVCHANSPEC 255
/* used to calculate the chan_freq = chan_factor * 500Mhz + 5 * chan_number */
#define WF_CHAN_FACTOR_2_4_G 4814 /* 2.4 GHz band, 2407 MHz */
#define WF_CHAN_FACTOR_5_G 10000 /* 5 GHz band, 5000 MHz */
#define WF_CHAN_FACTOR_4_G 8000 /* 4.9 GHz band for Japan */
/* channel defines */
#define LOWER_20_SB(channel) (((channel) > CH_10MHZ_APART) ? ((channel) - CH_10MHZ_APART) : 0)
#define UPPER_20_SB(channel) (((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
((channel) + CH_10MHZ_APART) : 0)
#define CHSPEC_WLCBANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX)
#define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
WL_CHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
#define NEXT_20MHZ_CHAN(channel) (((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
((channel) + CH_20MHZ_APART) : 0)
#define CH40MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
WL_CHANSPEC_BAND_5G))
#define CHSPEC_CHANNEL(chspec) ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK))
#define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK)
#ifdef WL11N_20MHZONLY
#define CHSPEC_CTL_SB(chspec) WL_CHANSPEC_CTL_SB_NONE
#define CHSPEC_BW(chspec) WL_CHANSPEC_BW_20
#define CHSPEC_IS10(chspec) 0
#define CHSPEC_IS20(chspec) 1
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) 0
#endif
#else /* !WL11N_20MHZONLY */
#define CHSPEC_CTL_SB(chspec) ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
#define CHSPEC_BW(chspec) ((chspec) & WL_CHANSPEC_BW_MASK)
#define CHSPEC_IS10(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
#define CHSPEC_IS20(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
#endif
#endif /* !WL11N_20MHZONLY */
#define CHSPEC_IS5G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
#define CHSPEC_IS2G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
#define CHSPEC_SB_NONE(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
#define CHSPEC_SB_UPPER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
#define CHSPEC_SB_LOWER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
#define CHSPEC_CTL_CHAN(chspec) ((CHSPEC_SB_LOWER(chspec)) ? \
(LOWER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
(UPPER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))))
#define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G(chspec) ? WLC_BAND_5G : WLC_BAND_2G)
#define CHANSPEC_STR_LEN 8
/* defined rate in 500kbps */
#define WLC_MAXRATE 108 /* in 500kbps units */
#define WLC_RATE_1M 2 /* in 500kbps units */
#define WLC_RATE_2M 4 /* in 500kbps units */
#define WLC_RATE_5M5 11 /* in 500kbps units */
#define WLC_RATE_11M 22 /* in 500kbps units */
#define WLC_RATE_6M 12 /* in 500kbps units */
#define WLC_RATE_9M 18 /* in 500kbps units */
#define WLC_RATE_12M 24 /* in 500kbps units */
#define WLC_RATE_18M 36 /* in 500kbps units */
#define WLC_RATE_24M 48 /* in 500kbps units */
#define WLC_RATE_36M 72 /* in 500kbps units */
#define WLC_RATE_48M 96 /* in 500kbps units */
#define WLC_RATE_54M 108 /* in 500kbps units */
#define WLC_2G_25MHZ_OFFSET 5 /* 2.4GHz band channel offset */
/*
* Convert chanspec to ascii string
* @param chspec chanspec format
* @param buf ascii string of chanspec
* @return pointer to buf with room for at least CHANSPEC_STR_LEN bytes
*/
extern char *wf_chspec_ntoa(chanspec_t chspec, char *buf);
/*
* Convert ascii string to chanspec
* @param a pointer to input string
* @return >= 0 if successful or 0 otherwise
*/
extern chanspec_t wf_chspec_aton(char *a);
/*
* Verify the chanspec is using a legal set of parameters, i.e. that the
* chanspec specified a band, bw, ctl_sb and channel and that the
* combination could be legal given any set of circumstances.
* RETURNS: TRUE is the chanspec is malformed, false if it looks good.
*/
extern bool wf_chspec_malformed(chanspec_t chanspec);
/*
* This function returns the channel number that control traffic is being sent on, for legacy
* channels this is just the channel number, for 40MHZ channels it is the upper or lowre 20MHZ
* sideband depending on the chanspec selected
*/
extern uint8 wf_chspec_ctlchan(chanspec_t chspec);
/*
* This function returns the chanspec that control traffic is being sent on, for legacy
* channels this is just the chanspec, for 40MHZ channels it is the upper or lowre 20MHZ
* sideband depending on the chanspec selected
*/
extern chanspec_t wf_chspec_ctlchspec(chanspec_t chspec);
/*
* Return the channel number for a given frequency and base frequency.
* The returned channel number is relative to the given base frequency.
* If the given base frequency is zero, a base frequency of 5 GHz is assumed for
* frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
*
* Frequency is specified in MHz.
* The base frequency is specified as (start_factor * 500 kHz).
* Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
* 2.4 GHz and 5 GHz bands.
*
* The returned channel will be in the range [1, 14] in the 2.4 GHz band
* and [0, 200] otherwise.
* -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
* frequency is not a 2.4 GHz channel, or if the frequency is not and even
* multiple of 5 MHz from the base frequency to the base plus 1 GHz.
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*/
extern int wf_mhz2channel(uint freq, uint start_factor);
/*
* Return the center frequency in MHz of the given channel and base frequency.
* The channel number is interpreted relative to the given base frequency.
*
* The valid channel range is [1, 14] in the 2.4 GHz band and [0, 200] otherwise.
* The base frequency is specified as (start_factor * 500 kHz).
* Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
* 2.4 GHz and 5 GHz bands.
* The channel range of [1, 14] is only checked for a start_factor of
* WF_CHAN_FACTOR_2_4_G (4814).
* Odd start_factors produce channels on .5 MHz boundaries, in which case
* the answer is rounded down to an integral MHz.
* -1 is returned for an out of range channel.
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*/
extern int wf_channel2mhz(uint channel, uint start_factor);
#endif /* _bcmwifi_h_ */
drivers/staging/brcm80211/include/bcmwpa.h 0 → 100644
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCMWPA_H_
#define _BCMWPA_H_
#include <proto/wpa.h>
#include <proto/802.11.h>
#include <wlioctl.h>
/* Field sizes for WPA key hierarchy */
#define WPA_MIC_KEY_LEN 16
#define WPA_ENCR_KEY_LEN 16
#define WPA_TEMP_ENCR_KEY_LEN 16
#define WPA_TEMP_TX_KEY_LEN 8
#define WPA_TEMP_RX_KEY_LEN 8
#define PMK_LEN 32
#define TKIP_PTK_LEN 64
#define TKIP_TK_LEN 32
#define AES_PTK_LEN 48
#define AES_TK_LEN 16
/* limits for pre-shared key lengths */
#define WPA_MIN_PSK_LEN 8
#define WPA_MAX_PSK_LEN 64
#define WLC_SW_KEYS(wlc, bsscfg) ((((wlc)->wsec_swkeys) || \
((bsscfg)->wsec & WSEC_SWFLAG)))
#define WSEC_WEP_ENABLED(wsec) ((wsec) & WEP_ENABLED)
#define WSEC_TKIP_ENABLED(wsec) ((wsec) & TKIP_ENABLED)
#define WSEC_AES_ENABLED(wsec) ((wsec) & AES_ENABLED)
#define WSEC_ENABLED(wsec) ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
#define WSEC_SES_OW_ENABLED(wsec) ((wsec) & SES_OW_ENABLED)
#define IS_WPA_AUTH(auth) ((auth) == WPA_AUTH_NONE || \
(auth) == WPA_AUTH_UNSPECIFIED || \
(auth) == WPA_AUTH_PSK)
#define INCLUDES_WPA_AUTH(auth) \
((auth) & (WPA_AUTH_NONE | WPA_AUTH_UNSPECIFIED | WPA_AUTH_PSK))
#define IS_WPA2_AUTH(auth) ((auth) == WPA2_AUTH_UNSPECIFIED || \
(auth) == WPA2_AUTH_PSK)(
#define INCLUDES_WPA2_AUTH(auth) \
((auth) & (WPA2_AUTH_UNSPECIFIED | \
WPA2_AUTH_PSK))
#define IS_WPA_AKM(akm) ((akm) == RSN_AKM_NONE || \
(akm) == RSN_AKM_UNSPECIFIED || \
(akm) == RSN_AKM_PSK)
#define IS_WPA2_AKM(akm) ((akm) == RSN_AKM_UNSPECIFIED || \
(akm) == RSN_AKM_PSK)
#define MAX_ARRAY 1
#define MIN_ARRAY 0
/* convert wsec to WPA mcast cipher. algo is needed only when WEP is enabled. */
#define WPA_MCAST_CIPHER(wsec, algo) (WSEC_WEP_ENABLED(wsec) ? \
((algo) == CRYPTO_ALGO_WEP128 ? WPA_CIPHER_WEP_104 : WPA_CIPHER_WEP_40) : \
WSEC_TKIP_ENABLED(wsec) ? WPA_CIPHER_TKIP : \
WSEC_AES_ENABLED(wsec) ? WPA_CIPHER_AES_CCM : \
WPA_CIPHER_NONE)
/* Look for a WPA IE; return it's address if found, NULL otherwise */
extern wpa_ie_fixed_t *BCMROMFN(bcm_find_wpaie) (uint8 * parse, uint len);
/* Check whether the given IE looks like WFA IE with the specific type. */
extern bool bcm_is_wfa_ie(uint8 * ie, uint8 ** tlvs, uint * tlvs_len,
uint8 type);
/* Check whether pointed-to IE looks like WPA. */
#define bcm_is_wpa_ie(ie, tlvs, len) bcm_is_wfa_ie(ie, tlvs, len, WFA_OUI_TYPE_WPA)
#endif /* _BCMWPA_H_ */
drivers/staging/brcm80211/include/bitfuncs.h 0 → 100644
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BITFUNCS_H
#define _BITFUNCS_H
#include <typedefs.h>
/* local prototypes */
static INLINE uint32 find_msbit(uint32 x);
/*
* find_msbit: returns index of most significant set bit in x, with index
* range defined as 0-31. NOTE: returns zero if input is zero.
*/
#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
/*
* Implementation for Pentium processors and gcc. Note that this
* instruction is actually very slow on some processors (e.g., family 5,
* model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
* implementation instead.
*/
static INLINE uint32 find_msbit(uint32 x)
{
uint msbit;
__asm__("bsrl %1,%0":"=r"(msbit)
: "r"(x));
return msbit;
}
#else /* !USE_PENTIUM_BSR || !__GNUC__ */
/*
* Generic Implementation
*/
#define DB_POW_MASK16 0xffff0000
#define DB_POW_MASK8 0x0000ff00
#define DB_POW_MASK4 0x000000f0
#define DB_POW_MASK2 0x0000000c
#define DB_POW_MASK1 0x00000002
static INLINE uint32 find_msbit(uint32 x)
{
uint32 temp_x = x;
uint msbit = 0;
if (temp_x & DB_POW_MASK16) {
temp_x >>= 16;
msbit = 16;
}
if (temp_x & DB_POW_MASK8) {
temp_x >>= 8;
msbit += 8;
}
if (temp_x & DB_POW_MASK4) {
temp_x >>= 4;
msbit += 4;
}
if (temp_x & DB_POW_MASK2) {
temp_x >>= 2;
msbit += 2;
}
if (temp_x & DB_POW_MASK1) {
msbit += 1;
}
return (msbit);
}
#endif /* USE_PENTIUM_BSR && __GNUC__ */
#endif /* _BITFUNCS_H */
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _epivers_h_
#define _epivers_h_
#define EPI_MAJOR_VERSION 5
#define EPI_MINOR_VERSION 75
#define EPI_RC_NUMBER 11
#define EPI_INCREMENTAL_NUMBER 0
#define EPI_BUILD_NUMBER 1
#define EPI_VERSION 5, 75, 11, 0
#ifdef BCMSDIO
/* EPI_VERSION_NUM must match FW version */
#define EPI_VERSION_NUM 0x054b0c00
#else
#define EPI_VERSION_NUM 0x054b0b00
#endif
#define EPI_VERSION_DEV 5.75.11
/* Driver Version String, ASCII, 32 chars max */
#define EPI_VERSION_STR "5.75.11"
#endif /* _epivers_h_ */
drivers/staging/brcm80211/include/hnddma.h 0 → 100644
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drivers/staging/brcm80211/include/hndpmu.h 0 → 100644
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _hndpmu_h_
#define _hndpmu_h_
#define SET_LDO_VOLTAGE_LDO1 1
#define SET_LDO_VOLTAGE_LDO2 2
#define SET_LDO_VOLTAGE_LDO3 3
#define SET_LDO_VOLTAGE_PAREF 4
#define SET_LDO_VOLTAGE_CLDO_PWM 5
#define SET_LDO_VOLTAGE_CLDO_BURST 6
#define SET_LDO_VOLTAGE_CBUCK_PWM 7
#define SET_LDO_VOLTAGE_CBUCK_BURST 8
#define SET_LDO_VOLTAGE_LNLDO1 9
#define SET_LDO_VOLTAGE_LNLDO2_SEL 10
extern void si_pmu_init(si_t * sih, osl_t * osh);
extern void si_pmu_chip_init(si_t * sih, osl_t * osh);
extern void si_pmu_pll_init(si_t * sih, osl_t * osh, uint32 xtalfreq);
extern void si_pmu_res_init(si_t * sih, osl_t * osh);
extern void si_pmu_swreg_init(si_t * sih, osl_t * osh);
extern uint32 si_pmu_force_ilp(si_t * sih, osl_t * osh, bool force);
extern uint32 si_pmu_si_clock(si_t * sih, osl_t * osh);
extern uint32 si_pmu_cpu_clock(si_t * sih, osl_t * osh);
extern uint32 si_pmu_mem_clock(si_t * sih, osl_t * osh);
extern uint32 si_pmu_alp_clock(si_t * sih, osl_t * osh);
extern uint32 si_pmu_ilp_clock(si_t * sih, osl_t * osh);
extern void si_pmu_set_switcher_voltage(si_t * sih, osl_t * osh,
uint8 bb_voltage, uint8 rf_voltage);
extern void si_pmu_set_ldo_voltage(si_t * sih, osl_t * osh, uint8 ldo,
uint8 voltage);
extern uint16 si_pmu_fast_pwrup_delay(si_t * sih, osl_t * osh);
extern void si_pmu_rcal(si_t * sih, osl_t * osh);
extern void si_pmu_pllupd(si_t * sih);
extern void si_pmu_spuravoid(si_t * sih, osl_t * osh, uint8 spuravoid);
extern bool si_pmu_is_otp_powered(si_t * sih, osl_t * osh);
extern uint32 si_pmu_measure_alpclk(si_t * sih, osl_t * osh);
extern uint32 si_pmu_chipcontrol(si_t * sih, uint reg, uint32 mask, uint32 val);
extern uint32 si_pmu_regcontrol(si_t * sih, uint reg, uint32 mask, uint32 val);
extern uint32 si_pmu_pllcontrol(si_t * sih, uint reg, uint32 mask, uint32 val);
extern void si_pmu_pllupd(si_t * sih);
extern void si_pmu_sprom_enable(si_t * sih, osl_t * osh, bool enable);
extern void si_pmu_radio_enable(si_t * sih, bool enable);
extern uint32 si_pmu_waitforclk_on_backplane(si_t * sih, osl_t * osh,
uint32 clk, uint32 delay);
extern void si_pmu_otp_power(si_t * sih, osl_t * osh, bool on);
extern void si_sdiod_drive_strength_init(si_t * sih, osl_t * osh,
uint32 drivestrength);
#endif /* _hndpmu_h_ */
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _hndtcam_h_
#define _hndtcam_h_
/*
* 0 - 1
* 1 - 2 Consecutive locations are patched
* 2 - 4 Consecutive locations are patched
* 3 - 8 Consecutive locations are patched
* 4 - 16 Consecutive locations are patched
* Define default to patch 2 locations
*/
#define PATCHCOUNT 0
#define SRPC_PATCHCOUNT PATCHCOUNT
/* N Consecutive location to patch */
#define SRPC_PATCHNLOC (1 << (SRPC_PATCHCOUNT))
/* patch values and address structure */
typedef struct patchaddrvalue {
uint32 addr;
uint32 value;
} patchaddrvalue_t;
extern void hnd_patch_init(void *srp);
extern void hnd_tcam_write(void *srp, uint16 index, uint32 data);
extern void hnd_tcam_read(void *srp, uint16 index, uint32 * content);
void *hnd_tcam_init(void *srp, uint no_addrs);
extern void hnd_tcam_disablepatch(void *srp);
extern void hnd_tcam_enablepatch(void *srp);
extern void hnd_tcam_load(void *srp, const patchaddrvalue_t * patchtbl);
#endif /* _hndtcam_h_ */
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