drm/amd/display: Remove dc_target object

dc_target does not fit well into DRM framework so removed it.
This will prevent the driver from leveraging the pipe-split
code for tiled displays, so will have to be handled at a higher
level.  Most places that used dc_target now directly use dc_stream
instead.
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

@@ -428,8 +428,8 @@ struct amdgpu_crtc {
 
 	int otg_inst;
 	uint32_t flip_flags;
-	/* After Set Mode target will be non-NULL */
-	struct dc_target *target;
+	/* After Set Mode stream will be non-NULL */
+	const struct dc_stream *stream;
 };
 
 struct amdgpu_encoder_atom_dig {
@@ -550,7 +550,7 @@ struct amdgpu_connector {
 	const struct dc_sink *dc_sink;
 	const struct dc_link *dc_link;
 	const struct dc_sink *dc_em_sink;
-	const struct dc_target *target;
+	const struct dc_stream *stream;
 	void *con_priv;
 	bool dac_load_detect;
 	bool detected_by_load; /* if the connection status was determined by load */

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

@@ -68,12 +68,12 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 	else {
 		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 
-		if (NULL == acrtc->target) {
-			DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc);
+		if (NULL == acrtc->stream) {
+			DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc);
 			return 0;
 		}
 
-		return dc_target_get_vblank_counter(acrtc->target);
+		return dc_stream_get_vblank_counter(acrtc->stream);
 	}
 }
 
@@ -85,12 +85,12 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 	else {
 		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 
-		if (NULL == acrtc->target) {
-			DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc);
+		if (NULL == acrtc->stream) {
+			DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc);
 			return 0;
 		}
 
-		return dc_target_get_scanoutpos(acrtc->target, vbl, position);
+		return dc_stream_get_scanoutpos(acrtc->stream, vbl, position);
 	}
 
 	return 0;
@@ -461,7 +461,7 @@ static int dm_suspend(void *handle)
 	drm_modeset_lock_all(adev->ddev);
 	list_for_each_entry(crtc, &adev->ddev->mode_config.crtc_list, head) {
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-		if (acrtc->target)
+		if (acrtc->stream)
 				drm_crtc_vblank_off(crtc);
 	}
 	drm_modeset_unlock_all(adev->ddev);
@@ -655,7 +655,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 	drm_modeset_lock_all(ddev);
 	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-		if (acrtc->target)
+		if (acrtc->stream)
 				drm_crtc_vblank_on(crtc);
 	}
 	drm_modeset_unlock_all(ddev);
@@ -740,7 +740,7 @@ void amdgpu_dm_update_connector_after_detect(
 	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
 			&& aconnector->dc_em_sink) {
 
-		/* For S3 resume with headless use eml_sink to fake target
+		/* For S3 resume with headless use eml_sink to fake stream
 		 * because on resume connecotr->sink is set ti NULL
 		 */
 		mutex_lock(&dev->mode_config.mutex);
@@ -1184,7 +1184,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		return -1;
 	}
 
-	for (i = 0; i < dm->dc->caps.max_targets; i++) {
+	for (i = 0; i < dm->dc->caps.max_streams; i++) {
 		acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
 		if (!acrtc)
 			goto fail;
@@ -1199,7 +1199,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		}
 	}
 
-	dm->display_indexes_num = dm->dc->caps.max_targets;
+	dm->display_indexes_num = dm->dc->caps.max_streams;
 
 	/* loops over all connectors on the board */
 	for (i = 0; i < link_cnt; i++) {
@@ -1318,7 +1318,7 @@ static void dm_page_flip(struct amdgpu_device *adev,
 			 int crtc_id, u64 crtc_base, bool async)
 {
 	struct amdgpu_crtc *acrtc;
-	struct dc_target *target;
+	const struct dc_stream *stream;
 	struct dc_flip_addrs addr = { {0} };
 
 	/*
@@ -1336,7 +1336,7 @@ static void dm_page_flip(struct amdgpu_device *adev,
 	 * a little longer to lock up all cores.
 	 *
 	 * The reason we should lock on dal_mutex is so that we can be sure
-	 * nobody messes with acrtc->target after we read and check its value.
+	 * nobody messes with acrtc->stream after we read and check its value.
 	 *
 	 * We might be able to fix our concurrency issues with a work queue
 	 * where we schedule all work items (mode_set, page_flip, etc.) and
@@ -1345,14 +1345,14 @@ static void dm_page_flip(struct amdgpu_device *adev,
 	 */
 
 	acrtc = adev->mode_info.crtcs[crtc_id];
-	target = acrtc->target;
+	stream = acrtc->stream;
 
 	/*
 	 * Received a page flip call after the display has been reset.
 	 * Just return in this case. Everything should be clean-up on reset.
 	 */
 
-	if (!target) {
+	if (!stream) {
 		WARN_ON(1);
 		return;
 	}
@@ -1368,7 +1368,7 @@ static void dm_page_flip(struct amdgpu_device *adev,
 
 	dc_flip_surface_addrs(
 			adev->dm.dc,
-			dc_target_get_status(target)->surfaces,
+			dc_stream_get_status(stream)->surfaces,
 			&addr, 1);
 }
 
@@ -1376,25 +1376,22 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
 				struct drm_file *filp)
 {
 	struct mod_freesync_params freesync_params;
-	uint8_t num_targets;
+	uint8_t num_streams;
 	uint8_t i;
-	struct dc_target *target;
 
 	struct amdgpu_device *adev = dev->dev_private;
 	int r = 0;
 
 	/* Get freesync enable flag from DRM */
 
-	num_targets = dc_get_current_target_count(adev->dm.dc);
+	num_streams = dc_get_current_stream_count(adev->dm.dc);
 
-	for (i = 0; i < num_targets; i++) {
-
-		target = dc_get_target_at_index(adev->dm.dc, i);
+	for (i = 0; i < num_streams; i++) {
+		const struct dc_stream *stream;
+		stream = dc_get_stream_at_index(adev->dm.dc, i);
 
 		mod_freesync_update_state(adev->dm.freesync_module,
-						target->streams,
-						target->stream_count,
-						&freesync_params);
+					  &stream, 1, &freesync_params);
 	}
 
 	return r;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h

@@ -59,7 +59,7 @@ int amdgpu_dm_atomic_commit(
 int amdgpu_dm_atomic_check(struct drm_device *dev,
 				struct drm_atomic_state *state);
 
-int dm_create_validation_set_for_target(
+int dm_create_validation_set_for_stream(
 	struct drm_connector *connector,
 	struct drm_display_mode *mode,
 	struct dc_validation_set *val_set);

drivers/gpu/drm/amd/display/dc/Makefile

@@ -13,7 +13,7 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI
 
 include $(AMD_DC)
 
-DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_target.o dc_sink.o \
+DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
 dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
 
 AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

@@ -27,6 +27,8 @@
 #include "dc.h"
 #include "core_types.h"
 #include "resource.h"
+#include "ipp.h"
+#include "timing_generator.h"
 
 /*******************************************************************************
  * Private definitions
@@ -146,3 +148,184 @@ struct dc_stream *dc_create_stream_for_sink(
 alloc_fail:
 	return NULL;
 }
+
+const struct dc_stream_status *dc_stream_get_status(
+	const struct dc_stream *dc_stream)
+{
+	uint8_t i;
+	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
+	struct core_dc *dc = DC_TO_CORE(stream->ctx->dc);
+
+	for (i = 0; i < dc->current_context->stream_count; i++)
+		if (stream == dc->current_context->streams[i])
+			return &dc->current_context->stream_status[i];
+
+	return NULL;
+}
+
+/**
+ * Update the cursor attributes and set cursor surface address
+ */
+bool dc_stream_set_cursor_attributes(
+	const struct dc_stream *dc_stream,
+	const struct dc_cursor_attributes *attributes)
+{
+	int i;
+	struct core_stream *stream;
+	struct core_dc *core_dc;
+	struct resource_context *res_ctx;
+	bool ret = false;
+
+	if (NULL == dc_stream) {
+		dm_error("DC: dc_stream is NULL!\n");
+			return false;
+	}
+	if (NULL == attributes) {
+		dm_error("DC: attributes is NULL!\n");
+			return false;
+	}
+
+	stream = DC_STREAM_TO_CORE(dc_stream);
+	core_dc = DC_TO_CORE(stream->ctx->dc);
+	res_ctx = &core_dc->current_context->res_ctx;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+
+		if (pipe_ctx->stream == stream) {
+			struct input_pixel_processor *ipp = pipe_ctx->ipp;
+
+			if (ipp->funcs->ipp_cursor_set_attributes(
+				ipp, attributes))
+				ret = true;
+		}
+	}
+
+	return ret;
+}
+
+bool dc_stream_set_cursor_position(
+	const struct dc_stream *dc_stream,
+	const struct dc_cursor_position *position)
+{
+	int i;
+	struct core_stream *stream;
+	struct core_dc *core_dc;
+	struct resource_context *res_ctx;
+	bool ret = false;
+
+	if (NULL == dc_stream) {
+		dm_error("DC: dc_stream is NULL!\n");
+		return false;
+	}
+
+	if (NULL == position) {
+		dm_error("DC: cursor position is NULL!\n");
+		return false;
+	}
+
+	stream = DC_STREAM_TO_CORE(dc_stream);
+	core_dc = DC_TO_CORE(stream->ctx->dc);
+	res_ctx = &core_dc->current_context->res_ctx;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+
+		if (pipe_ctx->stream == stream) {
+			struct input_pixel_processor *ipp = pipe_ctx->ipp;
+			struct dc_cursor_mi_param param = {
+				.pixel_clk_khz = dc_stream->timing.pix_clk_khz,
+				.ref_clk_khz = 48000,/*todo refclk*/
+				.viewport_x_start = pipe_ctx->scl_data.viewport.x,
+				.viewport_width = pipe_ctx->scl_data.viewport.width,
+				.h_scale_ratio = pipe_ctx->scl_data.ratios.horz,
+			};
+
+			ipp->funcs->ipp_cursor_set_position(ipp, position, &param);
+			ret = true;
+		}
+	}
+
+	return ret;
+}
+
+uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream)
+{
+	uint8_t i;
+	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
+	struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc);
+	struct resource_context *res_ctx =
+		&core_dc->current_context->res_ctx;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct timing_generator *tg = res_ctx->pipe_ctx[i].tg;
+
+		if (res_ctx->pipe_ctx[i].stream != stream)
+			continue;
+
+		return tg->funcs->get_frame_count(tg);
+	}
+
+	return 0;
+}
+
+uint32_t dc_stream_get_scanoutpos(
+		const struct dc_stream *dc_stream,
+		uint32_t *vbl,
+		uint32_t *position)
+{
+	uint8_t i;
+	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
+	struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc);
+	struct resource_context *res_ctx =
+		&core_dc->current_context->res_ctx;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct timing_generator *tg = res_ctx->pipe_ctx[i].tg;
+
+		if (res_ctx->pipe_ctx[i].stream != stream)
+			continue;
+
+		return tg->funcs->get_scanoutpos(tg, vbl, position);
+	}
+
+	return 0;
+}
+
+
+void dc_stream_log(
+	const struct dc_stream *stream,
+	struct dal_logger *dm_logger,
+	enum dc_log_type log_type)
+{
+	const struct core_stream *core_stream =
+		DC_STREAM_TO_CORE(stream);
+
+	dm_logger_write(dm_logger,
+			log_type,
+			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n",
+			core_stream,
+			core_stream->public.src.x,
+			core_stream->public.src.y,
+			core_stream->public.src.width,
+			core_stream->public.src.height,
+			core_stream->public.dst.x,
+			core_stream->public.dst.y,
+			core_stream->public.dst.width,
+			core_stream->public.dst.height);
+	dm_logger_write(dm_logger,
+			log_type,
+			"\tpix_clk_khz: %d, h_total: %d, v_total: %d\n",
+			core_stream->public.timing.pix_clk_khz,
+			core_stream->public.timing.h_total,
+			core_stream->public.timing.v_total);
+	dm_logger_write(dm_logger,
+			log_type,
+			"\tsink name: %s, serial: %d\n",
+			core_stream->sink->public.edid_caps.display_name,
+			core_stream->sink->public.edid_caps.serial_number);
+	dm_logger_write(dm_logger,
+			log_type,
+			"\tlink: %d\n",
+			core_stream->sink->link->public.link_index);
+}

drivers/gpu/drm/amd/display/dc/core/dc_target.c

-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "core_types.h"
-#include "hw_sequencer.h"
-#include "resource.h"
-#include "ipp.h"
-#include "timing_generator.h"
-
-struct target {
-	struct core_target protected;
-	int ref_count;
-};
-
-#define DC_TARGET_TO_TARGET(dc_target) \
-	container_of(dc_target, struct target, protected.public)
-#define CORE_TARGET_TO_TARGET(core_target) \
-	container_of(core_target, struct target, protected)
-
-static void construct(
-	struct core_target *target,
-	struct dc_context *ctx,
-	struct dc_stream *dc_streams[],
-	uint8_t stream_count)
-{
-	uint8_t i;
-	for (i = 0; i < stream_count; i++) {
-		target->public.streams[i] = dc_streams[i];
-		dc_stream_retain(dc_streams[i]);
-	}
-
-	target->ctx = ctx;
-	target->public.stream_count = stream_count;
-}
-
-static void destruct(struct core_target *core_target)
-{
-	int i;
-
-	for (i = 0; i < core_target->public.stream_count; i++) {
-		dc_stream_release(
-			(struct dc_stream *)core_target->public.streams[i]);
-		core_target->public.streams[i] = NULL;
-	}
-}
-
-void dc_target_retain(const struct dc_target *dc_target)
-{
-	struct target *target = DC_TARGET_TO_TARGET(dc_target);
-
-	ASSERT(target->ref_count > 0);
-	target->ref_count++;
-}
-
-void dc_target_release(const struct dc_target *dc_target)
-{
-	struct target *target = DC_TARGET_TO_TARGET(dc_target);
-	struct core_target *protected = DC_TARGET_TO_CORE(dc_target);
-
-	ASSERT(target->ref_count > 0);
-	target->ref_count--;
-
-	if (target->ref_count == 0) {
-		destruct(protected);
-		dm_free(target);
-	}
-}
-
-const struct dc_target_status *dc_target_get_status(
-					const struct dc_target* dc_target)
-{
-	uint8_t i;
-	struct core_target* target = DC_TARGET_TO_CORE(dc_target);
-	struct core_dc *dc = DC_TO_CORE(target->ctx->dc);
-
-	for (i = 0; i < dc->current_context->target_count; i++)
-		if (target == dc->current_context->targets[i])
-			return &dc->current_context->target_status[i];
-
-	return NULL;
-}
-
-struct dc_target *dc_create_target_for_streams(
-		struct dc_stream *dc_streams[],
-		uint8_t stream_count)
-{
-	struct core_stream *stream;
-	struct target *target;
-
-	if (0 == stream_count)
-		goto target_alloc_fail;
-
-	stream = DC_STREAM_TO_CORE(dc_streams[0]);
-
-	target = dm_alloc(sizeof(struct target));
-
-	if (NULL == target)
-		goto target_alloc_fail;
-
-	construct(&target->protected, stream->ctx, dc_streams, stream_count);
-
-	target->ref_count++;
-
-	return &target->protected.public;
-
-target_alloc_fail:
-	return NULL;
-}
-
-bool dc_target_is_connected_to_sink(
-		const struct dc_target * dc_target,
-		const struct dc_sink *dc_sink)
-{
-	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-	uint8_t i;
-	for (i = 0; i < target->public.stream_count; i++) {
-		if (target->public.streams[i]->sink == dc_sink)
-			return true;
-	}
-	return false;
-}
-
-/**
- * Update the cursor attributes and set cursor surface address
- */
-bool dc_target_set_cursor_attributes(
-	struct dc_target *dc_target,
-	const struct dc_cursor_attributes *attributes)
-{
-	int i, j;
-	struct core_target *target;
-	struct core_dc *core_dc;
-	struct resource_context *res_ctx;
-	bool ret = false;
-
-	if (NULL == dc_target) {
-		dm_error("DC: dc_target is NULL!\n");
-			return false;
-	}
-	if (NULL == attributes) {
-		dm_error("DC: attributes is NULL!\n");
-			return false;
-	}
-
-	target = DC_TARGET_TO_CORE(dc_target);
-	core_dc = DC_TO_CORE(target->ctx->dc);
-	res_ctx = &core_dc->current_context->res_ctx;
-
-	for (i = 0; i < dc_target->stream_count; i++) {
-		const struct dc_stream *stream = dc_target->streams[i];
-
-		for (j = 0; j < MAX_PIPES; j++) {
-			struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j];
-
-			if (&pipe_ctx->stream->public == stream) {
-				struct input_pixel_processor *ipp = pipe_ctx->ipp;
-
-				if (ipp->funcs->ipp_cursor_set_attributes(
-						ipp, attributes))
-					ret = true;
-			}
-		}
-	}
-
-	return ret;
-}
-
-bool dc_target_set_cursor_position(
-	struct dc_target *dc_target,
-	const struct dc_cursor_position *position)
-{
-	int i, j;
-	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-	struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc);
-	struct resource_context *res_ctx = &core_dc->current_context->res_ctx;
-	bool ret = false;
-
-	if (NULL == dc_target) {
-		dm_error("DC: dc_target is NULL!\n");
-		return false;
-	}
-
-	if (NULL == position) {
-		dm_error("DC: cursor position is NULL!\n");
-		return false;
-	}
-
-	for (i = 0; i < dc_target->stream_count; i++) {
-		const struct dc_stream *stream = dc_target->streams[i];
-
-		for (j = 0; j < MAX_PIPES; j++) {
-			struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j];
-
-			if (&pipe_ctx->stream->public == stream) {
-				struct input_pixel_processor *ipp = pipe_ctx->ipp;
-				struct dc_cursor_mi_param param = {
-					.pixel_clk_khz = stream->timing.pix_clk_khz,
-					.ref_clk_khz = 48000,/*todo refclk*/
-					.viewport_x_start = pipe_ctx->scl_data.viewport.x,
-					.viewport_width = pipe_ctx->scl_data.viewport.width,
-					.h_scale_ratio = pipe_ctx->scl_data.ratios.horz,
-				};
-
-				ipp->funcs->ipp_cursor_set_position(ipp, position, &param);
-				ret = true;
-			}
-		}
-	}
-
-	return ret;
-}
-
-uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
-{
-	uint8_t i, j;
-	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-	struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc);
-	struct resource_context *res_ctx =
-		&core_dc->current_context->res_ctx;
-
-	for (i = 0; i < target->public.stream_count; i++) {
-		for (j = 0; j < MAX_PIPES; j++) {
-			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
-
-			if (res_ctx->pipe_ctx[j].stream !=
-				DC_STREAM_TO_CORE(target->public.streams[i]))
-				continue;
-
-			return tg->funcs->get_frame_count(tg);
-		}
-	}
-
-	return 0;
-}
-
-uint32_t dc_target_get_scanoutpos(
-		const struct dc_target *dc_target,
-		uint32_t *vbl,
-		uint32_t *position)
-{
-	uint8_t i, j;
-	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-	struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc);
-	struct resource_context *res_ctx =
-		&core_dc->current_context->res_ctx;
-
-	for (i = 0; i < target->public.stream_count; i++) {
-		for (j = 0; j < MAX_PIPES; j++) {
-			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
-
-			if (res_ctx->pipe_ctx[j].stream !=
-				DC_STREAM_TO_CORE(target->public.streams[i]))
-				continue;
-
-			return tg->funcs->get_scanoutpos(tg, vbl, position);
-		}
-	}
-
-	return 0;
-}
-
-void dc_target_log(
-	const struct dc_target *dc_target,
-	struct dal_logger *dm_logger,
-	enum dc_log_type log_type)
-{
-	int i;
-
-	const struct core_target *core_target =
-			CONST_DC_TARGET_TO_CORE(dc_target);
-
-	dm_logger_write(dm_logger,
-			log_type,
-			"core_target 0x%x: stream_count=%d\n",
-			core_target,
-			core_target->public.stream_count);
-
-	for (i = 0; i < core_target->public.stream_count; i++) {
-		const struct core_stream *core_stream =
-			DC_STREAM_TO_CORE(core_target->public.streams[i]);
-
-		dm_logger_write(dm_logger,
-			log_type,
-			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n",
-			core_stream,
-			core_stream->public.src.x,
-			core_stream->public.src.y,
-			core_stream->public.src.width,
-			core_stream->public.src.height,
-			core_stream->public.dst.x,
-			core_stream->public.dst.y,
-			core_stream->public.dst.width,
-			core_stream->public.dst.height);
-		dm_logger_write(dm_logger,
-			log_type,
-			"\tpix_clk_khz: %d, h_total: %d, v_total: %d\n",
-			core_stream->public.timing.pix_clk_khz,
-			core_stream->public.timing.h_total,
-			core_stream->public.timing.v_total);
-		dm_logger_write(dm_logger,
-			log_type,
-			"\tsink name: %s, serial: %d\n",
-			core_stream->sink->public.edid_caps.display_name,
-			core_stream->sink->public.edid_caps.serial_number);
-		dm_logger_write(dm_logger,
-			log_type,
-			"\tlink: %d\n",
-			core_stream->sink->link->public.link_index);
-	}
-}

drivers/gpu/drm/amd/display/dc/dc.h

@@ -32,8 +32,8 @@
 #include "gpio_types.h"
 #include "link_service_types.h"
 
-#define MAX_TARGETS 6
 #define MAX_SURFACES 3
+#define MAX_STREAMS 6
 #define MAX_SINKS_PER_LINK 4
 
 /*******************************************************************************
@@ -41,7 +41,7 @@
  ******************************************************************************/
 
 struct dc_caps {
-	uint32_t max_targets;
+	uint32_t max_streams;
 	uint32_t max_links;
 	uint32_t max_audios;
 	uint32_t max_slave_planes;
@@ -139,7 +139,6 @@ struct dc_config {
 struct dc_debug {
 	bool surface_visual_confirm;
 	bool max_disp_clk;
-	bool target_trace;
 	bool surface_trace;
 	bool timing_trace;
 	bool validation_trace;
@@ -351,95 +350,91 @@ void dc_flip_surface_addrs(struct dc *dc,
 		uint32_t count);
 
 /*
- * Set up surface attributes and associate to a target
- * The surfaces parameter is an absolute set of all surface active for the target.
- * If no surfaces are provided, the target will be blanked; no memory read.
+ * Set up surface attributes and associate to a stream
+ * The surfaces parameter is an absolute set of all surface active for the stream.
+ * If no surfaces are provided, the stream will be blanked; no memory read.
  * Any flip related attribute changes must be done through this interface.
  *
  * After this call:
- *   Surfaces attributes are programmed and configured to be composed into target.
+ *   Surfaces attributes are programmed and configured to be composed into stream.
  *   This does not trigger a flip.  No surface address is programmed.
  */
 
-bool dc_commit_surfaces_to_target(
+bool dc_commit_surfaces_to_stream(
 		struct dc *dc,
 		const struct dc_surface **dc_surfaces,
 		uint8_t surface_count,
-		struct dc_target *dc_target);
+		const struct dc_stream *stream);
 
-bool dc_pre_update_surfaces_to_target(
+bool dc_pre_update_surfaces_to_stream(
 		struct dc *dc,
 		const struct dc_surface *const *new_surfaces,
 		uint8_t new_surface_count,
-		struct dc_target *dc_target);
+		const struct dc_stream *stream);
 
-bool dc_post_update_surfaces_to_target(
+bool dc_post_update_surfaces_to_stream(
 		struct dc *dc);
 
-void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *updates,
-		int surface_count, struct dc_target *dc_target);
+void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates,
+		int surface_count, const struct dc_stream *stream);
 
 /*******************************************************************************
- * Target Interfaces
+ * Stream Interfaces
  ******************************************************************************/
-#define MAX_STREAM_NUM 1
+struct dc_stream {
+	const struct dc_sink *sink;
+	struct dc_crtc_timing timing;
 
-struct dc_target {
-	uint8_t stream_count;
-	const struct dc_stream *streams[MAX_STREAM_NUM];
-};
+	enum dc_color_space output_color_space;
 
-/*
- * Target status is returned from dc_target_get_status in order to get the
- * the IRQ source, current frame counter and currently attached surfaces.
- */
-struct dc_target_status {
-	int primary_otg_inst;
-	int cur_frame_count;
-	int surface_count;
-	const struct dc_surface *surfaces[MAX_SURFACE_NUM];
-};
+	struct rect src; /* composition area */
+	struct rect dst; /* stream addressable area */
 
-struct dc_target *dc_create_target_for_streams(
-		struct dc_stream *dc_streams[],
-		uint8_t stream_count);
+	struct audio_info audio_info;
+
+	bool ignore_msa_timing_param;
+
+	struct freesync_context freesync_ctx;
+
+	const struct dc_transfer_func *out_transfer_func;
+	struct colorspace_transform gamut_remap_matrix;
+	struct csc_transform csc_color_matrix;
+
+	/* TODO: dithering */
+	/* TODO: custom INFO packets */
+	/* TODO: ABM info (DMCU) */
+	/* TODO: PSR info */
+	/* TODO: CEA VIC */
+};
 
 /*
- * Get the current target status.
+ * Log the current stream state.
  */
-const struct dc_target_status *dc_target_get_status(
-					const struct dc_target* dc_target);
-
-void dc_target_retain(const struct dc_target *dc_target);
-void dc_target_release(const struct dc_target *dc_target);
-void dc_target_log(
-	const struct dc_target *dc_target,
+void dc_stream_log(
+	const struct dc_stream *stream,
 	struct dal_logger *dc_logger,
 	enum dc_log_type log_type);
 
-uint8_t dc_get_current_target_count(const struct dc *dc);
-struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i);
+uint8_t dc_get_current_stream_count(const struct dc *dc);
+struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i);
 
-bool dc_target_is_connected_to_sink(
-		const struct dc_target *dc_target,
-		const struct dc_sink *dc_sink);
-
-uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target);
+/*
+ * Return the current frame counter.
+ */
+uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream);
 
 /* TODO: Return parsed values rather than direct register read
  * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
  * being refactored properly to be dce-specific
  */
-uint32_t dc_target_get_scanoutpos(
-		const struct dc_target *dc_target,
-		uint32_t *vbl,
-		uint32_t *position);
+uint32_t dc_stream_get_scanoutpos(
+		const struct dc_stream *stream, uint32_t *vbl, uint32_t *position);
 
 /*
- * Structure to store surface/target associations for validation
+ * Structure to store surface/stream associations for validation
  */
 struct dc_validation_set {
-	const struct dc_target *target;
+	const struct dc_stream *stream;
 	const struct dc_surface *surfaces[MAX_SURFACES];
 	uint8_t surface_count;
 };
@@ -456,8 +451,8 @@ bool dc_validate_resources(
 		uint8_t set_count);
 
 /*
- * This function takes a target and checks if it is guaranteed to be supported.
- * Guaranteed means that MAX_COFUNC*target is supported.
+ * This function takes a stream and checks if it is guaranteed to be supported.
+ * Guaranteed means that MAX_COFUNC similar streams are supported.
  *
  * After this call:
  *   No hardware is programmed for call.  Only validation is done.
@@ -465,49 +460,20 @@ bool dc_validate_resources(
 
 bool dc_validate_guaranteed(
 		const struct dc *dc,
-		const struct dc_target *dc_target);
+		const struct dc_stream *stream);
 
 /*
- * Set up streams and links associated to targets to drive sinks
- * The targets parameter is an absolute set of all active targets.
+ * Set up streams and links associated to drive sinks
+ * The streams parameter is an absolute set of all active streams.
  *
  * After this call:
  *   Phy, Encoder, Timing Generator are programmed and enabled.
- *   New targets are enabled with blank stream; no memory read.
+ *   New streams are enabled with blank stream; no memory read.
  */
-bool dc_commit_targets(
+bool dc_commit_streams(
 		struct dc *dc,
-		struct dc_target *targets[],
-		uint8_t target_count);
-
-/*******************************************************************************
- * Stream Interfaces
- ******************************************************************************/
-struct dc_stream {
-	const struct dc_sink *sink;
-	struct dc_crtc_timing timing;
-
-	enum dc_color_space output_color_space;
-
-	struct rect src; /* viewport in target space*/
-	struct rect dst; /* stream addressable area */
-
-	struct audio_info audio_info;
-
-	bool ignore_msa_timing_param;
-
-	struct freesync_context freesync_ctx;
-
-	const struct dc_transfer_func *out_transfer_func;
-	struct colorspace_transform gamut_remap_matrix;
-	struct csc_transform csc_color_matrix;
-
-	/* TODO: dithering */
-	/* TODO: custom INFO packets */
-	/* TODO: ABM info (DMCU) */
-	/* TODO: PSR info */
-	/* TODO: CEA VIC */
-};
+		const struct dc_stream *streams[],
+		uint8_t stream_count);
 
 /**
  * Create a new default stream for the requested sink
@@ -518,6 +484,10 @@ void dc_stream_retain(const struct dc_stream *dc_stream);
 void dc_stream_release(const struct dc_stream *dc_stream);
 
 struct dc_stream_status {
+	int primary_otg_inst;
+	int surface_count;
+	const struct dc_surface *surfaces[MAX_SURFACE_NUM];
+
 	/*
 	 * link this stream passes through
 	 */
@@ -691,15 +661,15 @@ struct dc_sink_init_data {
 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
 
 /*******************************************************************************
- * Cursor interfaces - To manages the cursor within a target
+ * Cursor interfaces - To manages the cursor within a stream
  ******************************************************************************/
 /* TODO: Deprecated once we switch to dc_set_cursor_position */
-bool dc_target_set_cursor_attributes(
-	struct dc_target *dc_target,
+bool dc_stream_set_cursor_attributes(
+	const struct dc_stream *stream,
 	const struct dc_cursor_attributes *attributes);
 
-bool dc_target_set_cursor_position(
-	struct dc_target *dc_target,
+bool dc_stream_set_cursor_position(
+	const struct dc_stream *stream,
 	const struct dc_cursor_position *position);
 
 /* Newer interfaces  */
@@ -708,36 +678,6 @@ struct dc_cursor {
 	struct dc_cursor_attributes attributes;
 };
 
-/*
- * Create a new cursor with default values for a given target.
- */
-struct dc_cursor *dc_create_cursor_for_target(
-		const struct dc *dc,
-		struct dc_target *dc_target);
-
-/**
- * Commit cursor attribute changes such as pixel format and dimensions and
- * surface address.
- *
- * After this call:
- *   Cursor address and format is programmed to the new values.
- *   Cursor position is unmodified.
- */
-bool dc_commit_cursor(
-		const struct dc *dc,
-		struct dc_cursor *cursor);
-
-/*
- * Optimized cursor position update
- *
- * After this call:
- *   Cursor position will be programmed as well as enable/disable bit.
- */
-bool dc_set_cursor_position(
-		const struct dc *dc,
-		struct dc_cursor *cursor,
-		struct dc_cursor_position *pos);
-
 /*******************************************************************************
  * Interrupt interfaces
  ******************************************************************************/

drivers/gpu/drm/amd/display/dc/dc_types.h

@@ -34,7 +34,6 @@
 
 /* forward declarations */
 struct dc_surface;
-struct dc_target;
 struct dc_stream;
 struct dc_link;
 struct dc_sink;

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

@@ -741,53 +741,48 @@ static enum dc_status validate_mapped_resource(
 		struct validate_context *context)
 {
 	enum dc_status status = DC_OK;
-	uint8_t i, j, k;
+	uint8_t i, j;
 
-	for (i = 0; i < context->target_count; i++) {
-		struct core_target *target = context->targets[i];
+	for (i = 0; i < context->stream_count; i++) {
+		struct core_stream *stream = context->streams[i];
+		struct core_link *link = stream->sink->link;
 
-		for (j = 0; j < target->public.stream_count; j++) {
-			struct core_stream *stream =
-				DC_STREAM_TO_CORE(target->public.streams[j]);
-			struct core_link *link = stream->sink->link;
-
-			if (resource_is_stream_unchanged(dc->current_context, stream))
-				continue;
+		if (resource_is_stream_unchanged(dc->current_context, stream))
+			continue;
 
-			for (k = 0; k < MAX_PIPES; k++) {
-				struct pipe_ctx *pipe_ctx =
-					&context->res_ctx.pipe_ctx[k];
+		for (j = 0; j < MAX_PIPES; j++) {
+			struct pipe_ctx *pipe_ctx =
+				&context->res_ctx.pipe_ctx[j];
 
-				if (context->res_ctx.pipe_ctx[k].stream != stream)
-					continue;
+			if (context->res_ctx.pipe_ctx[j].stream != stream)
+				continue;
 
-				if (!pipe_ctx->tg->funcs->validate_timing(
-						pipe_ctx->tg, &stream->public.timing))
-					return DC_FAIL_CONTROLLER_VALIDATE;
+			if (!pipe_ctx->tg->funcs->validate_timing(
+				pipe_ctx->tg, &stream->public.timing))
+				return DC_FAIL_CONTROLLER_VALIDATE;
 
-				status = dce110_resource_build_pipe_hw_param(pipe_ctx);
+			status = dce110_resource_build_pipe_hw_param(pipe_ctx);
 
-				if (status != DC_OK)
-					return status;
+			if (status != DC_OK)
+				return status;
 
-				if (!link->link_enc->funcs->validate_output_with_stream(
-						link->link_enc,
-						pipe_ctx))
-					return DC_FAIL_ENC_VALIDATE;
+			if (!link->link_enc->funcs->validate_output_with_stream(
+				link->link_enc,
+				pipe_ctx))
+				return DC_FAIL_ENC_VALIDATE;
 
-				/* TODO: validate audio ASIC caps, encoder */
-				status = dc_link_validate_mode_timing(stream,
-						link,
-						&stream->public.timing);
+			/* TODO: validate audio ASIC caps, encoder */
+			status = dc_link_validate_mode_timing(stream,
+							      link,
+							      &stream->public.timing);
 
-				if (status != DC_OK)
-					return status;
+			if (status != DC_OK)
+				return status;
 
-				resource_build_info_frame(pipe_ctx);
+			resource_build_info_frame(pipe_ctx);
 
-				/* do not need to validate non root pipes */
-				break;
-			}
+			/* do not need to validate non root pipes */
+			break;
 		}
 	}
 
@@ -818,9 +813,9 @@ static bool dce100_validate_surface_sets(
 			return false;
 
 		if (set[i].surfaces[0]->clip_rect.width
-				!= set[i].target->streams[0]->src.width
+				!= set[i].stream->src.width
 				|| set[i].surfaces[0]->clip_rect.height
-				!= set[i].target->streams[0]->src.height)
+				!= set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
@@ -846,9 +841,9 @@ enum dc_status dce100_validate_with_context(
 	context->res_ctx.pool = dc->res_pool;
 
 	for (i = 0; i < set_count; i++) {
-		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-		dc_target_retain(&context->targets[i]->public);
-		context->target_count++;
+		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
+		dc_stream_retain(&context->streams[i]->public);
+		context->stream_count++;
 	}
 
 	result = resource_map_pool_resources(dc, context);
@@ -858,7 +853,7 @@ enum dc_status dce100_validate_with_context(
 
 	if (!resource_validate_attach_surfaces(
 			set, set_count, dc->current_context, context)) {
-		DC_ERROR("Failed to attach surface to target!\n");
+		DC_ERROR("Failed to attach surface to stream!\n");
 		return DC_FAIL_ATTACH_SURFACES;
 	}
 
@@ -876,16 +871,16 @@ enum dc_status dce100_validate_with_context(
 
 enum dc_status dce100_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_target *dc_target,
+		const struct dc_stream *dc_stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
 	context->res_ctx.pool = dc->res_pool;
 
-	context->targets[0] = DC_TARGET_TO_CORE(dc_target);
-	dc_target_retain(&context->targets[0]->public);
-	context->target_count++;
+	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
+	dc_stream_retain(&context->streams[0]->public);
+	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context);
 
@@ -896,8 +891,8 @@ enum dc_status dce100_validate_guaranteed(
 		result = validate_mapped_resource(dc, context);
 
 	if (result == DC_OK) {
-		validate_guaranteed_copy_target(
-				context, dc->public.caps.max_targets);
+		validate_guaranteed_copy_streams(
+				context, dc->public.caps.max_streams);
 		result = resource_build_scaling_params_for_context(dc, context);
 	}
 

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

@@ -753,7 +753,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 					stream->public.timing.h_total,
 					stream->public.timing.v_total,
 					stream->public.timing.pix_clk_khz,
-					context->target_count);
+					context->stream_count);
 
 	return DC_OK;
 }
@@ -1055,7 +1055,7 @@ static void reset_single_pipe_hw_ctx(
 	}
 	pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
 	pipe_ctx->mi->funcs->free_mem_input(
-				pipe_ctx->mi, context->target_count);
+				pipe_ctx->mi, context->stream_count);
 	resource_unreference_clock_source(
 			&context->res_ctx, &pipe_ctx->clock_source);
 
@@ -1254,7 +1254,7 @@ enum dc_status dce110_apply_ctx_to_hw(
 	dc->hwss.reset_hw_ctx_wrap(dc, context);
 
 	/* Skip applying if no targets */
-	if (context->target_count <= 0)
+	if (context->stream_count <= 0)
 		return DC_OK;
 
 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
@@ -1761,7 +1761,7 @@ static void dce110_power_on_pipe_if_needed(
 				pipe_ctx->stream->public.timing.h_total,
 				pipe_ctx->stream->public.timing.v_total,
 				pipe_ctx->stream->public.timing.pix_clk_khz,
-				context->target_count);
+				context->stream_count);
 
 		/* TODO unhardcode*/
 		color_space_to_black_color(dc,

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

@@ -817,58 +817,53 @@ static enum dc_status validate_mapped_resource(
 		struct validate_context *context)
 {
 	enum dc_status status = DC_OK;
-	uint8_t i, j, k;
+	uint8_t i, j;
 
-	for (i = 0; i < context->target_count; i++) {
-		struct core_target *target = context->targets[i];
+	for (i = 0; i < context->stream_count; i++) {
+		struct core_stream *stream = context->streams[i];
+		struct core_link *link = stream->sink->link;
 
-		for (j = 0; j < target->public.stream_count; j++) {
-			struct core_stream *stream =
-				DC_STREAM_TO_CORE(target->public.streams[j]);
-			struct core_link *link = stream->sink->link;
-
-			if (resource_is_stream_unchanged(dc->current_context, stream))
-				continue;
+		if (resource_is_stream_unchanged(dc->current_context, stream))
+			continue;
 
-			for (k = 0; k < MAX_PIPES; k++) {
-				struct pipe_ctx *pipe_ctx =
-					&context->res_ctx.pipe_ctx[k];
+		for (j = 0; j < MAX_PIPES; j++) {
+			struct pipe_ctx *pipe_ctx =
+				&context->res_ctx.pipe_ctx[j];
 
-				if (context->res_ctx.pipe_ctx[k].stream != stream)
-					continue;
+			if (context->res_ctx.pipe_ctx[j].stream != stream)
+				continue;
 
-				if (!is_surface_pixel_format_supported(pipe_ctx,
-						context->res_ctx.pool->underlay_pipe_index))
-					return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
+			if (!is_surface_pixel_format_supported(pipe_ctx,
+							       context->res_ctx.pool->underlay_pipe_index))
+				return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
 
-				if (!pipe_ctx->tg->funcs->validate_timing(
-					pipe_ctx->tg, &stream->public.timing))
-					return DC_FAIL_CONTROLLER_VALIDATE;
+			if (!pipe_ctx->tg->funcs->validate_timing(
+				pipe_ctx->tg, &stream->public.timing))
+				return DC_FAIL_CONTROLLER_VALIDATE;
 
-				status = dce110_resource_build_pipe_hw_param(pipe_ctx);
+			status = dce110_resource_build_pipe_hw_param(pipe_ctx);
 
-				if (status != DC_OK)
-					return status;
+			if (status != DC_OK)
+				return status;
 
-				if (!link->link_enc->funcs->validate_output_with_stream(
-						link->link_enc,
-						pipe_ctx))
-					return DC_FAIL_ENC_VALIDATE;
+			if (!link->link_enc->funcs->validate_output_with_stream(
+				link->link_enc,
+				pipe_ctx))
+				return DC_FAIL_ENC_VALIDATE;
 
-				/* TODO: validate audio ASIC caps, encoder */
+			/* TODO: validate audio ASIC caps, encoder */
 
-				status = dc_link_validate_mode_timing(stream,
-						link,
-						&stream->public.timing);
+			status = dc_link_validate_mode_timing(stream,
+							      link,
+							      &stream->public.timing);
 
-				if (status != DC_OK)
-					return status;
+			if (status != DC_OK)
+				return status;
 
-				resource_build_info_frame(pipe_ctx);
+			resource_build_info_frame(pipe_ctx);
 
-				/* do not need to validate non root pipes */
-				break;
-			}
+			/* do not need to validate non root pipes */
+			break;
 		}
 	}
 
@@ -901,9 +896,9 @@ enum dc_status dce110_validate_bandwidth(
 		dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
 			"%s: %dx%d@%d Bandwidth validation failed!\n",
 			__func__,
-			context->targets[0]->public.streams[0]->timing.h_addressable,
-			context->targets[0]->public.streams[0]->timing.v_addressable,
-			context->targets[0]->public.streams[0]->timing.pix_clk_khz);
+			context->streams[0]->public.timing.h_addressable,
+			context->streams[0]->public.timing.v_addressable,
+			context->streams[0]->public.timing.pix_clk_khz);
 
 	if (memcmp(&dc->current_context->bw_results,
 			&context->bw_results, sizeof(context->bw_results))) {
@@ -972,9 +967,9 @@ static bool dce110_validate_surface_sets(
 			return false;
 
 		if (set[i].surfaces[0]->src_rect.width
-				!= set[i].target->streams[0]->src.width
+				!= set[i].stream->src.width
 				|| set[i].surfaces[0]->src_rect.height
-				!= set[i].target->streams[0]->src.height)
+				!= set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
@@ -988,7 +983,7 @@ static bool dce110_validate_surface_sets(
 					|| set[i].surfaces[1]->src_rect.height > 1080)
 				return false;
 
-			if (set[i].target->streams[0]->timing.pixel_encoding != PIXEL_ENCODING_RGB)
+			if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB)
 				return false;
 		}
 	}
@@ -1012,9 +1007,9 @@ enum dc_status dce110_validate_with_context(
 	context->res_ctx.pool = dc->res_pool;
 
 	for (i = 0; i < set_count; i++) {
-		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-		dc_target_retain(&context->targets[i]->public);
-		context->target_count++;
+		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
+		dc_stream_retain(&context->streams[i]->public);
+		context->stream_count++;
 	}
 
 	result = resource_map_pool_resources(dc, context);
@@ -1024,7 +1019,7 @@ enum dc_status dce110_validate_with_context(
 
 	if (!resource_validate_attach_surfaces(
 			set, set_count, dc->current_context, context)) {
-		DC_ERROR("Failed to attach surface to target!\n");
+		DC_ERROR("Failed to attach surface to stream!\n");
 		return DC_FAIL_ATTACH_SURFACES;
 	}
 
@@ -1042,16 +1037,16 @@ enum dc_status dce110_validate_with_context(
 
 enum dc_status dce110_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_target *dc_target,
+		const struct dc_stream *dc_stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
 	context->res_ctx.pool = dc->res_pool;
 
-	context->targets[0] = DC_TARGET_TO_CORE(dc_target);
-	dc_target_retain(&context->targets[0]->public);
-	context->target_count++;
+	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
+	dc_stream_retain(&context->streams[0]->public);
+	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context);
 
@@ -1062,8 +1057,8 @@ enum dc_status dce110_validate_guaranteed(
 		result = validate_mapped_resource(dc, context);
 
 	if (result == DC_OK) {
-		validate_guaranteed_copy_target(
-				context, dc->public.caps.max_targets);
+		validate_guaranteed_copy_streams(
+				context, dc->public.caps.max_streams);
 		result = resource_build_scaling_params_for_context(dc, context);
 	}
 

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

@@ -779,54 +779,49 @@ static enum dc_status validate_mapped_resource(
 		struct validate_context *context)
 {
 	enum dc_status status = DC_OK;
-	uint8_t i, j, k;
+	uint8_t i, j;
 
-	for (i = 0; i < context->target_count; i++) {
-		struct core_target *target = context->targets[i];
+	for (i = 0; i < context->stream_count; i++) {
+		struct core_stream *stream = context->streams[i];
+		struct core_link *link = stream->sink->link;
 
-		for (j = 0; j < target->public.stream_count; j++) {
-			struct core_stream *stream =
-				DC_STREAM_TO_CORE(target->public.streams[j]);
-			struct core_link *link = stream->sink->link;
-
-			if (resource_is_stream_unchanged(dc->current_context, stream))
-				continue;
+		if (resource_is_stream_unchanged(dc->current_context, stream))
+			continue;
 
-			for (k = 0; k < MAX_PIPES; k++) {
-				struct pipe_ctx *pipe_ctx =
-					&context->res_ctx.pipe_ctx[k];
+		for (j = 0; j < MAX_PIPES; j++) {
+			struct pipe_ctx *pipe_ctx =
+				&context->res_ctx.pipe_ctx[j];
 
-				if (context->res_ctx.pipe_ctx[k].stream != stream)
-					continue;
+			if (context->res_ctx.pipe_ctx[j].stream != stream)
+				continue;
 
-				if (!pipe_ctx->tg->funcs->validate_timing(
-						pipe_ctx->tg, &stream->public.timing))
-					return DC_FAIL_CONTROLLER_VALIDATE;
+			if (!pipe_ctx->tg->funcs->validate_timing(
+				pipe_ctx->tg, &stream->public.timing))
+				return DC_FAIL_CONTROLLER_VALIDATE;
 
-				status = dce110_resource_build_pipe_hw_param(pipe_ctx);
+			status = dce110_resource_build_pipe_hw_param(pipe_ctx);
 
-				if (status != DC_OK)
-					return status;
+			if (status != DC_OK)
+				return status;
 
-				if (!link->link_enc->funcs->validate_output_with_stream(
-						link->link_enc,
-						pipe_ctx))
-					return DC_FAIL_ENC_VALIDATE;
+			if (!link->link_enc->funcs->validate_output_with_stream(
+				link->link_enc,
+				pipe_ctx))
+				return DC_FAIL_ENC_VALIDATE;
 
-				/* TODO: validate audio ASIC caps, encoder */
+			/* TODO: validate audio ASIC caps, encoder */
 
-				status = dc_link_validate_mode_timing(stream,
-						link,
-						&stream->public.timing);
+			status = dc_link_validate_mode_timing(stream,
+							      link,
+							      &stream->public.timing);
 
-				if (status != DC_OK)
-					return status;
+			if (status != DC_OK)
+				return status;
 
-				resource_build_info_frame(pipe_ctx);
+			resource_build_info_frame(pipe_ctx);
 
-				/* do not need to validate non root pipes */
-				break;
-			}
+			/* do not need to validate non root pipes */
+			break;
 		}
 	}
 
@@ -917,45 +912,40 @@ enum dc_status resource_map_phy_clock_resources(
 		const struct core_dc *dc,
 		struct validate_context *context)
 {
-	uint8_t i, j, k;
+	uint8_t i, j;
 
 	/* acquire new resources */
-	for (i = 0; i < context->target_count; i++) {
-		struct core_target *target = context->targets[i];
+	for (i = 0; i < context->stream_count; i++) {
+		struct core_stream *stream = context->streams[i];
 
-		for (j = 0; j < target->public.stream_count; j++) {
-			struct core_stream *stream =
-				DC_STREAM_TO_CORE(target->public.streams[j]);
-
-			if (resource_is_stream_unchanged(dc->current_context, stream))
-				continue;
+		if (resource_is_stream_unchanged(dc->current_context, stream))
+			continue;
 
-			for (k = 0; k < MAX_PIPES; k++) {
-				struct pipe_ctx *pipe_ctx =
-					&context->res_ctx.pipe_ctx[k];
+		for (j = 0; j < MAX_PIPES; j++) {
+			struct pipe_ctx *pipe_ctx =
+				&context->res_ctx.pipe_ctx[j];
 
-				if (context->res_ctx.pipe_ctx[k].stream != stream)
-					continue;
+			if (context->res_ctx.pipe_ctx[j].stream != stream)
+				continue;
 
-				if (dc_is_dp_signal(pipe_ctx->stream->signal)
-					|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
-					pipe_ctx->clock_source =
-						context->res_ctx.pool->dp_clock_source;
-				else
-					pipe_ctx->clock_source =
-							find_matching_pll(&context->res_ctx,
-									stream);
+			if (dc_is_dp_signal(pipe_ctx->stream->signal)
+				|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
+				pipe_ctx->clock_source =
+					context->res_ctx.pool->dp_clock_source;
+			else
+				pipe_ctx->clock_source =
+					find_matching_pll(&context->res_ctx,
+							  stream);
 
-				if (pipe_ctx->clock_source == NULL)
-					return DC_NO_CLOCK_SOURCE_RESOURCE;
+			if (pipe_ctx->clock_source == NULL)
+				return DC_NO_CLOCK_SOURCE_RESOURCE;
 
-				resource_reference_clock_source(
-						&context->res_ctx,
-						pipe_ctx->clock_source);
+			resource_reference_clock_source(
+				&context->res_ctx,
+				pipe_ctx->clock_source);
 
-				/* only one cs per stream regardless of mpo */
-				break;
-			}
+			/* only one cs per stream regardless of mpo */
+			break;
 		}
 	}
 
@@ -976,9 +966,9 @@ static bool dce112_validate_surface_sets(
 			return false;
 
 		if (set[i].surfaces[0]->clip_rect.width
-				!= set[i].target->streams[0]->src.width
+				!= set[i].stream->src.width
 				|| set[i].surfaces[0]->clip_rect.height
-				!= set[i].target->streams[0]->src.height)
+				!= set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
@@ -1004,9 +994,9 @@ enum dc_status dce112_validate_with_context(
 	context->res_ctx.pool = dc->res_pool;
 
 	for (i = 0; i < set_count; i++) {
-		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-		dc_target_retain(&context->targets[i]->public);
-		context->target_count++;
+		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
+		dc_stream_retain(&context->streams[i]->public);
+		context->stream_count++;
 	}
 
 	result = resource_map_pool_resources(dc, context);
@@ -1016,7 +1006,7 @@ enum dc_status dce112_validate_with_context(
 
 	if (!resource_validate_attach_surfaces(
 			set, set_count, dc->current_context, context)) {
-		DC_ERROR("Failed to attach surface to target!\n");
+		DC_ERROR("Failed to attach surface to stream!\n");
 		return DC_FAIL_ATTACH_SURFACES;
 	}
 
@@ -1034,16 +1024,16 @@ enum dc_status dce112_validate_with_context(
 
 enum dc_status dce112_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_target *dc_target,
+		const struct dc_stream *dc_stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
 	context->res_ctx.pool = dc->res_pool;
 
-	context->targets[0] = DC_TARGET_TO_CORE(dc_target);
-	dc_target_retain(&context->targets[0]->public);
-	context->target_count++;
+	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
+	dc_stream_retain(&context->streams[0]->public);
+	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context);
 
@@ -1054,8 +1044,8 @@ enum dc_status dce112_validate_guaranteed(
 		result = validate_mapped_resource(dc, context);
 
 	if (result == DC_OK) {
-		validate_guaranteed_copy_target(
-				context, dc->public.caps.max_targets);
+		validate_guaranteed_copy_streams(
+				context, dc->public.caps.max_streams);
 		result = resource_build_scaling_params_for_context(dc, context);
 	}
 

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h

@@ -43,7 +43,7 @@ enum dc_status dce112_validate_with_context(
 
 enum dc_status dce112_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_target *dc_target,
+		const struct dc_stream *dc_stream,
 		struct validate_context *context);
 
 enum dc_status dce112_validate_bandwidth(

drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

@@ -731,54 +731,49 @@ static enum dc_status validate_mapped_resource(
 		struct validate_context *context)
 {
 	enum dc_status status = DC_OK;
-	uint8_t i, j, k;
+	uint8_t i, j;
 
-	for (i = 0; i < context->target_count; i++) {
-		struct core_target *target = context->targets[i];
+	for (i = 0; i < context->stream_count; i++) {
+		struct core_stream *stream = context->streams[i];
+		struct core_link *link = stream->sink->link;
 
-		for (j = 0; j < target->public.stream_count; j++) {
-			struct core_stream *stream =
-				DC_STREAM_TO_CORE(target->public.streams[j]);
-			struct core_link *link = stream->sink->link;
-
-			if (resource_is_stream_unchanged(dc->current_context, stream))
-				continue;
+		if (resource_is_stream_unchanged(dc->current_context, stream))
+			continue;
 
-			for (k = 0; k < MAX_PIPES; k++) {
-				struct pipe_ctx *pipe_ctx =
-					&context->res_ctx.pipe_ctx[k];
+		for (j = 0; j < MAX_PIPES; j++) {
+			struct pipe_ctx *pipe_ctx =
+				&context->res_ctx.pipe_ctx[j];
 
-				if (context->res_ctx.pipe_ctx[k].stream != stream)
-					continue;
+			if (context->res_ctx.pipe_ctx[j].stream != stream)
+				continue;
 
-				if (!pipe_ctx->tg->funcs->validate_timing(
-						pipe_ctx->tg, &stream->public.timing))
-					return DC_FAIL_CONTROLLER_VALIDATE;
+			if (!pipe_ctx->tg->funcs->validate_timing(
+				pipe_ctx->tg, &stream->public.timing))
+				return DC_FAIL_CONTROLLER_VALIDATE;
 
-				status = dce110_resource_build_pipe_hw_param(pipe_ctx);
+			status = dce110_resource_build_pipe_hw_param(pipe_ctx);
 
-				if (status != DC_OK)
-					return status;
+			if (status != DC_OK)
+				return status;
 
-				if (!link->link_enc->funcs->validate_output_with_stream(
-						link->link_enc,
-						pipe_ctx))
-					return DC_FAIL_ENC_VALIDATE;
+			if (!link->link_enc->funcs->validate_output_with_stream(
+				link->link_enc,
+				pipe_ctx))
+				return DC_FAIL_ENC_VALIDATE;
 
-				/* TODO: validate audio ASIC caps, encoder */
+			/* TODO: validate audio ASIC caps, encoder */
 
-				status = dc_link_validate_mode_timing(stream,
-						link,
-						&stream->public.timing);
+			status = dc_link_validate_mode_timing(stream,
+							      link,
+							      &stream->public.timing);
 
-				if (status != DC_OK)
-					return status;
+			if (status != DC_OK)
+				return status;
 
-				resource_build_info_frame(pipe_ctx);
+			resource_build_info_frame(pipe_ctx);
 
-				/* do not need to validate non root pipes */
-				break;
-			}
+			/* do not need to validate non root pipes */
+			break;
 		}
 	}
 
@@ -810,9 +805,9 @@ static bool dce80_validate_surface_sets(
 			return false;
 
 		if (set[i].surfaces[0]->clip_rect.width
-				!= set[i].target->streams[0]->src.width
+				!= set[i].stream->src.width
 				|| set[i].surfaces[0]->clip_rect.height
-				!= set[i].target->streams[0]->src.height)
+				!= set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
@@ -838,9 +833,9 @@ enum dc_status dce80_validate_with_context(
 	context->res_ctx.pool = dc->res_pool;
 
 	for (i = 0; i < set_count; i++) {
-		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-		dc_target_retain(&context->targets[i]->public);
-		context->target_count++;
+		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
+		dc_stream_retain(&context->streams[i]->public);
+		context->stream_count++;
 	}
 
 	result = resource_map_pool_resources(dc, context);
@@ -850,7 +845,7 @@ enum dc_status dce80_validate_with_context(
 
 	if (!resource_validate_attach_surfaces(
 			set, set_count, dc->current_context, context)) {
-		DC_ERROR("Failed to attach surface to target!\n");
+		DC_ERROR("Failed to attach surface to stream!\n");
 		return DC_FAIL_ATTACH_SURFACES;
 	}
 
@@ -868,16 +863,16 @@ enum dc_status dce80_validate_with_context(
 
 enum dc_status dce80_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_target *dc_target,
+		const struct dc_stream *dc_stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
 	context->res_ctx.pool = dc->res_pool;
 
-	context->targets[0] = DC_TARGET_TO_CORE(dc_target);
-	dc_target_retain(&context->targets[0]->public);
-	context->target_count++;
+	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
+	dc_stream_retain(&context->streams[0]->public);
+	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context);
 
@@ -888,8 +883,8 @@ enum dc_status dce80_validate_guaranteed(
 		result = validate_mapped_resource(dc, context);
 
 	if (result == DC_OK) {
-		validate_guaranteed_copy_target(
-				context, dc->public.caps.max_targets);
+		validate_guaranteed_copy_streams(
+				context, dc->public.caps.max_streams);
 		result = resource_build_scaling_params_for_context(dc, context);
 	}
 

drivers/gpu/drm/amd/display/dc/inc/core_dc.h

@@ -21,7 +21,6 @@ struct core_dc {
 	uint8_t link_count;
 	struct core_link *links[MAX_PIPES * 2];
 
-	/* TODO: determine max number of targets*/
 	struct validate_context *current_context;
 	struct validate_context *temp_flip_context;
 	struct validate_context *scratch_val_ctx;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

@@ -32,21 +32,10 @@
 #include "dc_bios_types.h"
 
 struct core_stream;
-/********* core_target *************/
-
-#define CONST_DC_TARGET_TO_CORE(dc_target) \
-	container_of(dc_target, const struct core_target, public)
-#define DC_TARGET_TO_CORE(dc_target) \
-	container_of(dc_target, struct core_target, public)
 
 #define MAX_PIPES 6
 #define MAX_CLOCK_SOURCES 7
 
-struct core_target {
-	struct dc_target public;
-
-	struct dc_context *ctx;
-};
 
 /********* core_surface **********/
 #define DC_SURFACE_TO_CORE(dc_surface) \
@@ -215,7 +204,7 @@ struct resource_funcs {
 
 	enum dc_status (*validate_guaranteed)(
 					const struct core_dc *dc,
-					const struct dc_target *dc_target,
+					const struct dc_stream *stream,
 					struct validate_context *context);
 
 	enum dc_status (*validate_bandwidth)(
@@ -312,9 +301,9 @@ struct resource_context {
  };
 
 struct validate_context {
-	struct core_target *targets[MAX_PIPES];
-	struct dc_target_status target_status[MAX_PIPES];
-	uint8_t target_count;
+	struct core_stream *streams[MAX_PIPES];
+	struct dc_stream_status stream_status[MAX_PIPES];
+	uint8_t stream_count;
 
 	struct resource_context res_ctx;
 

drivers/gpu/drm/amd/display/dc/inc/resource.h

@@ -118,25 +118,26 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
 bool resource_attach_surfaces_to_context(
 		const struct dc_surface *const *surfaces,
 		int surface_count,
-		const struct dc_target *dc_target,
+		const struct dc_stream *dc_stream,
 		struct validate_context *context);
 
 struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx);
 
 bool resource_is_stream_unchanged(
-	const struct validate_context *old_context, struct core_stream *stream);
+	const struct validate_context *old_context, const struct core_stream *stream);
+
+bool is_stream_unchanged(
+	const struct core_stream *old_stream, const struct core_stream *stream);
 
-bool is_target_unchanged(
-	const struct core_target *old_target, const struct core_target *target);
 bool resource_validate_attach_surfaces(
 		const struct dc_validation_set set[],
 		int set_count,
 		const struct validate_context *old_context,
 		struct validate_context *context);
 
-void validate_guaranteed_copy_target(
+void validate_guaranteed_copy_streams(
 		struct validate_context *context,
-		int max_targets);
+		int max_streams);
 
 void resource_validate_ctx_update_pointer_after_copy(
 		const struct validate_context *src_ctx,