Commit ab8eb7db authored by Eugeniy Paltsev's avatar Eugeniy Paltsev Committed by Vineet Gupta

ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset

DW ethernet controller on HSDK hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.
Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent edb40d74
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/reset/snps,hsdk-reset.h>
/ { / {
model = "snps,hsdk"; model = "snps,hsdk";
...@@ -102,6 +103,12 @@ soc { ...@@ -102,6 +103,12 @@ soc {
ranges = <0x00000000 0xf0000000 0x10000000>; ranges = <0x00000000 0xf0000000 0x10000000>;
cgu_rst: reset-controller@8a0 {
compatible = "snps,hsdk-reset";
#reset-cells = <1>;
reg = <0x8A0 0x4>, <0xFF0 0x4>;
};
core_clk: core-clk@0 { core_clk: core-clk@0 {
compatible = "snps,hsdk-core-pll-clock"; compatible = "snps,hsdk-core-pll-clock";
reg = <0x00 0x10>, <0x14B8 0x4>; reg = <0x00 0x10>, <0x14B8 0x4>;
...@@ -158,6 +165,8 @@ ethernet@8000 { ...@@ -158,6 +165,8 @@ ethernet@8000 {
clocks = <&gmacclk>; clocks = <&gmacclk>;
clock-names = "stmmaceth"; clock-names = "stmmaceth";
phy-handle = <&phy0>; phy-handle = <&phy0>;
resets = <&cgu_rst HSDK_ETH_RESET>;
reset-names = "stmmaceth";
mdio { mdio {
#address-cells = <1>; #address-cells = <1>;
......
...@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y ...@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y CONFIG_MMC_DW=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
CONFIG_RESET_HSDK=y
CONFIG_EXT3_FS=y CONFIG_EXT3_FS=y
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_TMPFS=y CONFIG_TMPFS=y
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment