Commit abd9d66a authored by Ankit Nautiyal's avatar Ankit Nautiyal Committed by Rodrigo Vivi

drm/i915/display: Fix the 12 BPC bits for PIPE_MISC reg

Till DISPLAY12 the PIPE_MISC bits 5-7 are used to set the
Dithering BPC, with valid values of 6, 8, 10 BPC.
For ADLP+ these bits are used to set the PORT OUTPUT BPC, with valid
values of: 6, 8, 10, 12 BPC, and need to be programmed whether
dithering is enabled or not.

This patch:
-corrects the bits 5-7 for PIPE MISC register for 12 BPC.
-renames the bits and mask to have generic names for these bits for
dithering bpc and port output bpc.

v3: Added a note for MIPI DSI which uses the PIPE_MISC for readout
for pipe_bpp. (Uma Shankar)

v2: Added 'display' to the subject and fixes tag. (Uma Shankar)

Fixes: 756f85cf ("drm/i915/bdw: Broadwell has PIPEMISC")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Cc: <stable@vger.kernel.org> # v3.13+
Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210811051857.109723-1-ankit.k.nautiyal@intel.com
(cherry picked from commit 70418a68)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent d927ae73
...@@ -5746,16 +5746,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) ...@@ -5746,16 +5746,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
switch (crtc_state->pipe_bpp) { switch (crtc_state->pipe_bpp) {
case 18: case 18:
val |= PIPEMISC_DITHER_6_BPC; val |= PIPEMISC_6_BPC;
break; break;
case 24: case 24:
val |= PIPEMISC_DITHER_8_BPC; val |= PIPEMISC_8_BPC;
break; break;
case 30: case 30:
val |= PIPEMISC_DITHER_10_BPC; val |= PIPEMISC_10_BPC;
break; break;
case 36: case 36:
val |= PIPEMISC_DITHER_12_BPC; /* Port output 12BPC defined for ADLP+ */
if (DISPLAY_VER(dev_priv) > 12)
val |= PIPEMISC_12_BPC_ADLP;
break; break;
default: default:
MISSING_CASE(crtc_state->pipe_bpp); MISSING_CASE(crtc_state->pipe_bpp);
...@@ -5808,15 +5810,27 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) ...@@ -5808,15 +5810,27 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
switch (tmp & PIPEMISC_DITHER_BPC_MASK) { switch (tmp & PIPEMISC_BPC_MASK) {
case PIPEMISC_DITHER_6_BPC: case PIPEMISC_6_BPC:
return 18; return 18;
case PIPEMISC_DITHER_8_BPC: case PIPEMISC_8_BPC:
return 24; return 24;
case PIPEMISC_DITHER_10_BPC: case PIPEMISC_10_BPC:
return 30; return 30;
case PIPEMISC_DITHER_12_BPC: /*
return 36; * PORT OUTPUT 12 BPC defined for ADLP+.
*
* TODO:
* For previous platforms with DSI interface, bits 5:7
* are used for storing pipe_bpp irrespective of dithering.
* Since the value of 12 BPC is not defined for these bits
* on older platforms, need to find a workaround for 12 BPC
* MIPI DSI HW readout.
*/
case PIPEMISC_12_BPC_ADLP:
if (DISPLAY_VER(dev_priv) > 12)
return 36;
fallthrough;
default: default:
MISSING_CASE(tmp); MISSING_CASE(tmp);
return 0; return 0;
......
...@@ -6163,11 +6163,17 @@ enum { ...@@ -6163,11 +6163,17 @@ enum {
#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
#define PIPEMISC_DITHER_BPC_MASK (7 << 5) /*
#define PIPEMISC_DITHER_8_BPC (0 << 5) * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
#define PIPEMISC_DITHER_10_BPC (1 << 5) * valid values of: 6, 8, 10 BPC.
#define PIPEMISC_DITHER_6_BPC (2 << 5) * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
#define PIPEMISC_DITHER_12_BPC (3 << 5) * 6, 8, 10, 12 BPC.
*/
#define PIPEMISC_BPC_MASK (7 << 5)
#define PIPEMISC_8_BPC (0 << 5)
#define PIPEMISC_10_BPC (1 << 5)
#define PIPEMISC_6_BPC (2 << 5)
#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */
#define PIPEMISC_DITHER_ENABLE (1 << 4) #define PIPEMISC_DITHER_ENABLE (1 << 4)
#define PIPEMISC_DITHER_TYPE_MASK (3 << 2) #define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
#define PIPEMISC_DITHER_TYPE_SP (0 << 2) #define PIPEMISC_DITHER_TYPE_SP (0 << 2)
......
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