Commit afbaa155 authored by Victor Zhao's avatar Victor Zhao Committed by Alex Deucher

Revert "drm/amdgpu: add debugfs amdgpu_reset_level"

This reverts commit 5bd8d53f.

This commit breaks the reset logic for aldebaran, revert it for now.
Will move the mask inside the reset handler.

Fixes: 5bd8d53f ("drm/amdgpu: add debugfs amdgpu_reset_level")
Signed-off-by: default avatarVictor Zhao <Victor.Zhao@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 65f8682b
...@@ -274,9 +274,6 @@ extern int amdgpu_vcnfw_log; ...@@ -274,9 +274,6 @@ extern int amdgpu_vcnfw_log;
#define AMDGPU_RESET_VCE (1 << 13) #define AMDGPU_RESET_VCE (1 << 13)
#define AMDGPU_RESET_VCE1 (1 << 14) #define AMDGPU_RESET_VCE1 (1 << 14)
#define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0)
#define AMDGPU_RESET_LEVEL_MODE2 (1 << 1)
/* max cursor sizes (in pixels) */ /* max cursor sizes (in pixels) */
#define CIK_CURSOR_WIDTH 128 #define CIK_CURSOR_WIDTH 128
#define CIK_CURSOR_HEIGHT 128 #define CIK_CURSOR_HEIGHT 128
...@@ -1065,7 +1062,6 @@ struct amdgpu_device { ...@@ -1065,7 +1062,6 @@ struct amdgpu_device {
struct work_struct reset_work; struct work_struct reset_work;
uint32_t amdgpu_reset_level_mask;
bool job_hang; bool job_hang;
}; };
......
...@@ -1954,8 +1954,6 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) ...@@ -1954,8 +1954,6 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
return PTR_ERR(ent); return PTR_ERR(ent);
} }
debugfs_create_u32("amdgpu_reset_level", 0600, root, &adev->amdgpu_reset_level_mask);
/* Register debugfs entries for amdgpu_ttm */ /* Register debugfs entries for amdgpu_ttm */
amdgpu_ttm_debugfs_init(adev); amdgpu_ttm_debugfs_init(adev);
amdgpu_debugfs_pm_init(adev); amdgpu_debugfs_pm_init(adev);
......
...@@ -37,8 +37,6 @@ int amdgpu_reset_init(struct amdgpu_device *adev) ...@@ -37,8 +37,6 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
{ {
int ret = 0; int ret = 0;
adev->amdgpu_reset_level_mask = 0x1;
switch (adev->ip_versions[MP1_HWIP][0]) { switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 2): case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_init(adev); ret = aldebaran_reset_init(adev);
...@@ -76,9 +74,6 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev, ...@@ -76,9 +74,6 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
{ {
struct amdgpu_reset_handler *reset_handler = NULL; struct amdgpu_reset_handler *reset_handler = NULL;
if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
return -ENOSYS;
if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags)) if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags))
return -ENOSYS; return -ENOSYS;
...@@ -98,9 +93,6 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev, ...@@ -98,9 +93,6 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
int ret; int ret;
struct amdgpu_reset_handler *reset_handler = NULL; struct amdgpu_reset_handler *reset_handler = NULL;
if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
return -ENOSYS;
if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags)) if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags))
return -ENOSYS; return -ENOSYS;
......
...@@ -405,9 +405,6 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, ...@@ -405,9 +405,6 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
{ {
ktime_t deadline = ktime_add_us(ktime_get(), 10000); ktime_t deadline = ktime_add_us(ktime_get(), 10000);
if (!(ring->adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_SOFT_RECOVERY))
return false;
if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
return false; return false;
......
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