Commit b15d5380 authored by Alexey Brodkin's avatar Alexey Brodkin Committed by Greg Kroah-Hartman

serial/8250/8250_early: Prevent rounding error in uartclk

Modify divisor to select the nearest baud rate divider rather than the
lowest. It minimizes baud rate errors especially on low UART clock
frequencies.

For example, if uartclk is 33000000 and baud is 115200 the ratio is
about 17.9 The current code selects 17 (5% error) but should select 18
(0.5% error).

This 5% error in baud rate leads to garbage on receiving end, while 0.5%
doesn't.

The issue showed up when using the stock 8250 driver for
Synopsys DW UART. This was on a FPGA with ~12MHz UART clock.
When we enabled early serial, we saw garbage which was narrowed down
to the rounding error.

So the bug had been latent and it only showed up with such low clock rates.
Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
Acked-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 9484b009
......@@ -140,7 +140,7 @@ static void __init init_port(struct early_serial8250_device *device)
serial_out(port, UART_FCR, 0); /* no fifo */
serial_out(port, UART_MCR, 0x3); /* DTR + RTS */
divisor = port->uartclk / (16 * device->baud);
divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * device->baud);
c = serial_in(port, UART_LCR);
serial_out(port, UART_LCR, c | UART_LCR_DLAB);
serial_out(port, UART_DLL, divisor & 0xff);
......
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