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Commit b217a721 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'imx-dt64-5.1' of... 

Merge tag 'imx-dt64-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree changes for 5.1:
 - Add initial i.MX8QXP SoC and MEK board support.
 - Various device additions to i.MX8MQ SoC and EVK board support:
   RTC, QuadSPI, PMU, ECSPI, PWM, GPC power domain, USB etc.
 - Use generic node name for m25p80 flash on layerscape devices.
 - Add num-viewport property for layerscape PCIe devices, and
   incr-burst-type-adjustment for USB3 devices.
 - Add LS1012AX based Oxalis board support.
 - Add fsl-mc, FlexSPI device and dma-ranges property for LX2160A SoC.
 - Add SMMU device and missing dma-coherent property in fsl-mc for
   LS1088 SoC.

* tag 'imx-dt64-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (30 commits)
  arm64: dts: imx8mq: specify dma-ranges
  arm64: dts: imx8mq: Add ARM PMU node
  arm64: dts: imx8mq: Add RTC support
  arm64: dts: imx8mq-evk: Enable the QuadSPI controller
  arm64: dts: imx8mq: Add QuadSPI controller
  arm64: dts: imx8mq: Add ECSPI support
  arm64: dts: imx8mq-evk: Add fsl,magic-packet property
  arm64: dts: imx8mq-evk: add missing MDIO / PHY nodes
  arm64: dts: imx8mq-evk: enable USB nodes for USB3 host
  arm64: dts: imx8mq: add USB nodes
  arm64: dts: imx8mq: properly describe IRQ hierarchy
  arm64: dts: lx2160a: update fspi node
  arm64: dts: freescale: Add devicetree for Oxalis
  arm64: dts: lx2160a: add FlexSPI node property
  arm64: dts: imx8qxp: Fix MU4_INT number
  arm64: dts: imx8mq: add GPC power domains
  arm64: dts: imx8mq: Add pwm device nodes
  arm64: dts: imx: add i.MX8QXP system controller RTC support
  arm64: dts: imx: add imx8qxp mek support
  arm64: dts: imx: add imx8qxp support
  ...
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 42d61413 ca04fed4
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Showing with 1292 additions and 29 deletions
arch/arm64/boot/dts/freescale/Makefile
View file @ b217a721
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
......@@ -20,3 +21,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts 0 → 100644
View file @ b217a721
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Oxalis
*
* Copyright (c) 2019 Manivannan Sadhasivam
*
*/
/dts-v1/;
#include "fsl-ls1012a.dtsi"
/ {
model = "Oxalis";
compatible = "ebs-systart,oxalis", "fsl,ls1012a";
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&sai2>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&codec>;
frame-master;
bitclock-master;
system-clock-frequency = <25000000>;
};
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&i2c0 {
status = "okay";
codec: audio-codec@a {
#sound-dai-cells = <0>;
compatible = "fsl,sgtl5000";
reg = <0xa>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_1p8v>;
clocks = <&sys_mclk>;
};
};
&i2c1 {
status = "okay";
};
&sai2 {
status = "okay";
};
&sata {
status = "okay";
};
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View file @ b217a721
......@@ -446,6 +446,7 @@ usb0: usb3@2f00000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
sata: sata@3200000 {
......@@ -486,6 +487,7 @@ pcie@3400000 {
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <2>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
View file @ b217a721
......@@ -137,7 +137,7 @@ &lpuart0 {
&qspi {
status = "okay";
qflash0: s25fl128s@0 {
qflash0: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View file @ b217a721
......@@ -611,6 +611,7 @@ usb0: usb3@2f00000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb3@3000000 {
......@@ -620,6 +621,7 @@ usb1: usb3@3000000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb2: usb3@3100000 {
......@@ -629,6 +631,7 @@ usb2: usb3@3100000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
sata: sata@3200000 {
......@@ -675,6 +678,7 @@ pcie@3400000 {
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......@@ -701,6 +705,7 @@ pcie@3500000 {
device_type = "pci";
dma-coherent;
num-lanes = <2>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......@@ -727,6 +732,7 @@ pcie@3600000 {
device_type = "pci";
dma-coherent;
num-lanes = <2>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
View file @ b217a721
......@@ -165,7 +165,7 @@ &lpuart0 {
&qspi {
status = "okay";
qflash0: s25fl128s@0 {
qflash0: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
View file @ b217a721
......@@ -101,7 +101,7 @@ cpld: board-control@2,0 {
&qspi {
status = "okay";
qflash0: s25fs512s@0 {
qflash0: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
......@@ -111,7 +111,7 @@ qflash0: s25fs512s@0 {
reg = <0>;
};
qflash1: s25fs512s@1 {
qflash1: flash@1 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View file @ b217a721
......@@ -202,6 +202,7 @@ ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
qspi: spi@1550000 {
......@@ -424,6 +425,7 @@ duart0: serial@21c0500 {
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
duart1: serial@21c0600 {
......@@ -431,6 +433,7 @@ duart1: serial@21c0600 {
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
duart2: serial@21d0500 {
......@@ -438,6 +441,7 @@ duart2: serial@21d0500 {
reg = <0x0 0x21d0500 0x0 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
duart3: serial@21d0600 {
......@@ -445,6 +449,7 @@ duart3: serial@21d0600 {
reg = <0x0 0x21d0600 0x0 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
gpio0: gpio@2300000 {
......@@ -572,6 +577,7 @@ usb0: usb@2f00000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb@3000000 {
......@@ -581,6 +587,7 @@ usb1: usb@3000000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb2: usb@3100000 {
......@@ -590,6 +597,7 @@ usb2: usb@3100000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
sata: sata@3200000 {
......@@ -644,6 +652,7 @@ pcie@3400000 {
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......@@ -670,6 +679,7 @@ pcie@3500000 {
device_type = "pci";
dma-coherent;
num-lanes = <2>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......@@ -696,6 +706,7 @@ pcie@3600000 {
device_type = "pci";
dma-coherent;
num-lanes = <2>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View file @ b217a721
......@@ -377,6 +377,7 @@ usb0: usb3@3100000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
......@@ -452,6 +453,7 @@ pcie@3400000 {
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <256>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......@@ -477,6 +479,7 @@ pcie@3500000 {
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......@@ -502,6 +505,7 @@ pcie@3600000 {
device_type = "pci";
dma-coherent;
num-lanes = <8>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
......@@ -515,6 +519,96 @@ pcie@3600000 {
status = "disabled";
};
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
#iommu-cells = <1>;
stream-match-mask = <0x7C00>;
#global-interrupts = <12>;
// global secure fault
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
// combined secure
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
// global non-secure fault
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
// combined non-secure
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
// performance counter interrupts 0-7
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
// per context interrupt, 64 interrupts
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
};
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
......@@ -576,6 +670,8 @@ fsl_mc: fsl-mc@80c000000 {
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
msi-parent = <&its>;
iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
dma-coherent;
#address-cells = <3>;
#size-cells = <1>;
......@@ -649,5 +745,4 @@ optee {
method = "smc";
};
};
};
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View file @ b217a721
......@@ -627,6 +627,7 @@ pcie1: pcie@3400000 {
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
......@@ -648,6 +649,7 @@ pcie2: pcie@3500000 {
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
......@@ -669,6 +671,7 @@ pcie3: pcie@3600000 {
device_type = "pci";
dma-coherent;
num-lanes = <8>;
num-viewport = <256>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
......@@ -690,6 +693,7 @@ pcie4: pcie@3700000 {
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
......@@ -727,6 +731,7 @@ usb0: usb3@3100000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb3@3110000 {
......@@ -737,6 +742,7 @@ usb1: usb3@3110000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
ccn@4000000 {
......
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
View file @ b217a721
......@@ -50,6 +50,32 @@ &esdhc1 {
status = "okay";
};
&fspi {
status = "okay";
mt35xu512aba0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
m25p,fast-read;
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
m25p,fast-read;
spi-max-frequency = <50000000>;
reg = <1>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <8>;
};
};
&i2c0 {
status = "okay";
......
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View file @ b217a721
......@@ -398,6 +398,7 @@ soc {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
......@@ -542,6 +543,19 @@ i2c7: i2c@2070000 {
status = "disabled";
};
fspi: spi@20c0000 {
compatible = "nxp,lx2160a-fspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
......@@ -658,6 +672,7 @@ usb0: usb@3100000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
......@@ -668,6 +683,7 @@ usb1: usb@3110000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
......@@ -762,5 +778,122 @@ smmu: iommu@5000000 {
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,
<0x00000000 0x08340000 0 0x40000>;
msi-parent = <&its>;
/* iommu-map property is fixed up by u-boot */
iommu-map = <0 &smmu 0 0>;
dma-coherent;
#address-cells = <3>;
#size-cells = <1>;
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
/*
* Define the maximum number of MACs present on the SoC.
*/
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x1>;
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x2>;
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
};
dpmac4: dpmac@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x4>;
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x5>;
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x6>;
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x7>;
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x8>;
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x9>;
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
};
dpmac11: dpmac@b {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xb>;
};
dpmac12: dpmac@c {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xc>;
};
dpmac13: dpmac@d {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xd>;
};
dpmac14: dpmac@e {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xe>;
};
dpmac15: dpmac@f {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xf>;
};
dpmac16: dpmac@10 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x10>;
};
dpmac17: dpmac@11 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x11>;
};
dpmac18: dpmac@12 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x12>;
};
};
};
};
};
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View file @ b217a721
......@@ -37,7 +37,19 @@ &fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&i2c1 {
......@@ -137,6 +149,29 @@ &uart1 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
n25q256a: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
......@@ -195,6 +230,18 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
......
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View file @ b217a721
This diff is collapsed.
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts 0 → 100644
View file @ b217a721
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017~2018 NXP
*/
/dts-v1/;
#include "imx8qxp.dtsi"
/ {
model = "Freescale i.MX8QXP MEK";
compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
chosen {
stdout-path = &adma_lpuart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adma_lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
};
arch/arm64/boot/dts/freescale/imx8qxp.dtsi 0 → 100644
View file @ b217a721
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