Commit b2a6cf3b authored by Ben Dooks's avatar Ben Dooks

[ARM] S3C24XX: Default SPI pin configuration for SPI

Add a set of default pin configuration routines for
setting up the SPI gpio configuration when using the
hardware SPI driver.
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent 72aaf09f
...@@ -22,5 +22,12 @@ struct s3c2410_spi_info { ...@@ -22,5 +22,12 @@ struct s3c2410_spi_info {
void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
}; };
/* Standard setup / suspend routines for SPI GPIO pins. */
extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
int enable);
extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
int enable);
#endif /* __ASM_ARCH_SPI_H */ #endif /* __ASM_ARCH_SPI_H */
...@@ -49,6 +49,22 @@ config S3C2410_DMA_DEBUG ...@@ -49,6 +49,22 @@ config S3C2410_DMA_DEBUG
Enable debugging output for the DMA code. This option sends info Enable debugging output for the DMA code. This option sends info
to the kernel log, at priority KERN_DEBUG. to the kernel log, at priority KERN_DEBUG.
# SPI default pin configuration code
config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
bool
help
SPI GPIO configuration code for BUS0 when connected to
GPE11, GPE12 and GPE13.
config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
bool
help
SPI GPIO configuration code for BUS 1 when connected to
GPG5, GPG6 and GPG7.
# common code for s3c24xx based machines, such as the SMDKs.
config MACH_SMDK config MACH_SMDK
bool bool
help help
......
...@@ -31,4 +31,12 @@ obj-$(CONFIG_PM) += pm.o ...@@ -31,4 +31,12 @@ obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_HAVE_PWM) += pwm.o obj-$(CONFIG_HAVE_PWM) += pwm.o
obj-$(CONFIG_S3C2410_DMA) += dma.o obj-$(CONFIG_S3C2410_DMA) += dma.o
# SPI gpio central GPIO functions
obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o
# machine common support
obj-$(CONFIG_MACH_SMDK) += common-smdk.o obj-$(CONFIG_MACH_SMDK) += common-smdk.o
/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/spi.h>
#include <mach/regs-gpio.h>
void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
int enable)
{
if (enable) {
s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
s3c2410_gpio_pullup(S3C2410_GPE11, 0);
s3c2410_gpio_pullup(S3C2410_GPE13, 0);
} else {
s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPE11, 1);
s3c2410_gpio_pullup(S3C2410_GPE12, 1);
s3c2410_gpio_pullup(S3C2410_GPE13, 1);
}
}
/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/spi.h>
#include <mach/regs-gpio.h>
void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
int enable)
{
if (enable) {
s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
s3c2410_gpio_pullup(S3C2410_GPG5, 0);
s3c2410_gpio_pullup(S3C2410_GPG6, 0);
} else {
s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPG5, 1);
s3c2410_gpio_pullup(S3C2410_GPG6, 1);
s3c2410_gpio_pullup(S3C2410_GPG7, 1);
}
}
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