Commit b598a404 authored by Jeb J. Cramer's avatar Jeb J. Cramer Committed by Jeff Garzik

e1000 9/10:

* Added bullets to changelog 
* Whitespace cleanup 
parent 4ab38cc7
......@@ -47,9 +47,9 @@ static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count);
static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw);
static void e1000_setup_eeprom(struct e1000_hw *hw);
static void e1000_standby_eeprom(struct e1000_hw *hw);
static void e1000_clock_eeprom(struct e1000_hw *hw);
static void e1000_cleanup_eeprom(struct e1000_hw *hw);
static void e1000_standby_eeprom(struct e1000_hw *hw);
static int32_t e1000_id_led_init(struct e1000_hw * hw);
/******************************************************************************
......@@ -1014,7 +1014,6 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
/* Write the configured values back to the Device Control Reg. */
E1000_WRITE_REG(hw, CTRL, ctrl);
/* Write the MII Control Register with the new PHY configuration. */
if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
......@@ -1029,9 +1028,11 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
return -E1000_ERR_PHY;
}
DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
/* Need to reset the PHY or these changes will be ignored */
mii_ctrl_reg |= MII_CR_RESET;
/* Write back the modified PHY MII control register. */
if(e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
DEBUGOUT("PHY Write Error\n");
return -E1000_ERR_PHY;
......@@ -2249,7 +2250,7 @@ e1000_raise_ee_clk(struct e1000_hw *hw,
uint32_t *eecd)
{
/* Raise the clock input to the EEPROM (by setting the SK bit), and then
* wait 50 microseconds.
* wait <delay> microseconds.
*/
*eecd = *eecd | E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, *eecd);
......@@ -2338,11 +2339,11 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw)
uint32_t i;
uint16_t data;
/* In order to read a register from the EEPROM, we need to shift 16 bits
* in from the EEPROM. Bits are "shifted in" by raising the clock input to
* the EEPROM (setting the SK bit), and then reading the value of the "DO"
* bit. During this "shifting in" process the "DI" bit should always be
* clear..
/* In order to read a register from the EEPROM, we need to shift 'count'
* bits in from the EEPROM. Bits are "shifted in" by raising the clock
* input to the EEPROM (setting the SK bit), and then reading the value of
* the "DO" bit. During this "shifting in" process the "DI" bit should
* always be clear.
*/
eecd = E1000_READ_REG(hw, EECD);
......
......@@ -30,6 +30,19 @@
#include "e1000.h"
/* Change Log
*
* 4.4.12 10/15/02
* o Clean up: use members of pci_device rather than direct calls to
* pci_read_config_word.
* o Bug fix: changed default flow control settings.
* o Clean up: ethtool file now has an inclusive list for adapters in the
* Wake-On-LAN capabilities instead of an exclusive list.
* o Bug fix: miscellaneous WoL bug fixes.
* o Added software interrupt for clearing rx ring
* o Bug fix: easier to undo "forcing" of 1000/fd using ethtool.
* o Now setting netdev->mem_end in e1000_probe.
* o Clean up: Moved tx_timeout from interrupt context to process context
* using schedule_task.
*
* o Feature: merged in modified NAPI patch from Robert Olsson
* <Robert.Olsson@its.uu.se> Uppsala Univeristy, Sweden.
......@@ -47,26 +60,8 @@
* o Feature: exposed two Tx and one Rx interrupt delay knobs for finer
* control over interurpt rate tuning.
* o Misc ethtool bug fixes.
*
* 4.3.2 7/5/02
* o Bug fix: perform controller reset using I/O rather than mmio because
* some chipsets try to perform a 64-bit write, but the controller ignores
* the upper 32-bit write once the reset is intiated by the lower 32-bit
* write, causing a master abort.
* o Bug fix: fixed jumbo frames sized from 1514 to 2048.
* o ASF support: disable ARP when driver is loaded or resumed; enable when
* driver is removed or suspended.
* o Bug fix: changed default setting for RxIntDelay to 0 for 82542/3/4
* controllers to workaround h/w errata where controller will hang when
* RxIntDelay <> 0 under certian network conditions.
* o Clean up: removed unused and undocumented user-settable settings for
* PHY.
* o Bug fix: ethtool GEEPROM was using byte address rather than word
* addressing.
* o Feature: added support for ethtool SEEPROM.
* o Feature: added support for entropy pool.
*
* 4.2.17 5/30/02
* 4.3.2 7/5/02
*/
char e1000_driver_name[] = "e1000";
......@@ -543,7 +538,7 @@ e1000_remove(struct pci_dev *pdev)
struct net_device *netdev = pci_get_drvdata(pdev);
struct e1000_adapter *adapter = netdev->priv;
uint32_t manc;
if(adapter->hw.mac_type >= e1000_82540) {
manc = E1000_READ_REG(&adapter->hw, MANC);
if(manc & E1000_MANC_SMBUS_EN) {
......@@ -551,7 +546,7 @@ e1000_remove(struct pci_dev *pdev)
E1000_WRITE_REG(&adapter->hw, MANC, manc);
}
}
unregister_netdev(netdev);
e1000_phy_hw_reset(&adapter->hw);
......@@ -1515,7 +1510,6 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
int f;
count = TXD_USE_COUNT(skb->len - skb->data_len,
adapter->max_data_per_txd);
for(f = 0; f < skb_shinfo(skb)->nr_frags; f++)
......
......@@ -314,7 +314,8 @@ e1000_check_options(struct e1000_adapter *adapter)
};
struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
e1000_mac_type mac_type = adapter->hw.mac_type;
opt.arg.r.max = mac_type < e1000_82544 ? MAX_TXD : MAX_82544_TXD;
opt.arg.r.max = mac_type < e1000_82544 ?
MAX_TXD : MAX_82544_TXD;
tx_ring->count = TxDescriptors[bd];
e1000_validate_option(&tx_ring->count, &opt);
......
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